From 0d04c8cf14050c0aeddc8a896cc20030d15a255f Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Mon, 16 Jul 2012 11:37:15 +0530 Subject: [PATCH] USB: dwc3: Add workaround for incorrect GUCTL register's default value GUCTL[31:22] indicate the time period (in ns) of the reference clock that is used to generate Isochronous Timestamp Packets (ITP). This value should be 8ns (125 MHz) by default. But it is overridden with 0 on cores revision < 2.30a. Fix this in software. CRs-Fixed: 377846 Change-Id: I827540eb9d2f1ffc65b6f30200b6c0e575bc52d2 Signed-off-by: Pavankumar Kondeti --- drivers/usb/dwc3/core.c | 11 +++++++++++ drivers/usb/dwc3/core.h | 3 +++ 2 files changed, 14 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 1fbfdd82041..ff6f490cbf0 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -372,6 +372,17 @@ static int __devinit dwc3_core_init(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GCTL, reg); + /* + * The default value of GUCTL[31:22] should be 0x8. But on cores + * revision < 2.30a, the default value is mistakenly overridden + * with 0x0. Restore the correct default value. + */ + if (dwc->revision < DWC3_REVISION_230A) { + reg = dwc3_readl(dwc->regs, DWC3_GUCTL); + reg &= ~DWC3_GUCTL_REFCLKPER; + reg |= 0x8 << __ffs(DWC3_GUCTL_REFCLKPER); + dwc3_writel(dwc->regs, DWC3_GUCTL, reg); + } /* * Currently, the default and the recommended value for GUSB3PIPECTL * [21:19] in the RTL is 3'b100 or 32 consecutive errors. Based on diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 98adff70d07..d5839f097f8 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -180,6 +180,9 @@ #define DWC3_GCTL_DISSCRAMBLE (1 << 3) #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) +/* Global User Control Register */ +#define DWC3_GUCTL_REFCLKPER (0x3FF << 22) + /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)