[S390] Whitespace cleanup.
Huge s390 assembly files whitespace cleanup. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
Heiko Carstens
committed by
Martin Schwidefsky
Martin Schwidefsky
parent
52149ba6b0
commit
25d83cbfaa
@@ -15,232 +15,232 @@
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# this is called either by the ipl loader or directly by PSW restart
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# or linload or SALIPL
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#
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.org 0x10000
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startup:basr %r13,0 # get base
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.LPG0: l %r13,0f-.LPG0(%r13)
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b 0(%r13)
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0: .long startup_continue
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.org 0x10000
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startup:basr %r13,0 # get base
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.LPG0: l %r13,0f-.LPG0(%r13)
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b 0(%r13)
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0: .long startup_continue
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#
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# params at 10400 (setup.h)
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#
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.org PARMAREA
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.quad 0 # IPL_DEVICE
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.quad 0 # INITRD_START
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.quad 0 # INITRD_SIZE
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.org PARMAREA
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.quad 0 # IPL_DEVICE
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.quad 0 # INITRD_START
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.quad 0 # INITRD_SIZE
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.org COMMAND_LINE
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.byte "root=/dev/ram0 ro"
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.byte 0
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.org COMMAND_LINE
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.byte "root=/dev/ram0 ro"
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.byte 0
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.org 0x11000
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.org 0x11000
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startup_continue:
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basr %r13,0 # get base
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.LPG1: sll %r13,1 # remove high order bit
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srl %r13,1
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lhi %r1,1 # mode 1 = esame
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mvi __LC_AR_MODE_ID,1 # set esame flag
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slr %r0,%r0 # set cpuid to zero
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sigp %r1,%r0,0x12 # switch to esame mode
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sam64 # switch to 64 bit mode
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lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
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lg %r12,.Lparmaddr-.LPG1(%r13)# pointer to parameter area
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# move IPL device to lowcore
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mvc __LC_IPLDEV(4),IPL_DEVICE+4-PARMAREA(%r12)
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basr %r13,0 # get base
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.LPG1: sll %r13,1 # remove high order bit
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srl %r13,1
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lhi %r1,1 # mode 1 = esame
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mvi __LC_AR_MODE_ID,1 # set esame flag
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slr %r0,%r0 # set cpuid to zero
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sigp %r1,%r0,0x12 # switch to esame mode
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sam64 # switch to 64 bit mode
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lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
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lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
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# move IPL device to lowcore
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mvc __LC_IPLDEV(4),IPL_DEVICE+4-PARMAREA(%r12)
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#
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# Setup stack
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#
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larl %r15,init_thread_union
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lg %r14,__TI_task(%r15) # cache current in lowcore
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stg %r14,__LC_CURRENT
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aghi %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE
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stg %r15,__LC_KERNEL_STACK # set end of kernel stack
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aghi %r15,-160
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xc __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15) # clear backchain
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larl %r15,init_thread_union
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lg %r14,__TI_task(%r15) # cache current in lowcore
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stg %r14,__LC_CURRENT
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aghi %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE
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stg %r15,__LC_KERNEL_STACK # set end of kernel stack
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aghi %r15,-160
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xc __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15) # clear backchain
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brasl %r14,ipl_save_parameters
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brasl %r14,ipl_save_parameters
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#
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# clear bss memory
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#
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larl %r2,__bss_start # start of bss segment
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larl %r3,_end # end of bss segment
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sgr %r3,%r2 # length of bss
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sgr %r4,%r4 #
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sgr %r5,%r5 # set src,length and pad to zero
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mvcle %r2,%r4,0 # clear mem
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jo .-4 # branch back, if not finish
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larl %r2,__bss_start # start of bss segment
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larl %r3,_end # end of bss segment
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sgr %r3,%r2 # length of bss
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sgr %r4,%r4 #
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sgr %r5,%r5 # set src,length and pad to zero
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mvcle %r2,%r4,0 # clear mem
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jo .-4 # branch back, if not finish
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l %r2,.Lrcp-.LPG1(%r13) # Read SCP forced command word
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l %r2,.Lrcp-.LPG1(%r13) # Read SCP forced command word
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.Lservicecall:
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stosm .Lpmask-.LPG1(%r13),0x01 # authorize ext interrupts
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stosm .Lpmask-.LPG1(%r13),0x01 # authorize ext interrupts
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stctg %r0,%r0,.Lcr-.LPG1(%r13) # get cr0
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la %r1,0x200 # set bit 22
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og %r1,.Lcr-.LPG1(%r13) # or old cr0 with r1
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stg %r1,.Lcr-.LPG1(%r13)
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lctlg %r0,%r0,.Lcr-.LPG1(%r13) # load modified cr0
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stctg %r0,%r0,.Lcr-.LPG1(%r13) # get cr0
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la %r1,0x200 # set bit 22
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og %r1,.Lcr-.LPG1(%r13) # or old cr0 with r1
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stg %r1,.Lcr-.LPG1(%r13)
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lctlg %r0,%r0,.Lcr-.LPG1(%r13) # load modified cr0
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mvc __LC_EXT_NEW_PSW(8),.Lpcmsk-.LPG1(%r13) # set postcall psw
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larl %r1,.Lsclph
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stg %r1,__LC_EXT_NEW_PSW+8 # set handler
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mvc __LC_EXT_NEW_PSW(8),.Lpcmsk-.LPG1(%r13) # set postcall psw
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larl %r1,.Lsclph
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stg %r1,__LC_EXT_NEW_PSW+8 # set handler
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larl %r4,.Lsccb # %r4 is our index for sccb stuff
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lgr %r1,%r4 # our sccb
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.insn rre,0xb2200000,%r2,%r1 # service call
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ipm %r1
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srl %r1,28 # get cc code
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xr %r3,%r3
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chi %r1,3
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be .Lfchunk-.LPG1(%r13) # leave
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chi %r1,2
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be .Lservicecall-.LPG1(%r13)
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lpswe .Lwaitsclp-.LPG1(%r13)
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larl %r4,.Lsccb # %r4 is our index for sccb stuff
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lgr %r1,%r4 # our sccb
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.insn rre,0xb2200000,%r2,%r1 # service call
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ipm %r1
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srl %r1,28 # get cc code
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xr %r3,%r3
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chi %r1,3
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be .Lfchunk-.LPG1(%r13) # leave
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chi %r1,2
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be .Lservicecall-.LPG1(%r13)
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lpswe .Lwaitsclp-.LPG1(%r13)
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.Lsclph:
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lh %r1,.Lsccbr-.Lsccb(%r4)
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chi %r1,0x10 # 0x0010 is the sucess code
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je .Lprocsccb # let's process the sccb
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chi %r1,0x1f0
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bne .Lfchunk-.LPG1(%r13) # unhandled error code
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c %r2,.Lrcp-.LPG1(%r13) # Did we try Read SCP forced
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bne .Lfchunk-.LPG1(%r13) # if no, give up
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l %r2,.Lrcp2-.LPG1(%r13) # try with Read SCP
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b .Lservicecall-.LPG1(%r13)
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lh %r1,.Lsccbr-.Lsccb(%r4)
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chi %r1,0x10 # 0x0010 is the sucess code
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je .Lprocsccb # let's process the sccb
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chi %r1,0x1f0
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bne .Lfchunk-.LPG1(%r13) # unhandled error code
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c %r2,.Lrcp-.LPG1(%r13) # Did we try Read SCP forced
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bne .Lfchunk-.LPG1(%r13) # if no, give up
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l %r2,.Lrcp2-.LPG1(%r13) # try with Read SCP
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b .Lservicecall-.LPG1(%r13)
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.Lprocsccb:
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lghi %r1,0
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icm %r1,3,.Lscpincr1-.Lsccb(%r4) # use this one if != 0
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jnz .Lscnd
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lg %r1,.Lscpincr2-.Lsccb(%r4) # otherwise use this one
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lghi %r1,0
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icm %r1,3,.Lscpincr1-.Lsccb(%r4) # use this one if != 0
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jnz .Lscnd
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lg %r1,.Lscpincr2-.Lsccb(%r4) # otherwise use this one
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.Lscnd:
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xr %r3,%r3 # same logic
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ic %r3,.Lscpa1-.Lsccb(%r4)
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chi %r3,0x00
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jne .Lcompmem
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l %r3,.Lscpa2-.Lsccb(%r4)
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xr %r3,%r3 # same logic
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ic %r3,.Lscpa1-.Lsccb(%r4)
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chi %r3,0x00
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jne .Lcompmem
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l %r3,.Lscpa2-.Lsccb(%r4)
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.Lcompmem:
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mlgr %r2,%r1 # mem in MB on 128-bit
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l %r1,.Lonemb-.LPG1(%r13)
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mlgr %r2,%r1 # mem size in bytes in %r3
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b .Lfchunk-.LPG1(%r13)
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mlgr %r2,%r1 # mem in MB on 128-bit
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l %r1,.Lonemb-.LPG1(%r13)
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mlgr %r2,%r1 # mem size in bytes in %r3
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b .Lfchunk-.LPG1(%r13)
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.align 4
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.align 4
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.Lpmask:
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.byte 0
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.align 8
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.byte 0
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.align 8
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.Lcr:
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.quad 0x00 # place holder for cr0
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.quad 0x00 # place holder for cr0
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.Lwaitsclp:
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.quad 0x0102000180000000,.Lsclph
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.quad 0x0102000180000000,.Lsclph
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.Lrcp:
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.int 0x00120001 # Read SCP forced code
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.int 0x00120001 # Read SCP forced code
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.Lrcp2:
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.int 0x00020001 # Read SCP code
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.int 0x00020001 # Read SCP code
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.Lonemb:
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.int 0x100000
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.int 0x100000
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.Lfchunk:
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# set program check new psw mask
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mvc __LC_PGM_NEW_PSW(8),.Lpcmsk-.LPG1(%r13)
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# set program check new psw mask
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mvc __LC_PGM_NEW_PSW(8),.Lpcmsk-.LPG1(%r13)
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#
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# find memory chunks.
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#
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lgr %r9,%r3 # end of mem
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larl %r1,.Lchkmem # set program check address
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stg %r1,__LC_PGM_NEW_PSW+8
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la %r1,1 # test in increments of 128KB
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sllg %r1,%r1,17
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larl %r3,memory_chunk
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slgr %r4,%r4 # set start of chunk to zero
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slgr %r5,%r5 # set end of chunk to zero
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slr %r6,%r6 # set access code to zero
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la %r10,MEMORY_CHUNKS # number of chunks
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lgr %r9,%r3 # end of mem
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larl %r1,.Lchkmem # set program check address
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stg %r1,__LC_PGM_NEW_PSW+8
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la %r1,1 # test in increments of 128KB
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sllg %r1,%r1,17
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larl %r3,memory_chunk
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slgr %r4,%r4 # set start of chunk to zero
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slgr %r5,%r5 # set end of chunk to zero
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slr %r6,%r6 # set access code to zero
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la %r10,MEMORY_CHUNKS # number of chunks
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.Lloop:
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tprot 0(%r5),0 # test protection of first byte
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ipm %r7
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srl %r7,28
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clr %r6,%r7 # compare cc with last access code
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je .Lsame
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j .Lchkmem
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tprot 0(%r5),0 # test protection of first byte
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ipm %r7
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srl %r7,28
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clr %r6,%r7 # compare cc with last access code
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je .Lsame
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j .Lchkmem
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.Lsame:
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algr %r5,%r1 # add 128KB to end of chunk
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# no need to check here,
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brc 12,.Lloop # this is the same chunk
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.Lchkmem: # > 16EB or tprot got a program check
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clgr %r4,%r5 # chunk size > 0?
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je .Lchkloop
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stg %r4,0(%r3) # store start address of chunk
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lgr %r0,%r5
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slgr %r0,%r4
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stg %r0,8(%r3) # store size of chunk
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st %r6,20(%r3) # store type of chunk
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la %r3,24(%r3)
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larl %r8,memory_size
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stg %r5,0(%r8) # store memory size
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ahi %r10,-1 # update chunk number
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algr %r5,%r1 # add 128KB to end of chunk
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# no need to check here,
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brc 12,.Lloop # this is the same chunk
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.Lchkmem: # > 16EB or tprot got a program check
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clgr %r4,%r5 # chunk size > 0?
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je .Lchkloop
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stg %r4,0(%r3) # store start address of chunk
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lgr %r0,%r5
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slgr %r0,%r4
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stg %r0,8(%r3) # store size of chunk
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st %r6,20(%r3) # store type of chunk
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la %r3,24(%r3)
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larl %r8,memory_size
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stg %r5,0(%r8) # store memory size
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ahi %r10,-1 # update chunk number
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.Lchkloop:
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lr %r6,%r7 # set access code to last cc
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lr %r6,%r7 # set access code to last cc
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# we got an exception or we're starting a new
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# chunk , we must check if we should
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# still try to find valid memory (if we detected
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# the amount of available storage), and if we
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# have chunks left
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lghi %r4,1
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sllg %r4,%r4,31
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clgr %r5,%r4
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je .Lhsaskip
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xr %r0, %r0
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clgr %r0, %r9 # did we detect memory?
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je .Ldonemem # if not, leave
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chi %r10, 0 # do we have chunks left?
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je .Ldonemem
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lghi %r4,1
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sllg %r4,%r4,31
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clgr %r5,%r4
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je .Lhsaskip
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xr %r0, %r0
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clgr %r0, %r9 # did we detect memory?
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je .Ldonemem # if not, leave
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chi %r10, 0 # do we have chunks left?
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je .Ldonemem
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.Lhsaskip:
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algr %r5,%r1 # add 128KB to end of chunk
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lgr %r4,%r5 # potential new chunk
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clgr %r5,%r9 # should we go on?
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jl .Lloop
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.Ldonemem:
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algr %r5,%r1 # add 128KB to end of chunk
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lgr %r4,%r5 # potential new chunk
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clgr %r5,%r9 # should we go on?
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jl .Lloop
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.Ldonemem:
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larl %r12,machine_flags
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larl %r12,machine_flags
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#
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# find out if we are running under VM
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#
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stidp __LC_CPUID # store cpuid
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tm __LC_CPUID,0xff # running under VM ?
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bno 0f-.LPG1(%r13)
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oi 7(%r12),1 # set VM flag
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0: lh %r0,__LC_CPUID+4 # get cpu version
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chi %r0,0x7490 # running on a P/390 ?
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bne 1f-.LPG1(%r13)
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oi 7(%r12),4 # set P/390 flag
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stidp __LC_CPUID # store cpuid
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tm __LC_CPUID,0xff # running under VM ?
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bno 0f-.LPG1(%r13)
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oi 7(%r12),1 # set VM flag
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0: lh %r0,__LC_CPUID+4 # get cpu version
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chi %r0,0x7490 # running on a P/390 ?
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bne 1f-.LPG1(%r13)
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oi 7(%r12),4 # set P/390 flag
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1:
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#
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# find out if we have the MVPG instruction
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#
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la %r1,0f-.LPG1(%r13) # set program check address
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stg %r1,__LC_PGM_NEW_PSW+8
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sgr %r0,%r0
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lghi %r1,0
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lghi %r2,0
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mvpg %r1,%r2 # test MVPG instruction
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oi 7(%r12),16 # set MVPG flag
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la %r1,0f-.LPG1(%r13) # set program check address
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stg %r1,__LC_PGM_NEW_PSW+8
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sgr %r0,%r0
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lghi %r1,0
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lghi %r2,0
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mvpg %r1,%r2 # test MVPG instruction
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oi 7(%r12),16 # set MVPG flag
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0:
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#
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# find out if the diag 0x44 works in 64 bit mode
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#
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la %r1,0f-.LPG1(%r13) # set program check address
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stg %r1,__LC_PGM_NEW_PSW+8
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diag 0,0,0x44 # test diag 0x44
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oi 7(%r12),32 # set diag44 flag
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0:
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la %r1,0f-.LPG1(%r13) # set program check address
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stg %r1,__LC_PGM_NEW_PSW+8
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diag 0,0,0x44 # test diag 0x44
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oi 7(%r12),32 # set diag44 flag
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0:
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#
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# find out if we have the IDTE instruction
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#
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la %r1,0f-.LPG1(%r13) # set program check address
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stg %r1,__LC_PGM_NEW_PSW+8
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la %r1,0f-.LPG1(%r13) # set program check address
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stg %r1,__LC_PGM_NEW_PSW+8
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.long 0xb2b10000 # store facility list
|
||||
tm 0xc8,0x08 # check bit for clearing-by-ASCE
|
||||
bno 0f-.LPG1(%r13)
|
||||
@@ -263,45 +263,45 @@ startup_continue:
|
||||
oi 6(%r12),2 # set MVCOS flag
|
||||
1:
|
||||
|
||||
lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space,
|
||||
# virtual and never return ...
|
||||
.align 16
|
||||
.Lentry:.quad 0x0000000180000000,_stext
|
||||
.Lctl: .quad 0x04b50002 # cr0: various things
|
||||
.quad 0 # cr1: primary space segment table
|
||||
.quad .Lduct # cr2: dispatchable unit control table
|
||||
.quad 0 # cr3: instruction authorization
|
||||
.quad 0 # cr4: instruction authorization
|
||||
.quad 0xffffffffffffffff # cr5: primary-aste origin
|
||||
.quad 0 # cr6: I/O interrupts
|
||||
.quad 0 # cr7: secondary space segment table
|
||||
.quad 0 # cr8: access registers translation
|
||||
.quad 0 # cr9: tracing off
|
||||
.quad 0 # cr10: tracing off
|
||||
.quad 0 # cr11: tracing off
|
||||
.quad 0 # cr12: tracing off
|
||||
.quad 0 # cr13: home space segment table
|
||||
.quad 0xc0000000 # cr14: machine check handling off
|
||||
.quad 0 # cr15: linkage stack operations
|
||||
.Lduct: .long 0,0,0,0,0,0,0,0
|
||||
.long 0,0,0,0,0,0,0,0
|
||||
.Lpcmsk:.quad 0x0000000180000000
|
||||
lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space,
|
||||
# virtual and never return ...
|
||||
.align 16
|
||||
.Lentry:.quad 0x0000000180000000,_stext
|
||||
.Lctl: .quad 0x04b50002 # cr0: various things
|
||||
.quad 0 # cr1: primary space segment table
|
||||
.quad .Lduct # cr2: dispatchable unit control table
|
||||
.quad 0 # cr3: instruction authorization
|
||||
.quad 0 # cr4: instruction authorization
|
||||
.quad 0xffffffffffffffff # cr5: primary-aste origin
|
||||
.quad 0 # cr6: I/O interrupts
|
||||
.quad 0 # cr7: secondary space segment table
|
||||
.quad 0 # cr8: access registers translation
|
||||
.quad 0 # cr9: tracing off
|
||||
.quad 0 # cr10: tracing off
|
||||
.quad 0 # cr11: tracing off
|
||||
.quad 0 # cr12: tracing off
|
||||
.quad 0 # cr13: home space segment table
|
||||
.quad 0xc0000000 # cr14: machine check handling off
|
||||
.quad 0 # cr15: linkage stack operations
|
||||
.Lduct: .long 0,0,0,0,0,0,0,0
|
||||
.long 0,0,0,0,0,0,0,0
|
||||
.Lpcmsk:.quad 0x0000000180000000
|
||||
.L4malign:.quad 0xffffffffffc00000
|
||||
.Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8
|
||||
.Lnop: .long 0x07000700
|
||||
.Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8
|
||||
.Lnop: .long 0x07000700
|
||||
.Lparmaddr:
|
||||
.quad PARMAREA
|
||||
|
||||
.globl ipl_schib
|
||||
.globl ipl_schib
|
||||
ipl_schib:
|
||||
.rept 13
|
||||
.long 0
|
||||
.endr
|
||||
|
||||
.globl ipl_flags
|
||||
.globl ipl_flags
|
||||
ipl_flags:
|
||||
.long 0
|
||||
.globl ipl_devno
|
||||
.long 0
|
||||
.globl ipl_devno
|
||||
ipl_devno:
|
||||
.word 0
|
||||
|
||||
@@ -309,47 +309,47 @@ ipl_devno:
|
||||
.globl s390_readinfo_sccb
|
||||
s390_readinfo_sccb:
|
||||
.Lsccb:
|
||||
.hword 0x1000 # length, one page
|
||||
.byte 0x00,0x00,0x00
|
||||
.byte 0x80 # variable response bit set
|
||||
.hword 0x1000 # length, one page
|
||||
.byte 0x00,0x00,0x00
|
||||
.byte 0x80 # variable response bit set
|
||||
.Lsccbr:
|
||||
.hword 0x00 # response code
|
||||
.hword 0x00 # response code
|
||||
.Lscpincr1:
|
||||
.hword 0x00
|
||||
.hword 0x00
|
||||
.Lscpa1:
|
||||
.byte 0x00
|
||||
.fill 89,1,0
|
||||
.byte 0x00
|
||||
.fill 89,1,0
|
||||
.Lscpa2:
|
||||
.int 0x00
|
||||
.int 0x00
|
||||
.Lscpincr2:
|
||||
.quad 0x00
|
||||
.fill 3984,1,0
|
||||
.quad 0x00
|
||||
.fill 3984,1,0
|
||||
.org 0x13000
|
||||
|
||||
#ifdef CONFIG_SHARED_KERNEL
|
||||
.org 0x100000
|
||||
.org 0x100000
|
||||
#endif
|
||||
|
||||
|
||||
#
|
||||
# startup-code, running in absolute addressing mode
|
||||
#
|
||||
.globl _stext
|
||||
_stext: basr %r13,0 # get base
|
||||
.globl _stext
|
||||
_stext: basr %r13,0 # get base
|
||||
.LPG3:
|
||||
# check control registers
|
||||
stctg %c0,%c15,0(%r15)
|
||||
oi 6(%r15),0x40 # enable sigp emergency signal
|
||||
oi 4(%r15),0x10 # switch on low address proctection
|
||||
lctlg %c0,%c15,0(%r15)
|
||||
stctg %c0,%c15,0(%r15)
|
||||
oi 6(%r15),0x40 # enable sigp emergency signal
|
||||
oi 4(%r15),0x10 # switch on low address proctection
|
||||
lctlg %c0,%c15,0(%r15)
|
||||
|
||||
lam 0,15,.Laregs-.LPG3(%r13) # load access regs needed by uaccess
|
||||
brasl %r14,start_kernel # go to C code
|
||||
lam 0,15,.Laregs-.LPG3(%r13) # load acrs needed by uaccess
|
||||
brasl %r14,start_kernel # go to C code
|
||||
#
|
||||
# We returned from start_kernel ?!? PANIK
|
||||
#
|
||||
basr %r13,0
|
||||
lpswe .Ldw-.(%r13) # load disabled wait psw
|
||||
basr %r13,0
|
||||
lpswe .Ldw-.(%r13) # load disabled wait psw
|
||||
|
||||
.align 8
|
||||
.Ldw: .quad 0x0002000180000000,0x0000000000000000
|
||||
.Laregs: .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
|
||||
.align 8
|
||||
.Ldw: .quad 0x0002000180000000,0x0000000000000000
|
||||
.Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
|
||||
|
||||
Reference in New Issue
Block a user