diff --git a/arch/arm/mach-msm/qdsp5v2/adsp.c b/arch/arm/mach-msm/qdsp5v2/adsp.c
index acd9c4c1bcc..8c1413c0909 100644
--- a/arch/arm/mach-msm/qdsp5v2/adsp.c
+++ b/arch/arm/mach-msm/qdsp5v2/adsp.c
@@ -883,7 +883,7 @@ int msm_adsp_enable(struct msm_adsp_module *module)
 			rc = -ETIMEDOUT;
 		}
 		if (module->open_count++ == 0 && module->clk)
-			clk_enable(module->clk);
+			clk_prepare_enable(module->clk);
 
 		mutex_lock(&adsp_open_lock);
 		if (adsp_open_count++ == 0)
@@ -938,7 +938,7 @@ int msm_adsp_disable(struct msm_adsp_module *module)
 		mutex_lock(&module->lock);
 		module->state = ADSP_STATE_DISABLED;
 		if (--module->open_count == 0 && module->clk)
-			clk_disable(module->clk);
+			clk_disable_unprepare(module->clk);
 		mutex_unlock(&module->lock);
 		mutex_lock(&adsp_open_lock);
 		if (--adsp_open_count == 0) {
diff --git a/arch/arm/mach-msm/qdsp5v2/lpa.c b/arch/arm/mach-msm/qdsp5v2/lpa.c
index c4e0feeaa0a..98297e30776 100644
--- a/arch/arm/mach-msm/qdsp5v2/lpa.c
+++ b/arch/arm/mach-msm/qdsp5v2/lpa.c
@@ -73,7 +73,7 @@ static void lpa_reset(struct lpa_drv *lpa)
 		MM_ERR("failed to get adsp clk\n");
 		goto error;
 	}
-	clk_enable(adsp_clk);
+	clk_prepare_enable(adsp_clk);
 	lpa_enable_codec(lpa, 0);
 	LPA_REG_WRITEL(lpa, (LPA_OBUF_RESETS_MISR_RESET |
 		LPA_OBUF_RESETS_OVERALL_RESET), LPA_OBUF_RESETS);
@@ -83,7 +83,7 @@ static void lpa_reset(struct lpa_drv *lpa)
 
 	LPA_REG_WRITEL(lpa, LPA_OBUF_ACK_RESET_DONE_BMSK, LPA_OBUF_ACK);
 	mb();
-	clk_disable(adsp_clk);
+	clk_disable_unprepare(adsp_clk);
 	clk_put(adsp_clk);
 error:
 	return;
diff --git a/arch/arm/mach-msm/qdsp5v2/snddev_ecodec.c b/arch/arm/mach-msm/qdsp5v2/snddev_ecodec.c
index a5da912b29b..943489a1d9f 100644
--- a/arch/arm/mach-msm/qdsp5v2/snddev_ecodec.c
+++ b/arch/arm/mach-msm/qdsp5v2/snddev_ecodec.c
@@ -60,7 +60,7 @@ static int snddev_ecodec_open_rx(struct snddev_ecodec_state *ecodec)
 			goto done;
 		}
 		/* config clocks */
-		clk_enable(drv->lpa_core_clk);
+		clk_prepare_enable(drv->lpa_core_clk);
 
 		/*if long sync is selected in aux PCM interface
 		ecodec clock is updated to work with 128KHz,
@@ -96,7 +96,7 @@ static int snddev_ecodec_open_rx(struct snddev_ecodec_state *ecodec)
 		}
 
 		/* enable ecodec clk */
-		clk_enable(drv->ecodec_clk);
+		clk_prepare_enable(drv->ecodec_clk);
 
 		/* let ADSP confiure AUX PCM regs */
 		aux_codec_adsp_codec_ctl_en(ADSP_CTL);
@@ -109,7 +109,7 @@ static int snddev_ecodec_open_rx(struct snddev_ecodec_state *ecodec)
 		audio_interct_tpcm_source(AUDIO_ADSP_A);
 		audio_interct_rpcm_source(AUDIO_ADSP_A);
 
-		clk_disable(drv->lpa_core_clk);
+		clk_disable_unprepare(drv->lpa_core_clk);
 
 		/* send AUX_CODEC_CONFIG to AFE */
 		rc = afe_config_aux_codec(ecodec->data->conf_pcm_ctl_val,
@@ -126,7 +126,7 @@ static int snddev_ecodec_open_rx(struct snddev_ecodec_state *ecodec)
 	if (IS_ERR_VALUE(rc)) {
 		if (!drv->tx_active) {
 			aux_pcm_gpios_free();
-			clk_disable(drv->ecodec_clk);
+			clk_disable_unprepare(drv->ecodec_clk);
 		}
 		goto done;
 	}
@@ -136,7 +136,7 @@ static int snddev_ecodec_open_rx(struct snddev_ecodec_state *ecodec)
 
 error:
 	aux_pcm_gpios_free();
-	clk_disable(drv->ecodec_clk);
+	clk_disable_unprepare(drv->ecodec_clk);
 done:
 	return rc;
 }
@@ -148,7 +148,7 @@ static int snddev_ecodec_close_rx(struct snddev_ecodec_state *ecodec)
 	/* free GPIO */
 	if (!drv->tx_active) {
 		aux_pcm_gpios_free();
-		clk_disable(drv->ecodec_clk);
+		clk_disable_unprepare(drv->ecodec_clk);
 	}
 
 	/* disable AFE */
@@ -176,7 +176,7 @@ static int snddev_ecodec_open_tx(struct snddev_ecodec_state *ecodec)
 			goto done;
 		}
 		/* config clocks */
-		clk_enable(drv->lpa_core_clk);
+		clk_prepare_enable(drv->lpa_core_clk);
 
 		/*if long sync is selected in aux PCM interface
 		ecodec clock is updated to work with 128KHz,
@@ -212,7 +212,7 @@ static int snddev_ecodec_open_tx(struct snddev_ecodec_state *ecodec)
 		}
 
 		/* enable ecodec clk */
-		clk_enable(drv->ecodec_clk);
+		clk_prepare_enable(drv->ecodec_clk);
 
 		/* let ADSP confiure AUX PCM regs */
 		aux_codec_adsp_codec_ctl_en(ADSP_CTL);
@@ -225,7 +225,7 @@ static int snddev_ecodec_open_tx(struct snddev_ecodec_state *ecodec)
 		audio_interct_tpcm_source(AUDIO_ADSP_A);
 		audio_interct_rpcm_source(AUDIO_ADSP_A);
 
-		clk_disable(drv->lpa_core_clk);
+		clk_disable_unprepare(drv->lpa_core_clk);
 
 		/* send AUX_CODEC_CONFIG to AFE */
 		rc = afe_config_aux_codec(ecodec->data->conf_pcm_ctl_val,
@@ -242,7 +242,7 @@ static int snddev_ecodec_open_tx(struct snddev_ecodec_state *ecodec)
 	if (IS_ERR_VALUE(rc)) {
 		if (!drv->rx_active) {
 			aux_pcm_gpios_free();
-			clk_disable(drv->ecodec_clk);
+			clk_disable_unprepare(drv->ecodec_clk);
 		}
 		goto done;
 	}
@@ -251,7 +251,7 @@ static int snddev_ecodec_open_tx(struct snddev_ecodec_state *ecodec)
 	return 0;
 
 error:
-	clk_disable(drv->ecodec_clk);
+	clk_disable_unprepare(drv->ecodec_clk);
 	aux_pcm_gpios_free();
 done:
 	return rc;
@@ -264,7 +264,7 @@ static int snddev_ecodec_close_tx(struct snddev_ecodec_state *ecodec)
 	/* free GPIO */
 	if (!drv->rx_active) {
 		aux_pcm_gpios_free();
-		clk_disable(drv->ecodec_clk);
+		clk_disable_unprepare(drv->ecodec_clk);
 	}
 
 	/* disable AFE */
diff --git a/arch/arm/mach-msm/qdsp5v2/snddev_icodec.c b/arch/arm/mach-msm/qdsp5v2/snddev_icodec.c
index 80c9a01d1b4..c416c078c18 100644
--- a/arch/arm/mach-msm/qdsp5v2/snddev_icodec.c
+++ b/arch/arm/mach-msm/qdsp5v2/snddev_icodec.c
@@ -199,12 +199,12 @@ static int snddev_icodec_open_rx(struct snddev_icodec_state *icodec)
 		SNDDEV_ICODEC_CLK_RATE(icodec->sample_rate));
 	if (IS_ERR_VALUE(trc))
 		goto error_invalid_freq;
-	clk_enable(drv->rx_mclk);
-	clk_enable(drv->rx_sclk);
+	clk_prepare_enable(drv->rx_mclk);
+	clk_prepare_enable(drv->rx_sclk);
 	/* clk_set_rate(drv->lpa_codec_clk, 1); */ /* Remove if use pcom */
-	clk_enable(drv->lpa_p_clk);
-	clk_enable(drv->lpa_codec_clk);
-	clk_enable(drv->lpa_core_clk);
+	clk_prepare_enable(drv->lpa_p_clk);
+	clk_prepare_enable(drv->lpa_codec_clk);
+	clk_prepare_enable(drv->lpa_core_clk);
 
 	/* Enable LPA sub system
 	 */
@@ -263,11 +263,11 @@ error_afe:
 error_adie:
 	lpa_put(drv->lpa);
 error_lpa:
-	clk_disable(drv->lpa_p_clk);
-	clk_disable(drv->lpa_codec_clk);
-	clk_disable(drv->lpa_core_clk);
-	clk_disable(drv->rx_sclk);
-	clk_disable(drv->rx_mclk);
+	clk_disable_unprepare(drv->lpa_p_clk);
+	clk_disable_unprepare(drv->lpa_codec_clk);
+	clk_disable_unprepare(drv->lpa_core_clk);
+	clk_disable_unprepare(drv->rx_sclk);
+	clk_disable_unprepare(drv->rx_mclk);
 error_invalid_freq:
 
 	MM_ERR("encounter error\n");
@@ -307,8 +307,8 @@ static int snddev_icodec_open_tx(struct snddev_icodec_state *icodec)
 		SNDDEV_ICODEC_CLK_RATE(icodec->sample_rate));
 	if (IS_ERR_VALUE(trc))
 		goto error_invalid_freq;
-	clk_enable(drv->tx_mclk);
-	clk_enable(drv->tx_sclk);
+	clk_prepare_enable(drv->tx_mclk);
+	clk_prepare_enable(drv->tx_sclk);
 
 	/* Set MI2S */
 	mi2s_set_codec_input_path((icodec->data->channel_mode ==
@@ -344,8 +344,8 @@ error_afe:
 	adie_codec_close(icodec->adie_path);
 	icodec->adie_path = NULL;
 error_adie:
-	clk_disable(drv->tx_sclk);
-	clk_disable(drv->tx_mclk);
+	clk_disable_unprepare(drv->tx_sclk);
+	clk_disable_unprepare(drv->tx_mclk);
 error_invalid_freq:
 
 	/* Disable mic bias */
@@ -414,14 +414,14 @@ static int snddev_icodec_close_rx(struct snddev_icodec_state *icodec)
 	lpa_put(drv->lpa);
 
 	/* Disable LPA clocks */
-	clk_disable(drv->lpa_p_clk);
-	clk_disable(drv->lpa_codec_clk);
-	clk_disable(drv->lpa_core_clk);
+	clk_disable_unprepare(drv->lpa_p_clk);
+	clk_disable_unprepare(drv->lpa_codec_clk);
+	clk_disable_unprepare(drv->lpa_core_clk);
 
 	/* Disable MI2S RX master block */
 	/* Disable MI2S RX bit clock */
-	clk_disable(drv->rx_sclk);
-	clk_disable(drv->rx_mclk);
+	clk_disable_unprepare(drv->rx_sclk);
+	clk_disable_unprepare(drv->rx_mclk);
 
 	icodec->enabled = 0;
 
@@ -452,8 +452,8 @@ static int snddev_icodec_close_tx(struct snddev_icodec_state *icodec)
 
 	/* Disable MI2S TX master block */
 	/* Disable MI2S TX bit clock */
-	clk_disable(drv->tx_sclk);
-	clk_disable(drv->tx_mclk);
+	clk_disable_unprepare(drv->tx_sclk);
+	clk_disable_unprepare(drv->tx_mclk);
 
 	/* Disable mic bias */
 	for (i = 0; i < icodec->data->pmctl_id_sz; i++) {
@@ -889,8 +889,8 @@ static void debugfs_adie_loopback(u32 loop)
 		/* enable MI2S RX bit clock */
 		clk_set_rate(drv->rx_mclk,
 			SNDDEV_ICODEC_CLK_RATE(8000));
-		clk_enable(drv->rx_mclk);
-		clk_enable(drv->rx_sclk);
+		clk_prepare_enable(drv->rx_mclk);
+		clk_prepare_enable(drv->rx_sclk);
 
 		MM_INFO("configure ADIE RX path\n");
 		/* Configure ADIE */
@@ -905,8 +905,8 @@ static void debugfs_adie_loopback(u32 loop)
 		/* enable MI2S TX bit clock */
 		clk_set_rate(drv->tx_mclk,
 			SNDDEV_ICODEC_CLK_RATE(8000));
-		clk_enable(drv->tx_mclk);
-		clk_enable(drv->tx_sclk);
+		clk_prepare_enable(drv->tx_mclk);
+		clk_prepare_enable(drv->tx_sclk);
 
 		MM_INFO("configure ADIE TX path\n");
 		/* Configure ADIE */
@@ -927,13 +927,13 @@ static void debugfs_adie_loopback(u32 loop)
 
 		/* Disable MI2S RX master block */
 		/* Disable MI2S RX bit clock */
-		clk_disable(drv->rx_sclk);
-		clk_disable(drv->rx_mclk);
+		clk_disable_unprepare(drv->rx_sclk);
+		clk_disable_unprepare(drv->rx_mclk);
 
 		/* Disable MI2S TX master block */
 		/* Disable MI2S TX bit clock */
-		clk_disable(drv->tx_sclk);
-		clk_disable(drv->tx_mclk);
+		clk_disable_unprepare(drv->tx_sclk);
+		clk_disable_unprepare(drv->tx_mclk);
 	}
 }
 
@@ -955,11 +955,11 @@ static void debugfs_afe_loopback(u32 loop)
 		SNDDEV_ICODEC_CLK_RATE(8000));
 		if (IS_ERR_VALUE(trc))
 			MM_ERR("failed to set clk rate\n");
-		clk_enable(drv->rx_mclk);
-		clk_enable(drv->rx_sclk);
-		clk_enable(drv->lpa_p_clk);
-		clk_enable(drv->lpa_codec_clk);
-		clk_enable(drv->lpa_core_clk);
+		clk_prepare_enable(drv->rx_mclk);
+		clk_prepare_enable(drv->rx_sclk);
+		clk_prepare_enable(drv->lpa_p_clk);
+		clk_prepare_enable(drv->lpa_codec_clk);
+		clk_prepare_enable(drv->lpa_core_clk);
 		/* Enable LPA sub system
 		 */
 		drv->lpa = lpa_get();
@@ -1003,8 +1003,8 @@ static void debugfs_afe_loopback(u32 loop)
 		/* enable MI2S TX bit clock */
 		clk_set_rate(drv->tx_mclk,
 			SNDDEV_ICODEC_CLK_RATE(8000));
-		clk_enable(drv->tx_mclk);
-		clk_enable(drv->tx_sclk);
+		clk_prepare_enable(drv->tx_mclk);
+		clk_prepare_enable(drv->tx_sclk);
 		/* Set MI2S */
 		mi2s_set_codec_input_path(MI2S_CHAN_MONO_PACKED, WT_16_BIT);
 		MM_INFO("configure ADIE TX path\n");
@@ -1048,14 +1048,14 @@ static void debugfs_afe_loopback(u32 loop)
 		lpa_put(drv->lpa);
 
 		/* Disable LPA clocks */
-		clk_disable(drv->lpa_p_clk);
-		clk_disable(drv->lpa_codec_clk);
-		clk_disable(drv->lpa_core_clk);
+		clk_disable_unprepare(drv->lpa_p_clk);
+		clk_disable_unprepare(drv->lpa_codec_clk);
+		clk_disable_unprepare(drv->lpa_core_clk);
 
 		/* Disable MI2S RX master block */
 		/* Disable MI2S RX bit clock */
-		clk_disable(drv->rx_sclk);
-		clk_disable(drv->rx_mclk);
+		clk_disable_unprepare(drv->rx_sclk);
+		clk_disable_unprepare(drv->rx_mclk);
 
 		pmapp_smps_mode_vote(SMPS_AUDIO_RECORD_ID,
 			PMAPP_VREG_S4, PMAPP_SMPS_MODE_VOTE_DONTCARE);
@@ -1069,8 +1069,8 @@ static void debugfs_afe_loopback(u32 loop)
 		adie_codec_close(debugfs_tx_adie);
 		/* Disable MI2S TX master block */
 		/* Disable MI2S TX bit clock */
-		clk_disable(drv->tx_sclk);
-		clk_disable(drv->tx_mclk);
+		clk_disable_unprepare(drv->tx_sclk);
+		clk_disable_unprepare(drv->tx_mclk);
 		pmic_hsed_enable(PM_HSED_CONTROLLER_0, PM_HSED_ENABLE_OFF);
 		MM_INFO("AFE loopback disabled\n");
 	}
diff --git a/arch/arm/mach-msm/qdsp5v2/snddev_mi2s.c b/arch/arm/mach-msm/qdsp5v2/snddev_mi2s.c
index 939cc8b3848..b5f3b666ad3 100644
--- a/arch/arm/mach-msm/qdsp5v2/snddev_mi2s.c
+++ b/arch/arm/mach-msm/qdsp5v2/snddev_mi2s.c
@@ -154,12 +154,12 @@ static int snddev_mi2s_open(struct msm_snddev_info *dev_info)
 			mutex_unlock(&drv->lock);
 			return -EIO;
 		}
-		clk_enable(drv->mclk);
-		clk_enable(drv->sclk);
+		clk_prepare_enable(drv->mclk);
+		clk_prepare_enable(drv->sclk);
 		drv->clocks_enabled = 1;
-		MM_DBG("%s: clks enabled \n", __func__);
+		MM_DBG("%s: clks enabled\n", __func__);
 	} else
-		MM_DBG("%s: clks already enabled \n", __func__);
+		MM_DBG("%s: clks already enabled\n", __func__);
 
 	if (snddev_mi2s_data->capability & SNDDEV_CAP_RX) {
 
@@ -225,8 +225,8 @@ mi2s_cleanup_open:
 
 mi2s_data_gpio_failure:
 	if (!drv->sd_lines_used) {
-		clk_disable(drv->sclk);
-		clk_disable(drv->mclk);
+		clk_disable_unprepare(drv->sclk);
+		clk_disable_unprepare(drv->mclk);
 		drv->clocks_enabled = 0;
 		mi2s_unconfig_clk_gpio();
 	}
@@ -268,8 +268,8 @@ static int snddev_mi2s_close(struct msm_snddev_info *dev_info)
 	mi2s_unconfig_data_gpio(dir, snddev_mi2s_data->sd_lines);
 
 	if (!drv->sd_lines_used) {
-		clk_disable(drv->sclk);
-		clk_disable(drv->mclk);
+		clk_disable_unprepare(drv->sclk);
+		clk_disable_unprepare(drv->mclk);
 		drv->clocks_enabled = 0;
 		mi2s_unconfig_clk_gpio();
 	}