From 598786820ecfd8b2e35946a0eec2d64e7b5fba70 Mon Sep 17 00:00:00 2001 From: Matt Wagantall Date: Fri, 29 Jun 2012 12:07:27 -0700 Subject: [PATCH] msm: acpuclock-8974: Vote on the PM8941_S2 regulator for HFPLLs PM8941_S2 is the parent of PM8941_L12, which supplies the HFPLLs. Because the rpm_regulator_*() APIs do not manage this relationship, it is necessary to enable both from acpuclock when the HFPLLs are needed. Change-Id: I1f60934f1cdfc7acfdf3dec5a793754896c8d33f Signed-off-by: Matt Wagantall --- arch/arm/boot/dts/msm8974.dtsi | 15 ++++++++++----- arch/arm/mach-msm/acpuclock-8974.c | 15 ++++++++++----- 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi index d3f75c11290..6bcc3c26cda 100644 --- a/arch/arm/boot/dts/msm8974.dtsi +++ b/arch/arm/boot/dts/msm8974.dtsi @@ -282,11 +282,16 @@ krait1_dig-supply = <&pm8841_s2_corner_ao>; krait2_dig-supply = <&pm8841_s2_corner_ao>; krait3_dig-supply = <&pm8841_s2_corner_ao>; - krait0_hfpll-supply = <&pm8941_l12_ao>; - krait1_hfpll-supply = <&pm8941_l12_ao>; - krait2_hfpll-supply = <&pm8941_l12_ao>; - krait3_hfpll-supply = <&pm8941_l12_ao>; - l2_hfpll-supply = <&pm8941_l12_ao>; + krait0_hfpll_a-supply = <&pm8941_s2_ao>; + krait1_hfpll_a-supply = <&pm8941_s2_ao>; + krait2_hfpll_a-supply = <&pm8941_s2_ao>; + krait3_hfpll_a-supply = <&pm8941_s2_ao>; + l2_hfpll_a-supply = <&pm8941_s2_ao>; + krait0_hfpll_b-supply = <&pm8941_l12_ao>; + krait1_hfpll_b-supply = <&pm8941_l12_ao>; + krait2_hfpll_b-supply = <&pm8941_l12_ao>; + krait3_hfpll_b-supply = <&pm8941_l12_ao>; + l2_hfpll_b-supply = <&pm8941_l12_ao>; }; qcom,ssusb@F9200000 { diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c index c27b6c07882..c67109e222f 100644 --- a/arch/arm/mach-msm/acpuclock-8974.c +++ b/arch/arm/mach-msm/acpuclock-8974.c @@ -64,7 +64,8 @@ static struct scalable scalable[] = { .vreg[VREG_CORE] = { "krait0", 1050000, 3200000 }, .vreg[VREG_MEM] = { "krait0_mem", 1050000 }, .vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH }, - .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 }, + .vreg[VREG_HFPLL_A] = { "krait0_hfpll_a", 2150000 }, + .vreg[VREG_HFPLL_B] = { "krait0_hfpll_b", 1800000 }, }, [CPU1] = { .hfpll_phys_base = 0xF909A000, @@ -73,7 +74,8 @@ static struct scalable scalable[] = { .vreg[VREG_CORE] = { "krait1", 1050000, 3200000 }, .vreg[VREG_MEM] = { "krait1_mem", 1050000 }, .vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH }, - .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 }, + .vreg[VREG_HFPLL_A] = { "krait1_hfpll_a", 2150000 }, + .vreg[VREG_HFPLL_B] = { "krait1_hfpll_b", 1800000 }, }, [CPU2] = { .hfpll_phys_base = 0xF90AA000, @@ -82,7 +84,8 @@ static struct scalable scalable[] = { .vreg[VREG_CORE] = { "krait2", 1050000, 3200000 }, .vreg[VREG_MEM] = { "krait2_mem", 1050000 }, .vreg[VREG_DIG] = { "krait2_dig", LVL_HIGH }, - .vreg[VREG_HFPLL_A] = { "krait2_hfpll", 1800000 }, + .vreg[VREG_HFPLL_A] = { "krait2_hfpll_a", 2150000 }, + .vreg[VREG_HFPLL_B] = { "krait2_hfpll_b", 1800000 }, }, [CPU3] = { .hfpll_phys_base = 0xF90BA000, @@ -91,13 +94,15 @@ static struct scalable scalable[] = { .vreg[VREG_CORE] = { "krait3", 1050000, 3200000 }, .vreg[VREG_MEM] = { "krait3_mem", 1050000 }, .vreg[VREG_DIG] = { "krait3_dig", LVL_HIGH }, - .vreg[VREG_HFPLL_A] = { "krait3_hfpll", 1800000 }, + .vreg[VREG_HFPLL_A] = { "krait3_hfpll_a", 2150000 }, + .vreg[VREG_HFPLL_B] = { "krait3_hfpll_b", 1800000 }, }, [L2] = { .hfpll_phys_base = 0xF9016000, .hfpll_data = &hfpll_data_l2, .l2cpmr_iaddr = 0x0500, - .vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 }, + .vreg[VREG_HFPLL_A] = { "l2_hfpll_a", 2150000 }, + .vreg[VREG_HFPLL_B] = { "l2_hfpll_b", 1800000 }, }, };