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x86: UV: Address interrupt/IO port operation conflict

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This patch for SGI UV systems addresses a problem whereby
interrupt transactions being looped back from a local IOH,
through the hub to a local CPU can (erroneously) conflict with
IO port operations and other transactions.

To workaound this we set a high bit in the APIC IDs used for
interrupts. This bit appears to be ignored by the sockets, but
it avoids the conflict in the hub.

Signed-off-by: Dimitri Sivanich <sivanich@sgi.com>
LKML-Reference: <20101116222352.GA8155@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
___

 arch/x86/include/asm/uv/uv_hub.h   |    4 ++++
 arch/x86/include/asm/uv/uv_mmrs.h  |   19 ++++++++++++++++++-
 arch/x86/kernel/apic/x2apic_uv_x.c |   25 +++++++++++++++++++++++--
 arch/x86/platform/uv/tlb_uv.c      |    2 +-
 arch/x86/platform/uv/uv_time.c     |    4 +++-
 5 files changed, 49 insertions(+), 5 deletions(-)
This commit is contained in:
Dimitri Sivanich
2010-11-16 16:23:52 -06:00
committed by Ingo Molnar
parent 9223081f54
commit 8191c9f692
5 changed files with 49 additions and 5 deletions
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4
arch/x86/include/asm/uv/uv_hub.h
View File

@@ -199,6 +199,8 @@ union uvh_apicid {
#define UVH_APICID 0x002D0E00L
#define UV_APIC_PNODE_SHIFT 6
#define UV_APICID_HIBIT_MASK 0xffff0000
/* Local Bus from cpu's perspective */
#define LOCAL_BUS_BASE 0x1c00000
#define LOCAL_BUS_SIZE (4 * 1024 * 1024)
@@ -491,8 +493,10 @@ static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
}
}
extern unsigned int uv_apicid_hibits;
static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode)
{
apicid |= uv_apicid_hibits;
return (1UL << UVH_IPI_INT_SEND_SHFT) |
((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
(mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |

19
arch/x86/include/asm/uv/uv_mmrs.h
View File

@@ -5,7 +5,7 @@
*
* SGI UV MMR definitions
*
* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
* Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_X86_UV_UV_MMRS_H
@@ -753,6 +753,23 @@ union uvh_lb_bau_sb_descriptor_base_u {
} s;
};
/* ========================================================================= */
/* UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK */
/* ========================================================================= */
#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL
#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x009f0
#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL
union uvh_lb_target_physical_apic_id_mask_u {
unsigned long v;
struct uvh_lb_target_physical_apic_id_mask_s {
unsigned long bit_enables : 32; /* RW */
unsigned long rsvd_32_63 : 32; /* */
} s;
};
/* ========================================================================= */
/* UVH_NODE_ID */
/* ========================================================================= */