From 8aa3df2fcbc992edfd28ff4ffc24feb9dce53414 Mon Sep 17 00:00:00 2001 From: Pratik Patel Date: Sat, 21 Jul 2012 15:54:54 -0700 Subject: [PATCH] coresight: fix whitespace in coresight drivers Add/remove whitespace to improve code readability. Change-Id: Iade3100b7eb9a57f95849d6665257cffe85b26b3 Signed-off-by: Pratik Patel --- drivers/coresight/coresight-etb.c | 7 ++----- drivers/coresight/coresight-etm.c | 9 ++++----- drivers/coresight/coresight-funnel.c | 7 ++----- drivers/coresight/coresight-priv.h | 2 -- drivers/coresight/coresight-replicator.c | 6 ++---- drivers/coresight/coresight-stm.c | 7 +++---- drivers/coresight/coresight-tmc.c | 10 +++++----- drivers/coresight/coresight-tpiu.c | 10 +++++----- drivers/coresight/coresight.c | 3 --- drivers/coresight/of_coresight.c | 1 - include/linux/coresight.h | 2 -- 11 files changed, 23 insertions(+), 41 deletions(-) diff --git a/drivers/coresight/coresight-etb.c b/drivers/coresight/coresight-etb.c index 9deec2e4bfd..56cee06a24d 100644 --- a/drivers/coresight/coresight-etb.c +++ b/drivers/coresight/coresight-etb.c @@ -30,7 +30,6 @@ #include "coresight-priv.h" - #define etb_writel(drvdata, val, off) __raw_writel((val), drvdata->base + off) #define etb_readl(drvdata, off) __raw_readl(drvdata->base + off) @@ -45,7 +44,6 @@ do { \ mb(); \ } while (0) - #define ETB_RAM_DEPTH_REG (0x004) #define ETB_STATUS_REG (0x00C) #define ETB_RAM_READ_DATA_REG (0x010) @@ -64,12 +62,10 @@ do { \ #define ETB_ITATBCTR1 (0xEF4) #define ETB_ITATBCTR0 (0xEF8) - #define BYTES_PER_WORD 4 #define ETB_SIZE_WORDS 4096 #define FRAME_SIZE_WORDS 4 - struct etb_drvdata { void __iomem *base; struct device *dev; @@ -84,7 +80,6 @@ struct etb_drvdata { uint32_t trigger_cntr; }; - static void __etb_enable(struct etb_drvdata *drvdata) { int i; @@ -381,6 +376,7 @@ static int __devinit etb_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENODEV; + drvdata->base = devm_ioremap(dev, res->start, resource_size(res)); if (!drvdata->base) return -ENOMEM; @@ -390,6 +386,7 @@ static int __devinit etb_probe(struct platform_device *pdev) drvdata->clk = devm_clk_get(dev, "core_clk"); if (IS_ERR(drvdata->clk)) return PTR_ERR(drvdata->clk); + ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE); if (ret) return ret; diff --git a/drivers/coresight/coresight-etm.c b/drivers/coresight/coresight-etm.c index ed4a783c6cc..e805c7fcab6 100644 --- a/drivers/coresight/coresight-etm.c +++ b/drivers/coresight/coresight-etm.c @@ -35,7 +35,6 @@ #include "coresight-priv.h" - #define etm_writel(drvdata, val, off) \ __raw_writel((val), drvdata->base + off) #define etm_readl(drvdata, off) \ @@ -52,7 +51,6 @@ do { \ mb(); \ } while (0) - /* * Device registers: * 0x000 - 0x2FC: Trace registers @@ -117,7 +115,6 @@ do { \ #define ETMPDCR (0x310) #define ETMPDSR (0x314) - #define ETM_MAX_ADDR_CMP (16) #define ETM_MAX_CNTR (4) #define ETM_MAX_CTXID_CMP (3) @@ -143,7 +140,6 @@ enum etm_addr_type { ETM_ADDR_TYPE_STOP, }; - #ifdef CONFIG_MSM_QDSS_ETM_DEFAULT_ENABLE static int boot_enable = 1; #else @@ -199,7 +195,6 @@ struct etm_drvdata { uint32_t timestamp_event; }; - /* ETM clock is derived from the processor clock and gets enabled on a * logical OR of below items on Krait (pass2 onwards): * 1.CPMR[ETMCLKEN] is 1 @@ -1537,6 +1532,7 @@ static int __devinit etm_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENODEV; + drvdata->base = devm_ioremap(dev, res->start, resource_size(res)); if (!drvdata->base) return -ENOMEM; @@ -1551,6 +1547,7 @@ static int __devinit etm_probe(struct platform_device *pdev) ret = PTR_ERR(drvdata->clk); goto err0; } + ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE); if (ret) goto err0; @@ -1560,10 +1557,12 @@ static int __devinit etm_probe(struct platform_device *pdev) ret = clk_prepare_enable(drvdata->clk); if (ret) goto err0; + ret = etm_init_arch_data(drvdata); if (ret) goto err1; etm_init_default_data(drvdata); + clk_disable_unprepare(drvdata->clk); desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); diff --git a/drivers/coresight/coresight-funnel.c b/drivers/coresight/coresight-funnel.c index bf1df0bc8f0..3d5c0c2e925 100644 --- a/drivers/coresight/coresight-funnel.c +++ b/drivers/coresight/coresight-funnel.c @@ -25,7 +25,6 @@ #include "coresight-priv.h" - #define funnel_writel(drvdata, val, off) \ __raw_writel((val), drvdata->base + off) #define funnel_readl(drvdata, off) \ @@ -42,7 +41,6 @@ do { \ mb(); \ } while (0) - #define FUNNEL_FUNCTL (0x000) #define FUNNEL_PRICTL (0x004) #define FUNNEL_ITATBDATA0 (0xEEC) @@ -50,12 +48,10 @@ do { \ #define FUNNEL_ITATBCTR1 (0xEF4) #define FUNNEL_ITATBCTR0 (0xEF8) - #define FUNNEL_HOLDTIME_MASK (0xF00) #define FUNNEL_HOLDTIME_SHFT (0x8) #define FUNNEL_HOLDTIME (0x7 << FUNNEL_HOLDTIME_SHFT) - struct funnel_drvdata { void __iomem *base; struct device *dev; @@ -64,7 +60,6 @@ struct funnel_drvdata { uint32_t priority; }; - static void __funnel_enable(struct funnel_drvdata *drvdata, int port) { uint32_t functl; @@ -195,6 +190,7 @@ static int __devinit funnel_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENODEV; + drvdata->base = devm_ioremap(dev, res->start, resource_size(res)); if (!drvdata->base) return -ENOMEM; @@ -202,6 +198,7 @@ static int __devinit funnel_probe(struct platform_device *pdev) drvdata->clk = devm_clk_get(dev, "core_clk"); if (IS_ERR(drvdata->clk)) return PTR_ERR(drvdata->clk); + ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE); if (ret) return ret; diff --git a/drivers/coresight/coresight-priv.h b/drivers/coresight/coresight-priv.h index a6486daf07e..a28a3a5c104 100644 --- a/drivers/coresight/coresight-priv.h +++ b/drivers/coresight/coresight-priv.h @@ -15,7 +15,6 @@ #include - /* Coresight management registers (0xF00-0xFCC) * 0xFA0 - 0xFA4: Management registers in PFTv1.0 * Trace registers in PFTv1.1 @@ -29,7 +28,6 @@ #define CORESIGHT_DEVID (0xFC8) #define CORESIGHT_DEVTYPE (0xFCC) - #define CORESIGHT_UNLOCK (0xC5ACCE55) #define TIMEOUT_US (100) diff --git a/drivers/coresight/coresight-replicator.c b/drivers/coresight/coresight-replicator.c index ccf49e95f37..fec76c5664a 100644 --- a/drivers/coresight/coresight-replicator.c +++ b/drivers/coresight/coresight-replicator.c @@ -24,7 +24,6 @@ #include "coresight-priv.h" - #define replicator_writel(drvdata, val, off) \ __raw_writel((val), drvdata->base + off) #define replicator_readl(drvdata, off) \ @@ -41,13 +40,11 @@ do { \ mb(); \ } while (0) - #define REPLICATOR_IDFILTER0 (0x000) #define REPLICATOR_IDFILTER1 (0x004) #define REPLICATOR_ITATBCTR0 (0xEFC) #define REPLICATOR_ITATBCTR1 (0xEF8) - struct replicator_drvdata { void __iomem *base; struct device *dev; @@ -55,7 +52,6 @@ struct replicator_drvdata { struct clk *clk; }; - static void __replicator_enable(struct replicator_drvdata *drvdata, int outport) { REPLICATOR_UNLOCK(drvdata); @@ -146,6 +142,7 @@ static int __devinit replicator_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENODEV; + drvdata->base = devm_ioremap(dev, res->start, resource_size(res)); if (!drvdata->base) return -ENOMEM; @@ -153,6 +150,7 @@ static int __devinit replicator_probe(struct platform_device *pdev) drvdata->clk = devm_clk_get(dev, "core_clk"); if (IS_ERR(drvdata->clk)) return PTR_ERR(drvdata->clk); + ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE); if (ret) return ret; diff --git a/drivers/coresight/coresight-stm.c b/drivers/coresight/coresight-stm.c index 050a01d0482..e366918597d 100644 --- a/drivers/coresight/coresight-stm.c +++ b/drivers/coresight/coresight-stm.c @@ -31,7 +31,6 @@ #include "coresight-priv.h" - #define stm_writel(drvdata, val, off) __raw_writel((val), drvdata->base + off) #define stm_readl(drvdata, off) __raw_readl(drvdata->base + off) @@ -78,7 +77,6 @@ do { \ #define STMITATBID (0xEF4) #define STMITATBCTR0 (0xEF8) - #define NR_STM_CHANNEL (32) #define BYTES_PER_CHANNEL (256) #define STM_TRACE_BUF_SIZE (1024) @@ -100,7 +98,6 @@ enum { (ch * BYTES_PER_CHANNEL)) #define stm_channel_off(type, opts) (type & ~opts) - #ifdef CONFIG_MSM_QDSS_STM_DEFAULT_ENABLE static int boot_enable = 1; #else @@ -136,7 +133,6 @@ struct stm_drvdata { static struct stm_drvdata *stmdrvdata; - static int stm_hwevent_isenable(struct stm_drvdata *drvdata) { int ret = 0; @@ -664,6 +660,7 @@ static int __devinit stm_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENODEV; + drvdata->base = devm_ioremap(dev, res->start, resource_size(res)); if (!drvdata->base) return -ENOMEM; @@ -671,6 +668,7 @@ static int __devinit stm_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (!res) return -ENODEV; + if (boot_nr_channel) { res_size = min((resource_size_t)(boot_nr_channel * BYTES_PER_CHANNEL), resource_size(res)); @@ -692,6 +690,7 @@ static int __devinit stm_probe(struct platform_device *pdev) drvdata->clk = devm_clk_get(dev, "core_clk"); if (IS_ERR(drvdata->clk)) return PTR_ERR(drvdata->clk); + ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE); if (ret) return ret; diff --git a/drivers/coresight/coresight-tmc.c b/drivers/coresight/coresight-tmc.c index 02b8378c4e1..1c85aff5271 100644 --- a/drivers/coresight/coresight-tmc.c +++ b/drivers/coresight/coresight-tmc.c @@ -32,7 +32,6 @@ #include "coresight-priv.h" - #define tmc_writel(drvdata, val, off) __raw_writel((val), drvdata->base + off) #define tmc_readl(drvdata, off) __raw_readl(drvdata->base + off) @@ -47,7 +46,6 @@ do { \ mb(); \ } while (0) - #define TMC_RSZ (0x004) #define TMC_STS (0x00C) #define TMC_RRD (0x010) @@ -75,7 +73,6 @@ do { \ #define TMC_ITATBCTR1 (0xEF4) #define TMC_ITATBCTR0 (0xEF8) - #define BYTES_PER_WORD 4 enum tmc_config_type { @@ -97,7 +94,6 @@ enum tmc_mem_intf_width { TMC_MEM_INTF_WIDTH_256BITS = 0x5, }; - struct tmc_drvdata { void __iomem *base; struct device *dev; @@ -116,7 +112,6 @@ struct tmc_drvdata { uint32_t trigger_cntr; }; - static void tmc_wait_for_ready(struct tmc_drvdata *drvdata) { int count; @@ -643,6 +638,7 @@ static int __devinit tmc_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENODEV; + drvdata->base = devm_ioremap(dev, res->start, resource_size(res)); if (!drvdata->base) return -ENOMEM; @@ -652,6 +648,7 @@ static int __devinit tmc_probe(struct platform_device *pdev) drvdata->clk = devm_clk_get(dev, "core_clk"); if (IS_ERR(drvdata->clk)) return PTR_ERR(drvdata->clk); + ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE); if (ret) return ret; @@ -659,12 +656,15 @@ static int __devinit tmc_probe(struct platform_device *pdev) ret = clk_prepare_enable(drvdata->clk); if (ret) return ret; + devid = tmc_readl(drvdata, CORESIGHT_DEVID); drvdata->config_type = BMVAL(devid, 6, 7); + if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) drvdata->size = SZ_1M; else drvdata->size = tmc_readl(drvdata, TMC_RSZ) * BYTES_PER_WORD; + clk_disable_unprepare(drvdata->clk); if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { diff --git a/drivers/coresight/coresight-tpiu.c b/drivers/coresight/coresight-tpiu.c index 6984e3289ad..290ae7f8a22 100644 --- a/drivers/coresight/coresight-tpiu.c +++ b/drivers/coresight/coresight-tpiu.c @@ -24,7 +24,6 @@ #include "coresight-priv.h" - #define tpiu_writel(drvdata, val, off) __raw_writel((val), drvdata->base + off) #define tpiu_readl(drvdata, off) __raw_readl(drvdata->base + off) @@ -39,7 +38,6 @@ do { \ mb(); \ } while (0) - #define TPIU_SUPP_PORTSZ (0x000) #define TPIU_CURR_PORTSZ (0x004) #define TPIU_SUPP_TRIGMODES (0x100) @@ -60,7 +58,6 @@ do { \ #define TPIU_ITATBCTR1 (0xEF4) #define TPIU_ITATBCTR0 (0xEF8) - struct tpiu_drvdata { void __iomem *base; struct device *dev; @@ -68,7 +65,6 @@ struct tpiu_drvdata { struct clk *clk; }; - static void __tpiu_enable(struct tpiu_drvdata *drvdata) { TPIU_UNLOCK(drvdata); @@ -158,6 +154,7 @@ static int __devinit tpiu_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENODEV; + drvdata->base = devm_ioremap(dev, res->start, resource_size(res)); if (!drvdata->base) return -ENOMEM; @@ -165,15 +162,18 @@ static int __devinit tpiu_probe(struct platform_device *pdev) drvdata->clk = devm_clk_get(dev, "core_clk"); if (IS_ERR(drvdata->clk)) return PTR_ERR(drvdata->clk); + ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE); if (ret) return ret; - /* Disable tpiu to support older targets that need this */ ret = clk_prepare_enable(drvdata->clk); if (ret) return ret; + + /* Disable tpiu to support older targets that need this */ __tpiu_disable(drvdata); + clk_disable_unprepare(drvdata->clk); desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); diff --git a/drivers/coresight/coresight.c b/drivers/coresight/coresight.c index 455ed1d15e4..f76d3033c26 100644 --- a/drivers/coresight/coresight.c +++ b/drivers/coresight/coresight.c @@ -26,16 +26,13 @@ #include "coresight-priv.h" - #define NO_SINK (-1) - static int curr_sink = NO_SINK; static LIST_HEAD(coresight_orph_conns); static LIST_HEAD(coresight_devs); static DEFINE_SEMAPHORE(coresight_mutex); - static int coresight_find_link_inport(struct coresight_device *csdev) { int i; diff --git a/drivers/coresight/of_coresight.c b/drivers/coresight/of_coresight.c index cdc76f1fe14..5c2c5259b53 100644 --- a/drivers/coresight/of_coresight.c +++ b/drivers/coresight/of_coresight.c @@ -17,7 +17,6 @@ #include #include - struct coresight_platform_data *of_get_coresight_platform_data( struct device *dev, struct device_node *node) { diff --git a/include/linux/coresight.h b/include/linux/coresight.h index a829f069e7d..04fcd883c3a 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -15,7 +15,6 @@ #include - /* Peripheral id registers (0xFD0-0xFEC) */ #define CORESIGHT_PERIPHIDR4 (0xFD0) #define CORESIGHT_PERIPHIDR5 (0xFD4) @@ -31,7 +30,6 @@ #define CORESIGHT_COMPIDR2 (0xFF8) #define CORESIGHT_COMPIDR3 (0xFFC) - /* DBGv7 with baseline CP14 registers implemented */ #define ARM_DEBUG_ARCH_V7B (0x3) /* DBGv7 with all CP14 registers implemented */