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Merge master.kernel.org:/home/rmk/linux-2.6-arm

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* master.kernel.org:/home/rmk/linux-2.6-arm: (38 commits)
  [ARM] 5191/1: ARM: remove CVS keywords
  [ARM] pxafb: fix the warning of incorrect lccr when lcd_conn is specified
  [ARM] pxafb: add flag to specify output format on LDD pins when base is RGBT16
  [ARM] pxafb: fix the incorrect configuration of GPIO77 as ACBIAS for TFT LCD
  [ARM] 5198/1: PalmTX: PCMCIA fixes
  [ARM] Fix a pile of broken watchdog drivers
  [ARM] update mach-types
  [ARM] 5196/1: fix inline asm constraints for preload
  [ARM] 5194/1: update .gitignore
  [ARM] add proc-macros.S include to proc-arm940 and proc-arm946
  [ARM] 5192/1: ARM TLB: add v7wbi_{possible,always}_flags to {possible,always}_tlb_flags
  [ARM] 5193/1: Wire up missing syscalls
  [ARM] traps: don't call undef hook functions with spinlock held
  [ARM] 5183/2: Provide Poodle LoCoMo GPIO names
  [ARM] dma-mapping: provide sync_range APIs
  [ARM] dma-mapping: improve type-safeness of DMA translations
  [ARM] Kirkwood: instantiate the orion_spi driver in the platform code
  [ARM] prevent crashing when too much RAM installed
  [ARM] Kirkwood: Instantiate mv_xor driver
  [ARM] Orion: Instantiate mv_xor driver for 5182
  ...
This commit is contained in:
Linus Torvalds
2008-08-16 16:48:45 -07:00
parent 5e6b83ed8c 66bfa2f031
commit 9c0d2a20fe
88 changed files with 940 additions and 214 deletions
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11
include/asm-arm/plat-orion/cache-feroceon-l2.h
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@@ -1,11 +0,0 @@
/*
* include/asm-arm/plat-orion/cache-feroceon-l2.h
*
* Copyright (C) 2008 Marvell Semiconductor
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
extern void __init feroceon_l2_init(int l2_wt_override);

19
include/asm-arm/plat-orion/ehci-orion.h
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@@ -1,19 +0,0 @@
/*
* include/asm-arm/plat-orion/ehci-orion.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_PLAT_ORION_EHCI_ORION_H
#define __ASM_PLAT_ORION_EHCI_ORION_H
#include <linux/mbus.h>
struct orion_ehci_data {
struct mbus_dram_target_info *dram;
};
#endif

17
include/asm-arm/plat-orion/irq.h
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@@ -1,17 +0,0 @@
/*
* include/asm-arm/plat-orion/irq.h
*
* Marvell Orion SoC IRQ handling.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_PLAT_ORION_IRQ_H
#define __ASM_PLAT_ORION_IRQ_H
void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr);
#endif

28
include/asm-arm/plat-orion/mv_xor.h
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@@ -1,28 +0,0 @@
/*
* Marvell XOR platform device data definition file.
*/
#ifndef __ASM_PLAT_ORION_MV_XOR_H
#define __ASM_PLAT_ORION_MV_XOR_H
#include <linux/dmaengine.h>
#include <linux/mbus.h>
#define MV_XOR_SHARED_NAME "mv_xor_shared"
#define MV_XOR_NAME "mv_xor"
struct mbus_dram_target_info;
struct mv_xor_platform_shared_data {
struct mbus_dram_target_info *dram;
};
struct mv_xor_platform_data {
struct platform_device *shared;
int hw_id;
dma_cap_mask_t cap_mask;
size_t pool_size;
};
#endif

25
include/asm-arm/plat-orion/orion_nand.h
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@@ -1,25 +0,0 @@
/*
* include/asm-arm/plat-orion/orion_nand.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_PLAT_ORION_ORION_NAND_H
#define __ASM_PLAT_ORION_ORION_NAND_H
/*
* Device bus NAND private data
*/
struct orion_nand_data {
struct mtd_partition *parts;
u32 nr_parts;
u8 ale; /* address line number connected to ALE */
u8 cle; /* address line number connected to CLE */
u8 width; /* buswidth */
u8 chip_delay;
};
#endif

32
include/asm-arm/plat-orion/pcie.h
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@@ -1,32 +0,0 @@
/*
* include/asm-arm/plat-orion/pcie.h
*
* Marvell Orion SoC PCIe handling.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_PLAT_ORION_PCIE_H
#define __ASM_PLAT_ORION_PCIE_H
u32 orion_pcie_dev_id(void __iomem *base);
u32 orion_pcie_rev(void __iomem *base);
int orion_pcie_link_up(void __iomem *base);
int orion_pcie_x4_mode(void __iomem *base);
int orion_pcie_get_local_bus_nr(void __iomem *base);
void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
void orion_pcie_setup(void __iomem *base,
struct mbus_dram_target_info *dram);
int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
u32 devfn, int where, int size, u32 *val);
int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
u32 devfn, int where, int size, u32 *val);
int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
u32 devfn, int where, int size, u32 *val);
int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
u32 devfn, int where, int size, u32 val);
#endif

17
include/asm-arm/plat-orion/time.h
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@@ -1,17 +0,0 @@
/*
* include/asm-arm/plat-orion/time.h
*
* Marvell Orion SoC time handling.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_PLAT_ORION_TIME_H
#define __ASM_PLAT_ORION_TIME_H
void orion_time_init(unsigned int irq, unsigned int tclk);
#endif

2
include/asm-arm/plat-s3c/regs-nand.h
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@@ -11,7 +11,7 @@
*/
#ifndef __ASM_ARM_REGS_NAND
#define __ASM_ARM_REGS_NAND "$Id: nand.h,v 1.3 2003/12/09 11:36:29 ben Exp $"
#define __ASM_ARM_REGS_NAND
#define S3C2410_NFREG(x) (x)

2
include/asm-arm/plat-s3c/regs-timer.h
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@@ -12,7 +12,7 @@
#ifndef __ASM_ARCH_REGS_TIMER_H
#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
#define __ASM_ARCH_REGS_TIMER_H
#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))

2
include/asm-arm/plat-s3c/regs-watchdog.h
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@@ -12,7 +12,7 @@
#ifndef __ASM_ARCH_REGS_WATCHDOG_H
#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
#define __ASM_ARCH_REGS_WATCHDOG_H
#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)

4
include/asm-arm/plat-s3c24xx/s3c2410.h
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@@ -21,11 +21,11 @@ extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void s3c2410_init_clocks(int xtal);
extern int s3c2410_baseclk_add(void);
#else
#define s3c2410_init_clocks NULL
#define s3c2410_init_uarts NULL
#define s3c2410_map_io NULL
#define s3c2410_init NULL
#endif
extern int s3c2410_baseclk_add(void);