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[PATCH] ppc32: Support for 82xx PQII on-chip PCI bridge

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This patch adds on-chip PCI bridge support for the PQ2 family.  The
incomplete existent code is updated with interrupt handling stuff and
board-specific bits for 8272ADS and PQ2FADS; the related files were renamed
(from m8260_pci to m82xx_pci) to be of more generic fashion.  This is
tested with 8266ADS and 8272ADS, should work on PQ2FADS as well.

Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Vitaly Bordug
2005-05-28 15:52:09 -07:00
committed by Linus Torvalds
parent ed36959621
commit a6dbba77a9
12 changed files with 558 additions and 303 deletions
Download Patch File Download Diff File Expand all files Collapse all files

46
include/asm-ppc/cpm2.h
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@@ -1039,6 +1039,52 @@ typedef struct im_idma {
#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration Register 4-31
*/
#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
#define SIUMCR_CDIS 0x10000000 /* Core Disable */
#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
#define SIUMCR_DPPC01 0x04000000 /* - " - */
#define SIUMCR_DPPC10 0x08000000 /* - " - */
#define SIUMCR_DPPC11 0x0c000000 /* - " - */
#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
#define SIUMCR_L2CPC01 0x01000000 /* - " - */
#define SIUMCR_L2CPC10 0x02000000 /* - " - */
#define SIUMCR_L2CPC11 0x03000000 /* - " - */
#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
#define SIUMCR_LBPC01 0x00400000 /* - " - */
#define SIUMCR_LBPC10 0x00800000 /* - " - */
#define SIUMCR_LBPC11 0x00c00000 /* - " - */
#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
#define SIUMCR_APPC01 0x00100000 /* - " - */
#define SIUMCR_APPC10 0x00200000 /* - " - */
#define SIUMCR_APPC11 0x00300000 /* - " - */
#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
#define SIUMCR_CS10PC01 0x00040000 /* - " - */
#define SIUMCR_CS10PC10 0x00080000 /* - " - */
#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
#define SIUMCR_BCTLC01 0x00010000 /* - " - */
#define SIUMCR_BCTLC10 0x00020000 /* - " - */
#define SIUMCR_BCTLC11 0x00030000 /* - " - */
#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
#define SIUMCR_MMR01 0x00004000 /* - " - */
#define SIUMCR_MMR10 0x00008000 /* - " - */
#define SIUMCR_MMR11 0x0000c000 /* - " - */
#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
/*-----------------------------------------------------------------------
* SCCR - System Clock Control Register 9-8
*/
#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
#define SCCR_PCIDF_SHIFT 3
#endif /* __CPM2__ */
#endif /* __KERNEL__ */