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Merge HEAD from master.kernel.org:/home/rmk/linux-2.6-arm.git

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This commit is contained in:
Linus Torvalds
2005-09-01 10:56:57 -07:00
parent 80ac2912f8 147056fb84
commit b25dd2842b
19 changed files with 273 additions and 225 deletions
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102
include/asm-arm/arch-ixp4xx/io.h
View File

@@ -383,39 +383,45 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
*vaddr++ = inl(io_addr);
}
#define __is_io_address(p) (((unsigned long)p >= 0x0) && \
((unsigned long)p <= 0x0000ffff))
#define PIO_OFFSET 0x10000UL
#define PIO_MASK 0x0ffffUL
#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
static inline unsigned int
__ixp4xx_ioread8(void __iomem *port)
__ixp4xx_ioread8(void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
return (unsigned int)__ixp4xx_inb((unsigned int)port);
return (unsigned int)__ixp4xx_inb(port & PIO_MASK);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
return (unsigned int)__raw_readb((u32)port);
return (unsigned int)__raw_readb(port);
#else
return (unsigned int)__ixp4xx_readb((u32)port);
return (unsigned int)__ixp4xx_readb(port);
#endif
}
static inline void
__ixp4xx_ioread8_rep(u32 port, u8 *vaddr, u32 count)
__ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_insb(port, vaddr, count);
__ixp4xx_insb(port & PIO_MASK, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsb((void __iomem *)port, vaddr, count);
__raw_readsb(addr, vaddr, count);
#else
__ixp4xx_readsb(port, vaddr, count);
#endif
}
static inline unsigned int
__ixp4xx_ioread16(void __iomem *port)
__ixp4xx_ioread16(void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
return (unsigned int)__ixp4xx_inw((unsigned int)port);
return (unsigned int)__ixp4xx_inw(port & PIO_MASK);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
return le16_to_cpu(__raw_readw((u32)port));
@@ -425,23 +431,25 @@ __ixp4xx_ioread16(void __iomem *port)
}
static inline void
__ixp4xx_ioread16_rep(u32 port, u16 *vaddr, u32 count)
__ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_insw(port, vaddr, count);
__ixp4xx_insw(port & PIO_MASK, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsw((void __iomem *)port, vaddr, count);
__raw_readsw(addr, vaddr, count);
#else
__ixp4xx_readsw(port, vaddr, count);
#endif
}
static inline unsigned int
__ixp4xx_ioread32(void __iomem *port)
__ixp4xx_ioread32(void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
return (unsigned int)__ixp4xx_inl((unsigned int)port);
return (unsigned int)__ixp4xx_inl(port & PIO_MASK);
else {
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
return le32_to_cpu(__raw_readl((u32)port));
@@ -452,90 +460,100 @@ __ixp4xx_ioread32(void __iomem *port)
}
static inline void
__ixp4xx_ioread32_rep(u32 port, u32 *vaddr, u32 count)
__ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_insl(port, vaddr, count);
__ixp4xx_insl(port & PIO_MASK, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsl((void __iomem *)port, vaddr, count);
__raw_readsl(addr, vaddr, count);
#else
__ixp4xx_readsl(port, vaddr, count);
#endif
}
static inline void
__ixp4xx_iowrite8(u8 value, void __iomem *port)
__ixp4xx_iowrite8(u8 value, void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_outb(value, (unsigned int)port);
__ixp4xx_outb(value, port & PIO_MASK);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writeb(value, (u32)port);
__raw_writeb(value, port);
#else
__ixp4xx_writeb(value, (u32)port);
__ixp4xx_writeb(value, port);
#endif
}
static inline void
__ixp4xx_iowrite8_rep(u32 port, u8 *vaddr, u32 count)
__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_outsb(port, vaddr, count);
__ixp4xx_outsb(port & PIO_MASK, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writesb((void __iomem *)port, vaddr, count);
__raw_writesb(addr, vaddr, count);
#else
__ixp4xx_writesb(port, vaddr, count);
#endif
}
static inline void
__ixp4xx_iowrite16(u16 value, void __iomem *port)
__ixp4xx_iowrite16(u16 value, void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_outw(value, (unsigned int)port);
__ixp4xx_outw(value, port & PIO_MASK);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writew(cpu_to_le16(value), (u32)port);
__raw_writew(cpu_to_le16(value), addr);
#else
__ixp4xx_writew(value, (u32)port);
__ixp4xx_writew(value, port);
#endif
}
static inline void
__ixp4xx_iowrite16_rep(u32 port, u16 *vaddr, u32 count)
__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_outsw(port, vaddr, count);
__ixp4xx_outsw(port & PIO_MASK, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsw((void __iomem *)port, vaddr, count);
__raw_writesw(addr, vaddr, count);
#else
__ixp4xx_writesw(port, vaddr, count);
#endif
}
static inline void
__ixp4xx_iowrite32(u32 value, void __iomem *port)
__ixp4xx_iowrite32(u32 value, void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_outl(value, (unsigned int)port);
__ixp4xx_outl(value, port & PIO_MASK);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writel(cpu_to_le32(value), (u32)port);
__raw_writel(cpu_to_le32(value), port);
#else
__ixp4xx_writel(value, (u32)port);
__ixp4xx_writel(value, port);
#endif
}
static inline void
__ixp4xx_iowrite32_rep(u32 port, u32 *vaddr, u32 count)
__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_outsl(port, vaddr, count);
__ixp4xx_outsl(port & PIO_MASK, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsl((void __iomem *)port, vaddr, count);
__raw_writesl(addr, vaddr, count);
#else
__ixp4xx_outsl(port, vaddr, count);
__ixp4xx_writesl(port, vaddr, count);
#endif
}
@@ -555,7 +573,7 @@ __ixp4xx_iowrite32_rep(u32 port, u32 *vaddr, u32 count)
#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c)
#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c)
#define ioport_map(port, nr) ((void __iomem*)port)
#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
#define ioport_unmap(addr)
#endif // __ASM_ARM_ARCH_IO_H

19
include/asm-arm/arch-ixp4xx/platform.h
View File

@@ -83,17 +83,6 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
#define IXP4XX_GPIO_OUT 0x1
#define IXP4XX_GPIO_IN 0x2
#define IXP4XX_GPIO_INTSTYLE_MASK 0x7C /* Bits [6:2] define interrupt style */
/*
* GPIO interrupt types.
*/
#define IXP4XX_GPIO_ACTIVE_HIGH 0x4 /* Default */
#define IXP4XX_GPIO_ACTIVE_LOW 0x8
#define IXP4XX_GPIO_RISING_EDGE 0x10
#define IXP4XX_GPIO_FALLING_EDGE 0x20
#define IXP4XX_GPIO_TRANSITIONAL 0x40
/* GPIO signal types */
#define IXP4XX_GPIO_LOW 0
#define IXP4XX_GPIO_HIGH 1
@@ -102,7 +91,13 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
#define IXP4XX_GPIO_CLK_0 14
#define IXP4XX_GPIO_CLK_1 15
extern void gpio_line_config(u8 line, u32 style);
static inline void gpio_line_config(u8 line, u32 direction)
{
if (direction == IXP4XX_GPIO_OUT)
*IXP4XX_GPIO_GPOER |= (1 << line);
else
*IXP4XX_GPIO_GPOER &= ~(1 << line);
}
static inline void gpio_line_get(u8 line, int *value)
{

29
include/asm-arm/arch-pxa/pxa-regs.h
View File

@@ -818,6 +818,23 @@
#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
Interrupt Enable */
#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
#define UDCCSR0_SA (1 << 7) /* Setup Active */
@@ -1423,6 +1440,7 @@
#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)
#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT)
#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)
#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)
#define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT)
@@ -1510,6 +1528,8 @@
#define PSSR_BFS (1 << 1) /* Battery Fault Status */
#define PSSR_SSS (1 << 0) /* Software Sleep Status */
#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
#define PCFR_RO (1 << 15) /* RDH Override */
#define PCFR_PO (1 << 14) /* PH Override */
#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
@@ -1517,6 +1537,7 @@
#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
@@ -1810,6 +1831,11 @@
#define LCCR0_PDD_S 12
#define LCCR0_BM (1 << 20) /* Branch mask */
#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
#define LCCR0_LCDT (1 << 22) /* LCD panel type */
#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */
#define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */
#define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */
#define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */
#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
@@ -2062,7 +2088,10 @@
#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */

11
include/asm-arm/arch-s3c2410/regs-clock.h
View File

@@ -1,7 +1,7 @@
/* linux/include/asm/arch-s3c2410/regs-clock.h
*
* Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
* Copyright (c) 2003,2004,2005 Simtec Electronics <linux@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -17,6 +17,7 @@
* 29-Sep-2004 Ben Dooks Fixed usage for assembly inclusion
* 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat)
* 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA
* 27-Aug-2005 Ben Dooks Add clock-slow info
*/
#ifndef __ASM_ARM_REGS_CLOCK
@@ -74,6 +75,12 @@
#define S3C2410_CLKDIVN_PDIVN (1<<0)
#define S3C2410_CLKDIVN_HDIVN (1<<1)
#define S3C2410_CLKSLOW_UCLK_OFF (1<<7)
#define S3C2410_CLKSLOW_MPLL_OFF (1<<5)
#define S3C2410_CLKSLOW_SLOW (1<<4)
#define S3C2410_CLKSLOW_SLOWVAL(x) (x)
#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
#ifndef __ASSEMBLY__
static inline unsigned int

1
include/asm-arm/unistd.h
View File

@@ -515,7 +515,6 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
#define __ARCH_WANT_SYS_TIME
#define __ARCH_WANT_SYS_UTIME
#define __ARCH_WANT_SYS_SOCKETCALL
#define __ARCH_WANT_SYS_FADVISE64
#define __ARCH_WANT_SYS_GETPGRP
#define __ARCH_WANT_SYS_LLSEEK
#define __ARCH_WANT_SYS_NICE