From b729840b3f4e17d8bfdfea5c7de13aa79bae226d Mon Sep 17 00:00:00 2001 From: Subhash Jadavani Date: Tue, 9 Oct 2012 20:01:56 +0530 Subject: [PATCH] mmc: msm_sdcc: set DDR timing mode before setting the clock rate Setting DDR timing mode in controller before setting the clock rate will make sure that card don't see the double clock rate even for very small amount duration. Some eMMC cards seems to lock up if they see clock frequency > 52MHz. (cherry picked from commit 2877d919135791d5223a9ba94b2cfc9ba50bc3df) Signed-off-by: Subhash Jadavani Change-Id: I7a4ace461e2def6d53863db4b768ec7e497b3095 Signed-off-by: Neha Pandey --- drivers/mmc/host/msm_sdcc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c index 8bac4ef0db1..353b4391c19 100644 --- a/drivers/mmc/host/msm_sdcc.c +++ b/drivers/mmc/host/msm_sdcc.c @@ -3156,8 +3156,21 @@ msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) /* * For DDR50 mode, controller needs clock rate to be * double than what is required on the SD card CLK pin. + * + * Setting DDR timing mode in controller before setting the + * clock rate will make sure that card don't see the double + * clock rate even for very small duration. Some eMMC + * cards seems to lock up if they see clock frequency > 52MHz. */ if (ios->timing == MMC_TIMING_UHS_DDR50) { + u32 clk; + + clk = readl_relaxed(host->base + MMCICLOCK); + clk &= ~(0x7 << 14); /* clear SELECT_IN field */ + clk |= (3 << 14); /* set DDR timing mode */ + writel_relaxed(clk, host->base + MMCICLOCK); + msmsdcc_sync_reg_wr(host); + /* * Make sure that we don't double the clock if * doubled clock rate is already set