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jme: PHY configuration for compatible issue

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To perform PHY calibration and set a different EA value by chip ID,
Whenever the NIC chip power on, ie booting or resuming, we need to
force HW to calibrate PHY parameter again, and also set a proper EA
value which gather from experiment.

Those procedures help to reduce compatible issues(NIC is unable to link
up in some special case) in giga speed.

Signed-off-by: AriesLee <AriesLee@jmicron.com>
Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Aries Lee
2011-11-21 10:20:42 +00:00
committed by David S. Miller
parent de68dca181
commit c4860ba2e1
2 changed files with 129 additions and 3 deletions
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19
drivers/net/ethernet/jme.h
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@@ -760,6 +760,25 @@ enum jme_rxmcs_bits {
RXMCS_CHECKSUM,
};
/* Extern PHY common register 2 */
#define PHY_GAD_TEST_MODE_1 0x00002000
#define PHY_GAD_TEST_MODE_MSK 0x0000E000
#define JM_PHY_SPEC_REG_READ 0x00004000
#define JM_PHY_SPEC_REG_WRITE 0x00008000
#define PHY_CALIBRATION_DELAY 20
#define JM_PHY_SPEC_ADDR_REG 0x1E
#define JM_PHY_SPEC_DATA_REG 0x1F
#define JM_PHY_EXT_COMM_0_REG 0x30
#define JM_PHY_EXT_COMM_1_REG 0x31
#define JM_PHY_EXT_COMM_2_REG 0x32
#define JM_PHY_EXT_COMM_2_CALI_ENABLE 0x01
#define JM_PHY_EXT_COMM_2_CALI_MODE_0 0x02
#define JM_PHY_EXT_COMM_2_CALI_LATCH 0x10
#define PCI_PRIV_SHARE_NICCTRL 0xF5
#define JME_FLAG_PHYEA_ENABLE 0x2
/*
* Wakeup Frame setup interface registers
*/