From e3c9bccad1c5556075cde7d2d6ff37b1fb3731ed Mon Sep 17 00:00:00 2001 From: Trilok Soni Date: Sat, 26 May 2012 11:58:59 +0530 Subject: [PATCH] ARM: gic: Remove unnecessary irq spinlocks from gic_resume path Remove the unnecessary irq spinlocks from gic resume path since it always gets called with interrupt disabled. It also fixes the bug introduced by commit 6278db09f where it called spin_lock again on the same lock. CRs-Fixed: 370894 Change-Id: I94f81cc0d93f362ac233c9af637cbe75036903f9 Signed-off-by: Trilok Soni --- arch/arm/common/gic.c | 23 ++--------------------- 1 file changed, 2 insertions(+), 21 deletions(-) diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 54a839265d8..174a79937fd 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -248,28 +248,17 @@ static void gic_show_resume_irq(struct gic_chip_data *gic) u32 enabled; unsigned long pending[32]; void __iomem *base = gic_data_dist_base(gic); -#ifdef CONFIG_ARCH_MSM8625 - unsigned long flags; -#endif if (!msm_show_resume_irq_mask) return; -#ifdef CONFIG_ARCH_MSM8625 - raw_spin_lock_irqsave(&irq_controller_lock, flags); -#else raw_spin_lock(&irq_controller_lock); -#endif for (i = 0; i * 32 < gic->max_irq; i++) { enabled = readl_relaxed(base + GIC_DIST_ENABLE_CLEAR + i * 4); pending[i] = readl_relaxed(base + GIC_DIST_PENDING_SET + i * 4); pending[i] &= enabled; } -#ifdef CONFIG_ARCH_MSM8625 - raw_spin_unlock_irqrestore(&irq_controller_lock, flags); -#else - raw_spin_lock(&irq_controller_lock); -#endif + raw_spin_unlock(&irq_controller_lock); for (i = find_first_bit(pending, gic->max_irq); i < gic->max_irq; @@ -283,22 +272,14 @@ static void gic_resume_one(struct gic_chip_data *gic) { unsigned int i; void __iomem *base = gic_data_dist_base(gic); -#ifdef CONFIG_ARCH_MSM8625 - unsigned long flags; -#endif + gic_show_resume_irq(gic); for (i = 0; i * 32 < gic->max_irq; i++) { -#ifdef CONFIG_ARCH_MSM8625 - raw_spin_lock_irqsave(&irq_controller_lock, flags); -#endif /* disable all of them */ writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4); /* enable the enabled set */ writel_relaxed(gic->enabled_irqs[i], base + GIC_DIST_ENABLE_SET + i * 4); -#ifdef CONFIG_ARCH_MSM8625 - raw_spin_unlock_irqrestore(&irq_controller_lock, flags); -#endif } mb(); }