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Merge ../linus/

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This commit is contained in:
Dave Jones
2005-11-21 06:56:52 -08:00
parent c243f1f1f6 db93a82fa9
commit e7e37ee9c5
404 changed files with 8173 additions and 10897 deletions
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2
include/linux/cciss_ioctl.h
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@@ -10,8 +10,8 @@
typedef struct _cciss_pci_info_struct
{
unsigned char bus;
unsigned short domain;
unsigned char dev_fn;
unsigned short domain;
__u32 board_id;
} cciss_pci_info_struct;

67
include/linux/ds17287rtc.h Normal file
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@@ -0,0 +1,67 @@
/*
* ds17287rtc.h - register definitions for the ds1728[57] RTC / CMOS RAM
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* (C) 2003 Guido Guenther <agx@sigxcpu.org>
*/
#ifndef __LINUX_DS17287RTC_H
#define __LINUX_DS17287RTC_H
#include <linux/rtc.h> /* get the user-level API */
#include <linux/spinlock.h> /* spinlock_t */
#include <linux/mc146818rtc.h>
/* Register A */
#define DS_REGA_DV2 0x40 /* countdown chain */
#define DS_REGA_DV1 0x20 /* oscillator enable */
#define DS_REGA_DV0 0x10 /* bank select */
/* bank 1 registers */
#define DS_B1_MODEL 0x40 /* model number byte */
#define DS_B1_SN1 0x41 /* serial number byte 1 */
#define DS_B1_SN2 0x42 /* serial number byte 2 */
#define DS_B1_SN3 0x43 /* serial number byte 3 */
#define DS_B1_SN4 0x44 /* serial number byte 4 */
#define DS_B1_SN5 0x45 /* serial number byte 5 */
#define DS_B1_SN6 0x46 /* serial number byte 6 */
#define DS_B1_CRC 0x47 /* CRC byte */
#define DS_B1_CENTURY 0x48 /* Century byte */
#define DS_B1_DALARM 0x49 /* date alarm */
#define DS_B1_XCTRL4A 0x4a /* extendec control register 4a */
#define DS_B1_XCTRL4B 0x4b /* extendec control register 4b */
#define DS_B1_RTCADDR2 0x4e /* rtc address 2 */
#define DS_B1_RTCADDR3 0x4f /* rtc address 3 */
#define DS_B1_RAMLSB 0x50 /* extended ram LSB */
#define DS_B1_RAMMSB 0x51 /* extended ram MSB */
#define DS_B1_RAMDPORT 0x53 /* extended ram data port */
/* register details */
/* extended control register 4a */
#define DS_XCTRL4A_VRT2 0x80 /* valid ram and time */
#define DS_XCTRL4A_INCR 0x40 /* increment progress status */
#define DS_XCTRL4A_BME 0x20 /* burst mode enable */
#define DS_XCTRL4A_PAB 0x08 /* power active bar ctrl */
#define DS_XCTRL4A_RF 0x04 /* ram clear flag */
#define DS_XCTRL4A_WF 0x02 /* wake up alarm flag */
#define DS_XCTRL4A_KF 0x01 /* kickstart flag */
/* interrupt causes */
#define DS_XCTRL4A_IFS (DS_XCTRL4A_RF|DS_XCTRL4A_WF|DS_XCTRL4A_KF)
/* extended control register 4b */
#define DS_XCTRL4B_ABE 0x80 /* auxiliary battery enable */
#define DS_XCTRL4B_E32K 0x40 /* enable 32.768 kHz Output */
#define DS_XCTRL4B_CS 0x20 /* crystal select */
#define DS_XCTRL4B_RCE 0x10 /* ram clear enable */
#define DS_XCTRL4B_PRS 0x08 /* PAB resec select */
#define DS_XCTRL4B_RIE 0x04 /* ram clear interrupt enable */
#define DS_XCTRL4B_WFE 0x02 /* wake up alarm interrupt enable */
#define DS_XCTRL4B_KFE 0x01 /* kickstart interrupt enable */
/* interrupt enable bits */
#define DS_XCTRL4B_IFES (DS_XCTRL4B_RIE|DS_XCTRL4B_WFE|DS_XCTRL4B_KFE)
#endif /* __LINUX_DS17287RTC_H */

53
include/linux/ds1742rtc.h Normal file
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@@ -0,0 +1,53 @@
/*
* ds1742rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
*
* Copyright (C) 1999-2001 Toshiba Corporation
* Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
*
* Permission is hereby granted to copy, modify and redistribute this code
* in terms of the GNU Library General Public License, Version 2 or later,
* at your option.
*/
#ifndef __LINUX_DS1742RTC_H
#define __LINUX_DS1742RTC_H
#include <asm/ds1742.h>
#define RTC_BRAM_SIZE 0x800
#define RTC_OFFSET 0x7f8
/*
* Register summary
*/
#define RTC_CONTROL (RTC_OFFSET + 0)
#define RTC_CENTURY (RTC_OFFSET + 0)
#define RTC_SECONDS (RTC_OFFSET + 1)
#define RTC_MINUTES (RTC_OFFSET + 2)
#define RTC_HOURS (RTC_OFFSET + 3)
#define RTC_DAY (RTC_OFFSET + 4)
#define RTC_DATE (RTC_OFFSET + 5)
#define RTC_MONTH (RTC_OFFSET + 6)
#define RTC_YEAR (RTC_OFFSET + 7)
#define RTC_CENTURY_MASK 0x3f
#define RTC_SECONDS_MASK 0x7f
#define RTC_DAY_MASK 0x07
/*
* Bits in the Control/Century register
*/
#define RTC_WRITE 0x80
#define RTC_READ 0x40
/*
* Bits in the Seconds register
*/
#define RTC_STOP 0x80
/*
* Bits in the Day register
*/
#define RTC_BATT_FLAG 0x80
#define RTC_FREQ_TEST 0x40
#endif /* __LINUX_DS1742RTC_H */

6
include/linux/hdreg.h
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@@ -80,10 +80,12 @@
/*
* Define standard taskfile in/out register
*/
#define IDE_TASKFILE_STD_OUT_FLAGS 0xFE
#define IDE_TASKFILE_STD_IN_FLAGS 0xFE
#define IDE_HOB_STD_OUT_FLAGS 0x3C
#define IDE_HOB_STD_IN_FLAGS 0x3C
#ifndef __KERNEL__
#define IDE_TASKFILE_STD_OUT_FLAGS 0xFE
#define IDE_HOB_STD_OUT_FLAGS 0x3C
#endif
typedef unsigned char task_ioreg_t;
typedef unsigned long sata_ioreg_t;

30
include/linux/ide.h
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@@ -1089,9 +1089,11 @@ enum {
/*
* Subdrivers support.
*
* The gendriver.owner field should be set to the module owner of this driver.
* The gendriver.name field should be set to the name of this driver
*/
typedef struct ide_driver_s {
struct module *owner;
const char *version;
u8 media;
unsigned supports_dsc_overlap : 1;
@@ -1199,37 +1201,11 @@ extern u64 ide_get_error_location(ide_drive_t *, char *);
*/
typedef enum {
ide_wait, /* insert rq at end of list, and wait for it */
ide_next, /* insert rq immediately after current request */
ide_preempt, /* insert rq in front of current request */
ide_head_wait, /* insert rq in front of current request and wait for it */
ide_end /* insert rq at end of list, but don't wait for it */
} ide_action_t;
/*
* This function issues a special IDE device request
* onto the request queue.
*
* If action is ide_wait, then the rq is queued at the end of the
* request queue, and the function sleeps until it has been processed.
* This is for use when invoked from an ioctl handler.
*
* If action is ide_preempt, then the rq is queued at the head of
* the request queue, displacing the currently-being-processed
* request and this function returns immediately without waiting
* for the new rq to be completed. This is VERY DANGEROUS, and is
* intended for careful use by the ATAPI tape/cdrom driver code.
*
* If action is ide_next, then the rq is queued immediately after
* the currently-being-processed-request (if any), and the function
* returns without waiting for the new rq to be completed. As above,
* This is VERY DANGEROUS, and is intended for careful use by the
* ATAPI tape/cdrom driver code.
*
* If action is ide_end, then the rq is queued at the end of the
* request queue, and the function returns immediately without waiting
* for the new rq to be completed. This is again intended for careful
* use by the ATAPI tape/cdrom driver code.
*/
extern int ide_do_drive_cmd(ide_drive_t *, struct request *, ide_action_t);
/*

2
include/linux/mm.h
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@@ -940,7 +940,9 @@ unsigned long max_sane_readahead(unsigned long nr);
/* Do stack extension */
extern int expand_stack(struct vm_area_struct *vma, unsigned long address);
#ifdef CONFIG_IA64
extern int expand_upwards(struct vm_area_struct *vma, unsigned long address);
#endif
/* Look up the first VMA which satisfies addr < vm_end, NULL if none. */
extern struct vm_area_struct * find_vma(struct mm_struct * mm, unsigned long addr);

3
include/linux/pci_ids.h
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@@ -620,6 +620,7 @@
#define PCI_DEVICE_ID_SI_961 0x0961
#define PCI_DEVICE_ID_SI_962 0x0962
#define PCI_DEVICE_ID_SI_963 0x0963
#define PCI_DEVICE_ID_SI_965 0x0965
#define PCI_DEVICE_ID_SI_5511 0x5511
#define PCI_DEVICE_ID_SI_5513 0x5513
#define PCI_DEVICE_ID_SI_5518 0x5518
@@ -1235,6 +1236,7 @@
#define PCI_DEVICE_ID_VIA_8703_51_0 0x3148
#define PCI_DEVICE_ID_VIA_8237_SATA 0x3149
#define PCI_DEVICE_ID_VIA_XN266 0x3156
#define PCI_DEVICE_ID_VIA_6410 0x3164
#define PCI_DEVICE_ID_VIA_8754C_0 0x3168
#define PCI_DEVICE_ID_VIA_8235 0x3177
#define PCI_DEVICE_ID_VIA_8385_0 0x3188
@@ -1402,6 +1404,7 @@
#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334
#define PCI_VENDOR_ID_MARVELL 0x11ab
#define PCI_DEVICE_ID_MARVELL_GT64111 0x4146
#define PCI_DEVICE_ID_MARVELL_GT64260 0x6430
#define PCI_DEVICE_ID_MARVELL_MV64360 0x6460
#define PCI_DEVICE_ID_MARVELL_MV64460 0x6480

13
include/linux/uinput.h
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@@ -34,8 +34,7 @@
#define UINPUT_BUFFER_SIZE 16
#define UINPUT_NUM_REQUESTS 16
/* state flags => bit index for {set|clear|test}_bit ops */
#define UIST_CREATED 0
enum uinput_state { UIST_NEW_DEVICE, UIST_SETUP_COMPLETE, UIST_CREATED };
struct uinput_request {
int id;
@@ -52,11 +51,12 @@ struct uinput_request {
struct uinput_device {
struct input_dev *dev;
unsigned long state;
struct semaphore sem;
enum uinput_state state;
wait_queue_head_t waitq;
unsigned char ready,
head,
tail;
unsigned char ready;
unsigned char head;
unsigned char tail;
struct input_event buff[UINPUT_BUFFER_SIZE];
struct uinput_request *requests[UINPUT_NUM_REQUESTS];
@@ -91,6 +91,7 @@ struct uinput_ff_erase {
#define UI_SET_SNDBIT _IOW(UINPUT_IOCTL_BASE, 106, int)
#define UI_SET_FFBIT _IOW(UINPUT_IOCTL_BASE, 107, int)
#define UI_SET_PHYS _IOW(UINPUT_IOCTL_BASE, 108, char*)
#define UI_SET_SWBIT _IOW(UINPUT_IOCTL_BASE, 109, int)
#define UI_BEGIN_FF_UPLOAD _IOWR(UINPUT_IOCTL_BASE, 200, struct uinput_ff_upload)
#define UI_END_FF_UPLOAD _IOW(UINPUT_IOCTL_BASE, 201, struct uinput_ff_upload)