Merge phase #4 (X2APIC, APIC unification, CPU identification unification) of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-v28-for-linus-phase4-D' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (186 commits) x86, debug: print more information about unknown CPUs x86 setup: handle more than 8 CPU flag words x86: cpuid, fix typo x86: move transmeta cap read to early_init_transmeta() x86: identify_cpu_without_cpuid v2 x86: extended "flags" to show virtualization HW feature in /proc/cpuinfo x86: move VMX MSRs to msr-index.h x86: centaur_64.c remove duplicated setting of CONSTANT_TSC x86: intel.c put workaround for old cpus together x86: let intel 64-bit use intel.c x86: make intel_64.c the same as intel.c x86: make intel.c have 64-bit support code x86: little clean up of intel.c/intel_64.c x86: make 64 bit to use amd.c x86: make amd_64 have 32 bit code x86: make amd.c have 64bit support code x86: merge header in amd_64.c x86: add srat_detect_node for amd64 x86: remove duplicated force_mwait x86: cpu make amd.c more like amd_64.c v2 ...
This commit is contained in:
Linus Torvalds
@@ -25,9 +25,99 @@
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#include <linux/types.h>
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#include <linux/msi.h>
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#ifdef CONFIG_DMAR
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#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
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struct intel_iommu;
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struct dmar_drhd_unit {
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struct list_head list; /* list of drhd units */
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struct acpi_dmar_header *hdr; /* ACPI header */
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u64 reg_base_addr; /* register base address*/
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struct pci_dev **devices; /* target device array */
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int devices_cnt; /* target device count */
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u8 ignored:1; /* ignore drhd */
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u8 include_all:1;
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struct intel_iommu *iommu;
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};
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extern struct list_head dmar_drhd_units;
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#define for_each_drhd_unit(drhd) \
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list_for_each_entry(drhd, &dmar_drhd_units, list)
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extern int dmar_table_init(void);
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extern int early_dmar_detect(void);
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extern int dmar_dev_scope_init(void);
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/* Intel IOMMU detection */
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extern void detect_intel_iommu(void);
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extern int parse_ioapics_under_ir(void);
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extern int alloc_iommu(struct dmar_drhd_unit *);
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#else
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static inline void detect_intel_iommu(void)
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{
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return;
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}
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static inline int dmar_table_init(void)
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{
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return -ENODEV;
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}
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#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */
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#ifdef CONFIG_INTR_REMAP
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extern int intr_remapping_enabled;
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extern int enable_intr_remapping(int);
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struct irte {
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union {
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struct {
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__u64 present : 1,
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fpd : 1,
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dst_mode : 1,
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redir_hint : 1,
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trigger_mode : 1,
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dlvry_mode : 3,
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avail : 4,
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__reserved_1 : 4,
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vector : 8,
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__reserved_2 : 8,
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dest_id : 32;
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};
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__u64 low;
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};
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union {
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struct {
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__u64 sid : 16,
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sq : 2,
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svt : 2,
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__reserved_3 : 44;
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};
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__u64 high;
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};
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};
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extern int get_irte(int irq, struct irte *entry);
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extern int modify_irte(int irq, struct irte *irte_modified);
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extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
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extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
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u16 sub_handle);
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extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
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extern int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index);
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extern int flush_irte(int irq);
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extern int free_irte(int irq);
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extern int irq_remapped(int irq);
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extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
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extern struct intel_iommu *map_ioapic_to_ir(int apic);
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#else
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#define irq_remapped(irq) (0)
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#define enable_intr_remapping(mode) (-1)
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#define intr_remapping_enabled (0)
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#endif
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#ifdef CONFIG_DMAR
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extern const char *dmar_get_fault_reason(u8 fault_reason);
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/* Can't use the common MSI interrupt functions
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@@ -40,47 +130,30 @@ extern void dmar_msi_write(int irq, struct msi_msg *msg);
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extern int dmar_set_interrupt(struct intel_iommu *iommu);
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extern int arch_setup_dmar_msi(unsigned int irq);
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/* Intel IOMMU detection and initialization functions */
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extern void detect_intel_iommu(void);
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extern int intel_iommu_init(void);
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extern int dmar_table_init(void);
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extern int early_dmar_detect(void);
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extern struct list_head dmar_drhd_units;
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extern int iommu_detected, no_iommu;
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extern struct list_head dmar_rmrr_units;
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struct dmar_drhd_unit {
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struct list_head list; /* list of drhd units */
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u64 reg_base_addr; /* register base address*/
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struct pci_dev **devices; /* target device array */
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int devices_cnt; /* target device count */
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u8 ignored:1; /* ignore drhd */
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u8 include_all:1;
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struct intel_iommu *iommu;
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};
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struct dmar_rmrr_unit {
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struct list_head list; /* list of rmrr units */
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struct acpi_dmar_header *hdr; /* ACPI header */
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u64 base_address; /* reserved base address*/
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u64 end_address; /* reserved end address */
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struct pci_dev **devices; /* target devices */
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int devices_cnt; /* target device count */
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};
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#define for_each_drhd_unit(drhd) \
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list_for_each_entry(drhd, &dmar_drhd_units, list)
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#define for_each_rmrr_units(rmrr) \
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list_for_each_entry(rmrr, &dmar_rmrr_units, list)
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/* Intel DMAR initialization functions */
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extern int intel_iommu_init(void);
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extern int dmar_disabled;
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#else
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static inline void detect_intel_iommu(void)
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{
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return;
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}
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static inline int intel_iommu_init(void)
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{
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#ifdef CONFIG_INTR_REMAP
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return dmar_dev_scope_init();
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#else
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return -ENODEV;
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#endif
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}
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#endif /* !CONFIG_DMAR */
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#endif /* __DMAR_H__ */
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@@ -108,6 +108,9 @@ extern struct resource iomem_resource;
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extern int request_resource(struct resource *root, struct resource *new);
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extern int release_resource(struct resource *new);
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extern void reserve_region_with_split(struct resource *root,
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resource_size_t start, resource_size_t end,
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const char *name);
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extern int insert_resource(struct resource *parent, struct resource *new);
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extern void insert_resource_expand_to_fit(struct resource *root, struct resource *new);
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extern int allocate_resource(struct resource *root, struct resource *new,
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@@ -62,6 +62,7 @@ typedef void (*irq_flow_handler_t)(unsigned int irq,
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#define IRQ_MOVE_PENDING 0x00200000 /* need to re-target IRQ destination */
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#define IRQ_NO_BALANCING 0x00400000 /* IRQ is excluded from balancing */
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#define IRQ_SPURIOUS_DISABLED 0x00800000 /* IRQ was disabled by the spurious trap */
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#define IRQ_MOVE_PCNTXT 0x01000000 /* IRQ migration from process context */
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#ifdef CONFIG_IRQ_PER_CPU
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# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
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@@ -23,12 +23,19 @@
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__attribute__((__section__(SHARED_ALIGNED_SECTION))) \
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PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name \
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____cacheline_aligned_in_smp
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#define DEFINE_PER_CPU_PAGE_ALIGNED(type, name) \
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__attribute__((__section__(".data.percpu.page_aligned"))) \
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PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name
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#else
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#define DEFINE_PER_CPU(type, name) \
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PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name
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#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \
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DEFINE_PER_CPU(type, name)
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#define DEFINE_PER_CPU_PAGE_ALIGNED(type, name) \
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DEFINE_PER_CPU(type, name)
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#endif
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#define EXPORT_PER_CPU_SYMBOL(var) EXPORT_SYMBOL(per_cpu__##var)
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