[MTD] Support for protection register support on Intel FLASH chips
This enables support for reading, writing and locking so called "Protection Registers" present on some flash chips. A subset of them are pre-programmed at the factory with a unique set of values. The rest is user-programmable. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Thomas Gleixner
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67d9e95c39
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f77814dd57
@@ -1,7 +1,7 @@
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/* Common Flash Interface structures
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* See http://support.intel.com/design/flash/technote/index.htm
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* $Id: cfi.h,v 1.51 2005/02/05 02:06:16 nico Exp $
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* $Id: cfi.h,v 1.52 2005/02/08 17:11:15 nico Exp $
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*/
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#ifndef __MTD_CFI_H__
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@@ -252,7 +252,7 @@ static inline uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs, int interleave, int
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* It looks too long to be inline, but in the common case it should almost all
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* get optimised away.
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*/
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static inline map_word cfi_build_cmd(u_char cmd, struct map_info *map, struct cfi_private *cfi)
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static inline map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi)
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{
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map_word val = { {0} };
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int wordwidth, words_per_bus, chip_mode, chips_per_word;
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