This patch converts dma_alloc/free/mmap_{coherent,writecombine}
functions to use generic alloc/free/mmap methods from dma_map_ops
structure. A new DMA_ATTR_WRITE_COMBINE DMA attribute have been
introduced to implement writecombine methods.
Change-Id: I2709e3ffc97546df2f505d555b29c3bb8148daec
[lauraa: context conflicts]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-By: Subash Patel <subash.ramaswamy@linaro.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
This patch removes dma bounce hooks from the common dma mapping
implementation on ARM architecture and creates a separate set of
dma_map_ops for dma bounce devices.
Change-Id: I42d7869b4f74ffa5f36a4a7526bc0c55aaf6bab7
[lauraa: conflicts due to code cruft]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-By: Subash Patel <subash.ramaswamy@linaro.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
The write_val argument was not specified as an input
on the asm instruction. The compiler thought it wasn't used,
even though the asm instruction does use r0, which
is how write_val is passed into the function. The compiler
would optimise out the argument being passed into
the function.
Add write_val as an input operand to prevent it being
optimised out.
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
(cherry picked from commit e1bb10a173de0327171c2c8d16f64af34a5ca937)
Change-Id: I478f79a1a34a4ee15516a1765f8c6094191454fd
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
The genirq layer expects a 0 in case of failure. The current code is
returning -ENXIO for an error.
Fix it.
Change-Id: I0985f12477d472f4fbef525f7b04fed9bf593686
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Ajay Dudani <adudani@codeaurora.org>
This patch removes the need for the offset parameter in dma bounce
functions. This is required to let dma-mapping framework on ARM
architecture to use common, generic dma_map_ops based dma-mapping
helpers.
Background and more detailed explaination:
dma_*_range_* functions are available from the early days of the dma
mapping api. They are the correct way of doing a partial syncs on the
buffer (usually used by the network device drivers). This patch changes
only the internal implementation of the dma bounce functions to let
them tunnel through dma_map_ops structure. The driver api stays
unchanged, so driver are obliged to call dma_*_range_* functions to
keep code clean and easy to understand.
The only drawback from this patch is reduced detection of the dma api
abuse. Let us consider the following code:
dma_addr = dma_map_single(dev, ptr, 64, DMA_TO_DEVICE);
dma_sync_single_range_for_cpu(dev, dma_addr+16, 0, 32, DMA_TO_DEVICE);
Without the patch such code fails, because dma bounce code is unable
to find the bounce buffer for the given dma_address. After the patch
the above sync call will be equivalent to:
dma_sync_single_range_for_cpu(dev, dma_addr, 16, 32, DMA_TO_DEVICE);
which succeeds.
I don't consider this as a real problem, because DMA API abuse should be
caught by debug_dma_* function family. This patch lets us to simplify
the internal low-level implementation without chaning the driver visible
API.
Change-Id: I9a847e30f345bf5e69fded1747ff79057750fb66
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-By: Subash Patel <subash.ramaswamy@linaro.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Remove modem_wake and from_idle parameters from msm_gic_save
API since they are not used at all.
Change-Id: Icd1a83aea6b0eb988c19ccdbaf65b1f5be9e8ac2
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
MSM8625 v1.0 needs the s/w workaround for hready pin access problem
in QGIC2. The workaround is add the lock around every QGIC2 register's
read and write operation to avoid reading the incorrect value from the
QGIC2 registers when back to back read happens on another CPU.
Change-Id: If980c03d2c57b0b9c560b5a746db0535584841d9
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
msm_gic_save/restore APIs were added to save the context of the
GIC across the apps. power collapse since 8625 PM framework
doesn't use the CPUIdle framework of the kernel. If the CPUIdle
framework was in use then we could have used the GIC driver provided
notification mechanism which takes of calling appropriate functions.
There is no need to protect these APIs using this #ifdef since there
is nothing specific to 8625 inside, also add empty functions for save
and restore since not all targets have CPU_PM defined.
Change-Id: I02bb4e4021c31caf7ab1282fb675d45ffba42a66
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Use a label instead of using function start address. It's not
guaranteed that the compiler will make the mrc instruction
the first instruction in the function.
Self-modifying code replaces the dummy instruction with a new
instruction during runtime according to user inputs.
Change-Id: I8c37f4e414ce5983f0317a51a3cf790b45763bfc
Acked-by: Suren Eda Naarayana Kulothungan <sedanaar@qualcomm.com>
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
The following merge commit chose the irq_domain implementation
from AU_LINUX_ANDROID_ICS.04.00.04.00.126 instead of the version
in v3.4.
commit f132c6cf77251e011e1dad0ec88c0b1fda16d5aa
Merge: 23016de 3f6240f
Author: Steve Muckle <smuckle@codeaurora.org>
Date: Wed Jun 6 18:30:57 2012 -0700
Merge commit 'AU_LINUX_ANDROID_ICS.04.00.04.00.126' into
msm-3.4
Since this version is inconsistent with the upstream,
port the irq_domain framework to the version in v3.4 and
makes all necessary changes to clients that are out of spec.
Details of client ports are below.
-Update the qpnp-int driver for revmap irq_domain API. The revmap
irq_domain implementation introduces a reverse lookup scheme using
a radix tree. This scheme is useful for controllers like qpnp-int
that require a large range of hwirqs.
-Bring the ARM GIC driver up to v3.4, being careful
to port existing CAF changes.
-Partially port the gpio-msm-common driver to the new irq_domain API.
Enable the gpio-msm-common driver to work with the new irq_domain
API using a linear revmap. It is not a full port since irq_domain
is still only registered for Device Tree configurations. It should
be registered even for legacy configurations.
In addition, the irq_domains .map function should be setting all
the fields currently done in msm_gpio_probe(). That's not
currently possible since msm_gpio_probe is invoked
unconditionally - even from Device Tree configurations.
Finally, gpio-msm-common should be converted into a real
platform_device so that probe() is invoked due to driver and
device matching.
Change-Id: I19fa50171bd244759fb6076e3cddc70896d8727b
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Rename gic_is_spi_pending and gic_clear_spi_pending APIs
to generic gic_is_irq_pending and gic_clear_irq_pending names
since this API could be used for anyother interrupts, and while
at it also use proper style for the multi-line comments around
these APIs.
Change-Id: I7d440f3caa0ebc77483d1ba43eff7932d5ac6666
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Remove the unnecessary irq spinlocks from gic resume path since it
always gets called with interrupt disabled. It also fixes the bug
introduced by commit 6278db09f where it called spin_lock again on the same
lock.
CRs-Fixed: 370894
Change-Id: I94f81cc0d93f362ac233c9af637cbe75036903f9
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Fix NR_IPI to be 7 instead of 6 because both googly and core add
an IPI.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Conflicts:
arch/arm/Kconfig
arch/arm/common/Makefile
arch/arm/include/asm/hardware/cache-l2x0.h
arch/arm/mm/cache-l2x0.c
arch/arm/mm/mmu.c
include/linux/wakelock.h
kernel/power/Kconfig
kernel/power/Makefile
kernel/power/main.c
kernel/power/power.h
This API now returns an error. Since gic_init_bases() is called
early on, there's probably not a whole lot we can do here except
send a warning.
Change-Id: I2835dacfa191db0ce70434de23e6ee540fe33b57
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Conflicts:
arch/arm/common/gic.c
Recently a change was added to break apart irq_domain_add() into
two functions. The first creates the domain, and the second
registers it.
This change abides to this new interface and registers the
GIC irq_domain after creating it.
Change-Id: I34c6a1f56dc27113a9b72f0fefa577276f91bbc8
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Conflicts:
arch/arm/common/gic.c
We may enter PC from either suspend or idle path. So even
if we enter from suspend path we should disable all interrupts
before we go to Power collapse, so as to make sure, there
are no pending interrupts(not even the wakeup capable) which
could result in WFI failure.
CRs-Fixed: 363293
Change-Id: Ied25b21f59a9fa0a891a27a2e806876cc337a759
Signed-off-by: Taniya Das <tdas@codeaurora.org>
(cherry picked from commit 8862d7d2202f33a6fe2f219aca0b2d7bb62b570e)
msm_gic_spi_ppi_pending, msm_gic_save and core1_gic_configure_and_raise
gets called with interrupt enabled on the core0, so it is possible
that we get into the spinlock deadlock since interrupt like timer PPI
could get fired on core0 and get locked in gic_handle_irq() routine
itself, so move these spinlocks to irqsave variants to avoid this
scenario.
CRs-Fixed: 363249
Change-Id: I2d40d6e26f5d9dba4ee6b9d4602cd0e685226693
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
(cherry picked from commit 6278db09f0535ca05d6bc12bfbb4ef4aa9da0652)
Conflicts:
arch/arm/common/gic.c
Moving code which modifies the GIC registers. As there is no global
lock in gic code, moving the code out.
Change-Id: I85a2bd580dbeefc942a3307f3c0cad8b1da509b7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
(cherry picked from commit bc9248ab6fd94f9f5f2a818e7d8b67645b4310cb)
Conflicts:
arch/arm/common/gic.c
arch/arm/mach-msm/mpm-8625.c
arch/arm/mach-msm/platsmp-8625.c
On 8625 due to bug in AHB MUX on hready, back to back write followed
by read (from any CPU) on QGIC2 registers (SGIR(WO) ,IAR(RO) and
write on EOI(WO)) cause the read data to get corrupted on AHB bus.
Due to this whenever a valid irq has occurs, and dispatched to the cpu
interface but still cpu reads the IAR as 0x0 and that particular IRQ
becomes active.
But due to incorrect irq id (read as 0x0), IRQ handler will not do
proper EOI for that particular interrupt and thus it gets trapped
in the active state.
Below is the qgic register dump from CPU-1, in this particular case
we see that SGI-3 is not getting clear as cpu reads this as 0x0.
AZSD:C0000200| 00240008 00000000 00008000 00000000 00000000 00000000
00000000 00000000 ..$.............................
AZSD:C0000280| 00240008 00000000 00008000 00000000 00000000 00000000
00000000 00000000 ..$.............................
AZSD:C0000300| 00040008 00000000 00000000 00000000 00000000 00000000
00000000 00000000 ................................
AZSD:C0000380| 00040008 00000000 00000000 00000000 00000000 00000000
00000000 00000000 ................................
As the interrupt gets trapped, no other interrupt received on the core is
services any more causing the system hang.
CRs-Fixed: 349219
Change-Id: Icad2c65114377a08984b1032566cfba811bb4ca8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
(cherry picked from commit 6639886be3b2326bcce81a3d553bc91b6de793ac)
Currently gic secure mode is enabled for all the v7 cpus.
For 8x25 we do not want to access GIC in secure mode as
we are observe issues of not able to clear the pending clear
registers when we come out of power collapse.
The Kconfig should make it flexible for targets who want to
support GIC in secure/non-secure modes.
Change-Id: Id7c85f5b741346233993966752607e5c4fb23e74
Signed-off-by: Taniya Das <tdas@codeaurora.org>
(cherry picked from commit b241bd843145b76dcd87697a53d8f8cf1952b9d1)
Conflicts:
arch/arm/mach-msm/Kconfig
Configure the GIC to run in secure mode and handle
secure as well as non-secure interrupts. This patch
adds an API to configure an IRQ as a secure IRQ so that
it can be treated as an FIQ in the secure mode.
Change-Id: Ic3321e76c95a4c10d6287ba418e84623e7004cb1
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit 26e44869e1e730ec7434e899dfd5857530b63415)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/gic.h
This change is to satisfy the logging requirement of
wakeup interrupts. Add code to log the trigger status
of wakeup interrupts. This helps in debugging
the cause of wakeup when the system is suspended
Change-Id: I0f724296f9133433cdbc3271a9b91c6fa992a2ff
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
(cherry picked from commit c0dde6391c0d4971f5669e970a95b2e6885e36eb)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/gic.h
While in suspend state, the system should not wake up due to triggering
of a non wakeup interrupt. Implement suspend and resume functions to be
called from power management code to switch enabled interrupts between
wakeup set or normal set.
Change-Id: Iaceae286707460eadc5f05c0baef72b43c942777
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
(cherry picked from commit 3f2f06c6205445266aabdb9c843da70a4dd5d22f)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/gic.h
Some kernel code needs to check for and clear specific pending
interrupt explicitly. The polling and clearing may happen in
contexts where interrupts are masked off at the cpu level.
Change-Id: Icba9bb2f05e9fc61dd48c4174c4d276ab20b4244
Signed-off-by: Ai Li <aili@codeaurora.org>
(cherry picked from commit 20b3c0ee6e4852af8c52fb5f98188530760c8c74)
Conflicts:
arch/arm/include/asm/hardware/gic.h
Use smp_call_function_single only for SMP systems. For
single cores, call the function directly. Use CONFIG_SMP
to determine if its a SMP system.
Change-Id: I310d8e449ba1fd00318cb4454b3bc840f67230aa
Signed-off-by: Suren Eda Naarayana Kulothungan <sedanaar@codeaurora.org>
(cherry picked from commit 2c9001b514daecea0433ed0e23fc60b1513ac379)
Declare function as noinline so that function which changes
during run time does not get inlined and instead gets called.
Without this, the function contents get inlined while
optimization is turned on.
Change-Id: I8533b0c5a83ed48346a2846e7cd531b8907f82d8
Signed-off-by: Suren Eda Naarayana Kulothungan <sedanaar@codeaurora.org>
(cherry picked from commit 42b0f68886094aa319aa9ca8da72c5ac394dd1e9)
Calls the mmu function to ensure that kernel space is
write-enabled before writing the updated CP15
instruction. Removes the unnecessary write of the
constant bx lr instruction.
Change-Id: Idfe44bb89e793b009b17565e7486f3a6e8cdf582
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
(cherry picked from commit 7673a8753ade677b02fbc013f95958d2ee815ba0)
The commit 292b293 creates the MSM boot failures, so squash
the commit 28af690 with it to avoid such failures. The commit ddd847
and 0c1991 are required to keep the watchdog and Copper targets working.
commit 292b293cee
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Wed Jul 20 16:24:14 2011 +0100
ARM: gic: consolidate PPI handling
PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).
Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.
This also allows the removal of some duplicated code.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit 28af690a28
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Fri Jul 22 12:52:37 2011 +0100
ARM: gic, local timers: use the request_percpu_irq() interface
This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).
PPIs are now useable for more than just the local timers.
Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).
Cc: David Brown <davidb@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit ddd8478d68f8cf75ee9771667c0cbe2a9d1caeb9
Author: Trilok Soni <tsoni@codeaurora.org>
Date: Tue Dec 6 00:56:01 2011 +0530
msm: watchdog: Use request_percpu_irq() interface
Change-Id: I7c319344f6a7f7a7c70682ac87f5c385e56d130c
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
commit 0c19915e092214a4c17a9920c4c1f3d78610217d
Author: Sathish Ambley <sambley@codeaurora.org>
Date: Fri Dec 9 17:07:37 2011 +0530
arm: arch_timer: Use request_percpu_irq() API
Change-Id: Iee9b218d538f315cd884a47d95bcc0dcc49b0fe1
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
Change-Id: I7bbba706b1f2e55814be5891ed76063725c2bfb1
Signed-off-by: Ravi Kumar <kumarrav@codeaurora.org>
[tsoni@codeaurora.org: MSM specific fixes]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
(cherry picked from commit eecb28c59054b1b9d8b9f410a903f87c8eb1ac48)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/entry-macro-gic.S
arch/arm/include/asm/localtimer.h
arch/arm/include/asm/smp.h
arch/arm/include/asm/smp_twd.h
arch/arm/kernel/smp.c
arch/arm/kernel/smp_twd.c
arch/arm/mach-exynos4/include/mach/entry-macro.S
arch/arm/mach-exynos4/mct.c
arch/arm/mach-msm/board-8064.c
arch/arm/mach-msm/board-8960.c
arch/arm/mach-msm/board-copper.c
arch/arm/mach-msm/board-dt.c
arch/arm/mach-msm/devices-9615.c
arch/arm/mach-msm/devices-msm8x60.c
arch/arm/mach-msm/include/mach/entry-macro-qgic.S
arch/arm/mach-msm/msm_watchdog.c
arch/arm/mach-msm/timer.c
arch/arm/mach-omap2/include/mach/entry-macro.S
Added indirect L2 rw support to cpaccess kernel module. Input format
change to include a parameter to specify register access type. Validation
if register type is one of supported types.
Change-Id: I5bd52c89d87a4fb4da4248526e56079bb604f910
Signed-off-by: Suren Eda Naarayana Kulothungan <sedanaar@codeaurora.org>
(cherry picked from commit 4c317fbf87a93d8e34e33063b6164e5d5c32cdd0)
The tool can be used to read/write to CP registers by
passing the CP parameters through /sys interface. SMP
support added.
Change-Id: I01d3621f2b6f17d959a237d207b817992404ef88
Signed-off-by: Suren Eda Naarayana Kulothungan <sedanaar@codeaurora.org>
(cherry picked from commit c399b9755096e95036362f00f819c28650eb1a10)
Conflicts:
arch/arm/Kconfig
arch/arm/common/Makefile
handle_IRQ may briefly cause interrupts to be re-enabled during soft IRQ
processing on the exit path, leading to nested handling of VIC interrupts.
Since the current code does not re-read the VIC_IRQ_STATUS register, this
can lead to multiple invocations of the same interrupt handler and
spurious interrupts to be reported.
This patch changes the VIC interrupt dispatching code to re-read the
status register each time, avoiding duplicate invocations of the same
handler.
Acked-and-Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix setting up consoles on multiple fiq debugger devices by
splitting the tty driver init into the initcall, and initializing
the single tty device during probe. Has the side effect of moving
the tty device node to /dev/ttyFIQx, where x is the platform device
id, which should normally match the serial port.
To avoid having to pass a different console=/dev/ttyFIQx for every
device, make the fiq debugger a preferred console that will be used
by default if no console was passed on the command line.
Change-Id: I6cc2670628a41e84615859bc96adba189966d647
Signed-off-by: Colin Cross <ccross@android.com>
Adds polling tty ops to the fiq debugger console tty, which allows
kgdb to run against an fiq debugger console.
Add a check in do_sysrq to prevent enabling kgdb from the fiq
debugger unless a flag (writable only by root) has been set. This
should make it safe to enable KGDB on a production device.
Also add a shortcut to enable the console and kgdb together, to
allow kgdb to be enabled when the shell on the console is not
responding.
Change-Id: Ifc65239ca96c9887431a6a36b9b44a539002f544
Signed-off-by: Colin Cross <ccross@android.com>
Convert all the calls to state->pdata->uart_putc to a debug_putc
helper.
Change-Id: Idc007bd170ff1b51d0325e238105ae0c86d23777
Signed-off-by: Colin Cross <ccross@android.com>
Pass the rest of the reboot command to kernel_restart to allow
reboot bootloader to work from FIQ debugger.
Change-Id: I4e7b366a69268dda17ffcf4c84f2373d15cb1271
Signed-off-by: Colin Cross <ccross@android.com>
Call kernel_restart instead of arch_reset, the ARM reset handling
has changed.
Remove localtimer irq printing, they now show up in the regular
irq stats.
Change-Id: I523da343b292c5711f3e1cbfd766d32eea2da84e
Signed-off-by: Colin Cross <ccross@android.com>
Pull more ARM updates from Russell King.
This got a fair number of conflicts with the <asm/system.h> split, but
also with some other sparse-irq and header file include cleanups. They
all looked pretty trivial, though.
* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (59 commits)
ARM: fix Kconfig warning for HAVE_BPF_JIT
ARM: 7361/1: provide XIP_VIRT_ADDR for no-MMU builds
ARM: 7349/1: integrator: convert to sparse irqs
ARM: 7259/3: net: JIT compiler for packet filters
ARM: 7334/1: add jump label support
ARM: 7333/2: jump label: detect %c support for ARM
ARM: 7338/1: add support for early console output via semihosting
ARM: use set_current_blocked() and block_sigmask()
ARM: exec: remove redundant set_fs(USER_DS)
ARM: 7332/1: extract out code patch function from kprobes
ARM: 7331/1: extract out insn generation code from ftrace
ARM: 7330/1: ftrace: use canonical Thumb-2 wide instruction format
ARM: 7351/1: ftrace: remove useless memory checks
ARM: 7316/1: kexec: EOI active and mask all interrupts in kexec crash path
ARM: Versatile Express: add NO_IOPORT
ARM: get rid of asm/irq.h in asm/prom.h
ARM: 7319/1: Print debug info for SIGBUS in user faults
ARM: 7318/1: gic: refactor irq_start assignment
ARM: 7317/1: irq: avoid NULL check in for_each_irq_desc loop
ARM: 7315/1: perf: add support for the Cortex-A7 PMU
...
Pull slave-dmaengine update from Vinod Koul:
"This includes the cookie cleanup by Russell, the addition of context
parameter for dmaengine APIs, more arm dmaengine driver cleanup by
moving code to dmaengine, this time for imx by Javier and pl330 by
Boojin along with the usual driver fixes."
Fix up some fairly trivial conflicts with various other cleanups.
* 'next' of git://git.infradead.org/users/vkoul/slave-dma: (67 commits)
dmaengine: imx: fix the build failure on x86_64
dmaengine: i.MX: Fix merge of cookie branch.
dmaengine: i.MX: Add support for interleaved transfers.
dmaengine: imx-dma: use 'dev_dbg' and 'dev_warn' for messages.
dmaengine: imx-dma: remove 'imx_dmav1_baseaddr' and 'dma_clk'.
dmaengine: imx-dma: remove unused arg of imxdma_sg_next.
dmaengine: imx-dma: remove internal structure.
dmaengine: imx-dma: remove 'resbytes' field of 'internal' structure.
dmaengine: imx-dma: remove 'in_use' field of 'internal' structure.
dmaengine: imx-dma: remove sg member from internal structure.
dmaengine: imx-dma: remove 'imxdma_setup_sg_hw' function.
dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function.
dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
dmaengine: imx-dma: remove dma_mode member of internal structure.
dmaengine: imx-dma: remove data member from internal structure.
dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
dmaengine: at_hdmac: add slave config operation
dmaengine: add context parameter to prep_slave_sg and prep_dma_cyclic
dmaengine/dma_slave: introduce inline wrappers
dma: imx-sdma: Treat firmware messages as warnings instead of erros
...
Pull "Disintegrate and delete asm/system.h" from David Howells:
"Here are a bunch of patches to disintegrate asm/system.h into a set of
separate bits to relieve the problem of circular inclusion
dependencies.
I've built all the working defconfigs from all the arches that I can
and made sure that they don't break.
The reason for these patches is that I recently encountered a circular
dependency problem that came about when I produced some patches to
optimise get_order() by rewriting it to use ilog2().
This uses bitops - and on the SH arch asm/bitops.h drags in
asm-generic/get_order.h by a circuituous route involving asm/system.h.
The main difficulty seems to be asm/system.h. It holds a number of
low level bits with no/few dependencies that are commonly used (eg.
memory barriers) and a number of bits with more dependencies that
aren't used in many places (eg. switch_to()).
These patches break asm/system.h up into the following core pieces:
(1) asm/barrier.h
Move memory barriers here. This already done for MIPS and Alpha.
(2) asm/switch_to.h
Move switch_to() and related stuff here.
(3) asm/exec.h
Move arch_align_stack() here. Other process execution related bits
could perhaps go here from asm/processor.h.
(4) asm/cmpxchg.h
Move xchg() and cmpxchg() here as they're full word atomic ops and
frequently used by atomic_xchg() and atomic_cmpxchg().
(5) asm/bug.h
Move die() and related bits.
(6) asm/auxvec.h
Move AT_VECTOR_SIZE_ARCH here.
Other arch headers are created as needed on a per-arch basis."
Fixed up some conflicts from other header file cleanups and moving code
around that has happened in the meantime, so David's testing is somewhat
weakened by that. We'll find out anything that got broken and fix it..
* tag 'split-asm_system_h-for-linus-20120328' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-asm_system: (38 commits)
Delete all instances of asm/system.h
Remove all #inclusions of asm/system.h
Add #includes needed to permit the removal of asm/system.h
Move all declarations of free_initmem() to linux/mm.h
Disintegrate asm/system.h for OpenRISC
Split arch_align_stack() out from asm-generic/system.h
Split the switch_to() wrapper out of asm-generic/system.h
Move the asm-generic/system.h xchg() implementation to asm-generic/cmpxchg.h
Create asm-generic/barrier.h
Make asm-generic/cmpxchg.h #include asm-generic/cmpxchg-local.h
Disintegrate asm/system.h for Xtensa
Disintegrate asm/system.h for Unicore32 [based on ver #3, changed by gxt]
Disintegrate asm/system.h for Tile
Disintegrate asm/system.h for Sparc
Disintegrate asm/system.h for SH
Disintegrate asm/system.h for Score
Disintegrate asm/system.h for S390
Disintegrate asm/system.h for PowerPC
Disintegrate asm/system.h for PA-RISC
Disintegrate asm/system.h for MN10300
...
