The genirq layer expects a 0 in case of failure. The current code is
returning -ENXIO for an error.
Fix it.
Change-Id: I0985f12477d472f4fbef525f7b04fed9bf593686
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Ajay Dudani <adudani@codeaurora.org>
Remove modem_wake and from_idle parameters from msm_gic_save
API since they are not used at all.
Change-Id: Icd1a83aea6b0eb988c19ccdbaf65b1f5be9e8ac2
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
MSM8625 v1.0 needs the s/w workaround for hready pin access problem
in QGIC2. The workaround is add the lock around every QGIC2 register's
read and write operation to avoid reading the incorrect value from the
QGIC2 registers when back to back read happens on another CPU.
Change-Id: If980c03d2c57b0b9c560b5a746db0535584841d9
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
msm_gic_save/restore APIs were added to save the context of the
GIC across the apps. power collapse since 8625 PM framework
doesn't use the CPUIdle framework of the kernel. If the CPUIdle
framework was in use then we could have used the GIC driver provided
notification mechanism which takes of calling appropriate functions.
There is no need to protect these APIs using this #ifdef since there
is nothing specific to 8625 inside, also add empty functions for save
and restore since not all targets have CPU_PM defined.
Change-Id: I02bb4e4021c31caf7ab1282fb675d45ffba42a66
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
The following merge commit chose the irq_domain implementation
from AU_LINUX_ANDROID_ICS.04.00.04.00.126 instead of the version
in v3.4.
commit f132c6cf77251e011e1dad0ec88c0b1fda16d5aa
Merge: 23016de 3f6240f
Author: Steve Muckle <smuckle@codeaurora.org>
Date: Wed Jun 6 18:30:57 2012 -0700
Merge commit 'AU_LINUX_ANDROID_ICS.04.00.04.00.126' into
msm-3.4
Since this version is inconsistent with the upstream,
port the irq_domain framework to the version in v3.4 and
makes all necessary changes to clients that are out of spec.
Details of client ports are below.
-Update the qpnp-int driver for revmap irq_domain API. The revmap
irq_domain implementation introduces a reverse lookup scheme using
a radix tree. This scheme is useful for controllers like qpnp-int
that require a large range of hwirqs.
-Bring the ARM GIC driver up to v3.4, being careful
to port existing CAF changes.
-Partially port the gpio-msm-common driver to the new irq_domain API.
Enable the gpio-msm-common driver to work with the new irq_domain
API using a linear revmap. It is not a full port since irq_domain
is still only registered for Device Tree configurations. It should
be registered even for legacy configurations.
In addition, the irq_domains .map function should be setting all
the fields currently done in msm_gpio_probe(). That's not
currently possible since msm_gpio_probe is invoked
unconditionally - even from Device Tree configurations.
Finally, gpio-msm-common should be converted into a real
platform_device so that probe() is invoked due to driver and
device matching.
Change-Id: I19fa50171bd244759fb6076e3cddc70896d8727b
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Rename gic_is_spi_pending and gic_clear_spi_pending APIs
to generic gic_is_irq_pending and gic_clear_irq_pending names
since this API could be used for anyother interrupts, and while
at it also use proper style for the multi-line comments around
these APIs.
Change-Id: I7d440f3caa0ebc77483d1ba43eff7932d5ac6666
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Remove the unnecessary irq spinlocks from gic resume path since it
always gets called with interrupt disabled. It also fixes the bug
introduced by commit 6278db09f where it called spin_lock again on the same
lock.
CRs-Fixed: 370894
Change-Id: I94f81cc0d93f362ac233c9af637cbe75036903f9
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
This API now returns an error. Since gic_init_bases() is called
early on, there's probably not a whole lot we can do here except
send a warning.
Change-Id: I2835dacfa191db0ce70434de23e6ee540fe33b57
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Conflicts:
arch/arm/common/gic.c
Recently a change was added to break apart irq_domain_add() into
two functions. The first creates the domain, and the second
registers it.
This change abides to this new interface and registers the
GIC irq_domain after creating it.
Change-Id: I34c6a1f56dc27113a9b72f0fefa577276f91bbc8
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Conflicts:
arch/arm/common/gic.c
We may enter PC from either suspend or idle path. So even
if we enter from suspend path we should disable all interrupts
before we go to Power collapse, so as to make sure, there
are no pending interrupts(not even the wakeup capable) which
could result in WFI failure.
CRs-Fixed: 363293
Change-Id: Ied25b21f59a9fa0a891a27a2e806876cc337a759
Signed-off-by: Taniya Das <tdas@codeaurora.org>
(cherry picked from commit 8862d7d2202f33a6fe2f219aca0b2d7bb62b570e)
msm_gic_spi_ppi_pending, msm_gic_save and core1_gic_configure_and_raise
gets called with interrupt enabled on the core0, so it is possible
that we get into the spinlock deadlock since interrupt like timer PPI
could get fired on core0 and get locked in gic_handle_irq() routine
itself, so move these spinlocks to irqsave variants to avoid this
scenario.
CRs-Fixed: 363249
Change-Id: I2d40d6e26f5d9dba4ee6b9d4602cd0e685226693
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
(cherry picked from commit 6278db09f0535ca05d6bc12bfbb4ef4aa9da0652)
Conflicts:
arch/arm/common/gic.c
Moving code which modifies the GIC registers. As there is no global
lock in gic code, moving the code out.
Change-Id: I85a2bd580dbeefc942a3307f3c0cad8b1da509b7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
(cherry picked from commit bc9248ab6fd94f9f5f2a818e7d8b67645b4310cb)
Conflicts:
arch/arm/common/gic.c
arch/arm/mach-msm/mpm-8625.c
arch/arm/mach-msm/platsmp-8625.c
On 8625 due to bug in AHB MUX on hready, back to back write followed
by read (from any CPU) on QGIC2 registers (SGIR(WO) ,IAR(RO) and
write on EOI(WO)) cause the read data to get corrupted on AHB bus.
Due to this whenever a valid irq has occurs, and dispatched to the cpu
interface but still cpu reads the IAR as 0x0 and that particular IRQ
becomes active.
But due to incorrect irq id (read as 0x0), IRQ handler will not do
proper EOI for that particular interrupt and thus it gets trapped
in the active state.
Below is the qgic register dump from CPU-1, in this particular case
we see that SGI-3 is not getting clear as cpu reads this as 0x0.
AZSD:C0000200| 00240008 00000000 00008000 00000000 00000000 00000000
00000000 00000000 ..$.............................
AZSD:C0000280| 00240008 00000000 00008000 00000000 00000000 00000000
00000000 00000000 ..$.............................
AZSD:C0000300| 00040008 00000000 00000000 00000000 00000000 00000000
00000000 00000000 ................................
AZSD:C0000380| 00040008 00000000 00000000 00000000 00000000 00000000
00000000 00000000 ................................
As the interrupt gets trapped, no other interrupt received on the core is
services any more causing the system hang.
CRs-Fixed: 349219
Change-Id: Icad2c65114377a08984b1032566cfba811bb4ca8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
(cherry picked from commit 6639886be3b2326bcce81a3d553bc91b6de793ac)
Currently gic secure mode is enabled for all the v7 cpus.
For 8x25 we do not want to access GIC in secure mode as
we are observe issues of not able to clear the pending clear
registers when we come out of power collapse.
The Kconfig should make it flexible for targets who want to
support GIC in secure/non-secure modes.
Change-Id: Id7c85f5b741346233993966752607e5c4fb23e74
Signed-off-by: Taniya Das <tdas@codeaurora.org>
(cherry picked from commit b241bd843145b76dcd87697a53d8f8cf1952b9d1)
Conflicts:
arch/arm/mach-msm/Kconfig
Configure the GIC to run in secure mode and handle
secure as well as non-secure interrupts. This patch
adds an API to configure an IRQ as a secure IRQ so that
it can be treated as an FIQ in the secure mode.
Change-Id: Ic3321e76c95a4c10d6287ba418e84623e7004cb1
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit 26e44869e1e730ec7434e899dfd5857530b63415)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/gic.h
This change is to satisfy the logging requirement of
wakeup interrupts. Add code to log the trigger status
of wakeup interrupts. This helps in debugging
the cause of wakeup when the system is suspended
Change-Id: I0f724296f9133433cdbc3271a9b91c6fa992a2ff
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
(cherry picked from commit c0dde6391c0d4971f5669e970a95b2e6885e36eb)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/gic.h
While in suspend state, the system should not wake up due to triggering
of a non wakeup interrupt. Implement suspend and resume functions to be
called from power management code to switch enabled interrupts between
wakeup set or normal set.
Change-Id: Iaceae286707460eadc5f05c0baef72b43c942777
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
(cherry picked from commit 3f2f06c6205445266aabdb9c843da70a4dd5d22f)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/gic.h
Some kernel code needs to check for and clear specific pending
interrupt explicitly. The polling and clearing may happen in
contexts where interrupts are masked off at the cpu level.
Change-Id: Icba9bb2f05e9fc61dd48c4174c4d276ab20b4244
Signed-off-by: Ai Li <aili@codeaurora.org>
(cherry picked from commit 20b3c0ee6e4852af8c52fb5f98188530760c8c74)
Conflicts:
arch/arm/include/asm/hardware/gic.h
The commit 292b293 creates the MSM boot failures, so squash
the commit 28af690 with it to avoid such failures. The commit ddd847
and 0c1991 are required to keep the watchdog and Copper targets working.
commit 292b293cee
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Wed Jul 20 16:24:14 2011 +0100
ARM: gic: consolidate PPI handling
PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).
Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.
This also allows the removal of some duplicated code.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit 28af690a28
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Fri Jul 22 12:52:37 2011 +0100
ARM: gic, local timers: use the request_percpu_irq() interface
This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).
PPIs are now useable for more than just the local timers.
Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).
Cc: David Brown <davidb@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit ddd8478d68f8cf75ee9771667c0cbe2a9d1caeb9
Author: Trilok Soni <tsoni@codeaurora.org>
Date: Tue Dec 6 00:56:01 2011 +0530
msm: watchdog: Use request_percpu_irq() interface
Change-Id: I7c319344f6a7f7a7c70682ac87f5c385e56d130c
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
commit 0c19915e092214a4c17a9920c4c1f3d78610217d
Author: Sathish Ambley <sambley@codeaurora.org>
Date: Fri Dec 9 17:07:37 2011 +0530
arm: arch_timer: Use request_percpu_irq() API
Change-Id: Iee9b218d538f315cd884a47d95bcc0dcc49b0fe1
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
Change-Id: I7bbba706b1f2e55814be5891ed76063725c2bfb1
Signed-off-by: Ravi Kumar <kumarrav@codeaurora.org>
[tsoni@codeaurora.org: MSM specific fixes]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
(cherry picked from commit eecb28c59054b1b9d8b9f410a903f87c8eb1ac48)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/entry-macro-gic.S
arch/arm/include/asm/localtimer.h
arch/arm/include/asm/smp.h
arch/arm/include/asm/smp_twd.h
arch/arm/kernel/smp.c
arch/arm/kernel/smp_twd.c
arch/arm/mach-exynos4/include/mach/entry-macro.S
arch/arm/mach-exynos4/mct.c
arch/arm/mach-msm/board-8064.c
arch/arm/mach-msm/board-8960.c
arch/arm/mach-msm/board-copper.c
arch/arm/mach-msm/board-dt.c
arch/arm/mach-msm/devices-9615.c
arch/arm/mach-msm/devices-msm8x60.c
arch/arm/mach-msm/include/mach/entry-macro-qgic.S
arch/arm/mach-msm/msm_watchdog.c
arch/arm/mach-msm/timer.c
arch/arm/mach-omap2/include/mach/entry-macro.S
Pull more ARM updates from Russell King.
This got a fair number of conflicts with the <asm/system.h> split, but
also with some other sparse-irq and header file include cleanups. They
all looked pretty trivial, though.
* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (59 commits)
ARM: fix Kconfig warning for HAVE_BPF_JIT
ARM: 7361/1: provide XIP_VIRT_ADDR for no-MMU builds
ARM: 7349/1: integrator: convert to sparse irqs
ARM: 7259/3: net: JIT compiler for packet filters
ARM: 7334/1: add jump label support
ARM: 7333/2: jump label: detect %c support for ARM
ARM: 7338/1: add support for early console output via semihosting
ARM: use set_current_blocked() and block_sigmask()
ARM: exec: remove redundant set_fs(USER_DS)
ARM: 7332/1: extract out code patch function from kprobes
ARM: 7331/1: extract out insn generation code from ftrace
ARM: 7330/1: ftrace: use canonical Thumb-2 wide instruction format
ARM: 7351/1: ftrace: remove useless memory checks
ARM: 7316/1: kexec: EOI active and mask all interrupts in kexec crash path
ARM: Versatile Express: add NO_IOPORT
ARM: get rid of asm/irq.h in asm/prom.h
ARM: 7319/1: Print debug info for SIGBUS in user faults
ARM: 7318/1: gic: refactor irq_start assignment
ARM: 7317/1: irq: avoid NULL check in for_each_irq_desc loop
ARM: 7315/1: perf: add support for the Cortex-A7 PMU
...
The irq_start and hwirq_base assignment code is fairly hairy and ended
up being difficult to read following a conflict resolution for 3.2.
This patch rearranges the code slightly to make it easier to read.
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch removes the simplistic implementation of irq_domains and enables
the powerpc infrastructure for all irq_domain users. The powerpc
infrastructure includes support for complex mappings between Linux and
hardware irq numbers, and can manage allocation of irq_descs.
This patch also converts the few users of irq_domain_add()/irq_domain_del()
to call irq_domain_add_legacy() instead.
v3: Fix bug that set up too many irqs in translation range.
v2: Fix removal of irq_alloc_descs() call in gic driver
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Milton Miller <miltonm@bga.com>
Tested-by: Olof Johansson <olof@lixom.net>
Part of the series to unify the irq remapping mechanisms in the
kernel. A follow up patch will copy the powerpc implementation into
kernel/irq/irqdomain.c, which will be a lot easier if the structures
are identical.
Where they differ, I've chose to use the powerpc names since there is
a lot more code using those names.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Milton Miller <miltonm@bga.com>
Tested-by: Olof Johansson <olof@lixom.net>
It turns out that the logical CPU mapping is useful even when !CONFIG_SMP
for manipulation of devices like interrupt and power controllers when
running a UP kernel on a CPU other than 0. This can happen when kexecing
a UP image from an SMP kernel.
In the future, multi-cluster systems running AMP configurations will
require something similar for mapping cluster IDs, so it makes sense to
decouple this logic in preparation for this support.
Acked-by: Yang Bai <hamo.by@gmail.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reported-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Commit 4294f8baa ("ARM: gic: add irq_domain support") defines irq_start
as irq_start = (irq_start & ~31) + 16; On a platform with a GIC and a
CPU without PPIs, this results in irq_start being off by 16.
This patch fixes gic_init so that we only carve out a PPI space when
PPIs exist for the GIC being initialised.
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When multiple GICs exist on a platform (RealView PB1176/11MP),
we must make sure the PM notifier block is only registered
once, otherwise we end up corrupting the PM notifier list.
The fix is to only register the notifier when initializing
the first GIC, as the power management functions seem
to iterate over all the registered GICs.
Tested on PB11MP and PB1176.
Reported-by: Will Deacon <will.deacon@arm.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Cc: Colin Cross <ccross@android.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now that MULTI_IRQ_HANDLER is selected by all the in-tree
GIC users, make it mandatory and remove the unused macros.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Provide the GIC code with a low level handler that can be used
by platforms using CONFIG_MULTI_IRQ_HANDLER.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The GIC support code is heavily using the fact that hardware
implementations are exposing banked registers. Unfortunately, it
looks like at least one GIC implementation (EXYNOS) offers both
the distributor and the CPU interfaces at different addresses,
depending on the CPU.
This problem is solved by allowing the distributor and CPU interface
addresses to be per-cpu variables for the platforms that require it.
The EXYNOS code is updated not to mess with the GIC internals while
handling interrupts, and struct gic_chip_data is back to being private.
The DT binding for the gic is updated to allow an optional "cpu-offset"
value, which is used to compute the various base addresses.
Finally, a new config option (GIC_NON_BANKED) is used to control this
feature, so the overhead is only present on kernels compiled with
support for EXYNOS.
Tested on Origen (EXYNOS4) and Panda (OMAP4).
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* 'next/dt' of git://git.linaro.org/people/arnd/arm-soc:
ARM: gic: use module.h instead of export.h
ARM: gic: fix irq_alloc_descs handling for sparse irq
ARM: gic: add OF based initialization
ARM: gic: add irq_domain support
irq: support domains with non-zero hwirq base
of/irq: introduce of_irq_init
ARM: at91: add at91sam9g20 and Calao USB A9G20 DT support
ARM: at91: dt: at91sam9g45 family and board device tree files
arm/mx5: add device tree support for imx51 babbage
arm/mx5: add device tree support for imx53 boards
ARM: msm: Add devicetree support for msm8660-surf
msm_serial: Add devicetree support
msm_serial: Use relative resources for iomem
Fix up conflicts in arch/arm/mach-at91/{at91sam9260.c,at91sam9g45.c}
The module.h cleanup series is not merged at this point, so use the
older header file for now, to make it build either way.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Commit "ARM: gic: add irq_domain support" (b49b6ff) breaks SPARSE_IRQ
on platforms with GIC. When SPARSE_IRQ is enabled, all NR_IRQS or
mach_desc->nr_irqs will be allocated by arch_probe_nr_irqs(). This caused
irq_alloc_descs to allocate irq_descs after the pre-allocated space.
Make irq_alloc_descs search for an exact irq range and assume it has
been pre-allocated on failure. For DT probing dynamic allocation is used.
DT enabled platforms should set their nr_irqs to NR_IRQ_LEGACY and have all
irq_chips allocate their irq_descs with irq_alloc_descs if SPARSE_IRQ is
enabled.
gic_init irq_start param is changed to be signed with negative meaning do
dynamic Linux irq assigment.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
This adds ARM gic interrupt controller initialization using device tree
data.
The initialization function is intended to be called by of_irq_init
function like this:
const static struct of_device_id irq_match[] = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
{}
};
static void __init init_irqs(void)
{
of_irq_init(irq_match);
}
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Convert the gic interrupt controller to use irq domains in preparation
for device-tree binding and MULTI_IRQ. This allows for translation between
GIC interrupt IDs and Linux irq numbers.
The meaning of irq_offset has changed. It now is just the number of skipped
GIC interrupt IDs for the controller. It will be 16 for primary GIC and 32
for secondary GICs.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
* 'core-locking-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (27 commits)
rtmutex: Add missing rcu_read_unlock() in debug_rt_mutex_print_deadlock()
lockdep: Comment all warnings
lib: atomic64: Change the type of local lock to raw_spinlock_t
locking, lib/atomic64: Annotate atomic64_lock::lock as raw
locking, x86, iommu: Annotate qi->q_lock as raw
locking, x86, iommu: Annotate irq_2_ir_lock as raw
locking, x86, iommu: Annotate iommu->register_lock as raw
locking, dma, ipu: Annotate bank_lock as raw
locking, ARM: Annotate low level hw locks as raw
locking, drivers/dca: Annotate dca_lock as raw
locking, powerpc: Annotate uic->lock as raw
locking, x86: mce: Annotate cmci_discover_lock as raw
locking, ACPI: Annotate c3_lock as raw
locking, oprofile: Annotate oprofilefs lock as raw
locking, video: Annotate vga console lock as raw
locking, latencytop: Annotate latency_lock as raw
locking, timer_stats: Annotate table_lock as raw
locking, rwsem: Annotate inner lock as raw
locking, semaphores: Annotate inner lock as raw
locking, sched: Annotate thread_group_cputimer as raw
...
Fix up conflicts in kernel/posix-cpu-timers.c manually: making
cputimer->cputime a raw lock conflicted with the ABBA fix in commit
bcd5cff721 ("cputimer: Cure lock inversion").
This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).
PPIs are now useable for more than just the local timers.
Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).
Cc: David Brown <davidb@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The GIC driver must convert logical CPU numbers passed in from Linux
into physical CPU numbers that are understood by the hardware.
This patch uses the new cpu_logical_map macro for performing the
conversion inside the GIC driver.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When the cpu is powered down in a low power mode, the gic cpu
interface may be reset, and when the cpu cluster is powered
down, the gic distributor may also be reset.
This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save
and restore the gic cpu interface registers, and the
CPU_CLUSTER_PM_ENTER and CPU_CLUSTER_PM_EXIT notifiers to save
and restore the gic distributor registers.
Original-author: Gary King <gking@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
Annotate the low level hardware locks which must not be preempted.
In mainline this change documents the low level nature of
the lock - otherwise there's no functional difference. Lockdep
and Sparse checking will work as usual.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
