The A330 GPU defines a few new registers that don't exist on
A305/A320. Define a new subset for A330 and dump it in the
postmortem and binary snapshot.
Change-Id: Ic0dedbadd0c44ee8872b99fd6b0b3dc8eb972eea
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Expand the snapshot register dump helper function to support multiple
sets of registers. This will be useful for derivative GPUS that
use a global subset of registers and add a few new ones. This will
not be useful for chipsets that have extensive changes to existing
registers.
Change-Id: Ic0dedbad05bcc3b5a3a0cc933659959965ff5817
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
The CP MERCIU queue can be read from the A330 GPU. Dump it into
the snapshot binary.
Change-Id: Ic0dedbadf2c61ccec6a11af103374f4aee8be727
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
The A330 has a larger ROQ buffer then the A305/A320 variants so
adjust the size at runtime based on the core type.
Change-Id: Ic0dedbade62c988cfe402876bc94d91a2dd71617
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Create adreno_is_a330() to identify the GPU for A330 specific
register settings and core specific code.
Change-Id: Ic0dedbade244ffba3ba3917661a88f97108e6182
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Increase number of clocks that RBBM will wait before de-asserting
the Register Clock Active signal. This fixes kernel panics during
stability tests on multiple devices
Change-Id: I6f7f8bb17cfd9c5beed0fd21d56ab6ab9fd40195
Signed-off-by: Rammohan Basavaraju <rammoh@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
For A3xx, initialize UCHE_CACHE_MODE_CONTROL_REG to
0x00000001 so that UCHE will always use 64-byte
cachelines when we boot up or reset. This value
increases performance and was previously set in the
graphics preambles, but should instead be set at
boot/reset time.
Change-Id: Iec71ffc04262ac43534fd632d8b092a48d280509
Signed-off-by: Kevin Matlage <kmatlage@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
GPU register RB_GMEM_BASE_ADDR needs to be initialized with GMEM base
address. From A330, OCMEM is utilized to be GMEM dynamically; when
OCMEM is allocated for GFX, the allocated region address may vary
every time, GPU register RB_GMEM_BASE_ADDR need to be initialized
with the allocated OCMEM region address.
Change-Id: I5cb4472a9f18759d2af160a15d83f1404378a530
Signed-off-by: liu zhong <zhongl@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
No need to save a context if it is being destroyed since
it will no longer be used at all. This is better for
performance and also avoids the use of legacy kgsl
context save code for contexts that use preambles
Change-Id: I19a64e82188b4132f353bb61c21e4ed2281092fc
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Define the register offsets for IOMMU-v2 and switch off using per
process pagetables for IOMMU-v2.
Change-Id: I8b76de557c8e52b5a2a333ceb987bd743b213eb7
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Changed values written to VBIF registers for A330.
The maximum pending request from clients is increased to 24.
Disable VBIF clock gating. This potentially increases stand-by power.
Change-Id: Ic9a4f15546f4122298e140e79e4572c82e6385fc
Signed-off-by: Lokesh Batra <lbatra@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Define the IOMMU register offsets in a structure array. This
offers flexibility in defining IOMMU v2 offsets in another array
and the right array to be used can be setup during MMU
initialization.
Also, restrict the usage of IOMMU offsets only in the iommu file
by redifining the functions that return iommu information. Remove
the function to get iommu mapped register address and replace
it with a function that returns the gpuaddress of given iommu
register. Only return the valid address bits of an iommu pagetable
instead of just returning the pagetable base register value.
Change-Id: Ib88e605f57e551c7b84029647451cb20f06025a0
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Calling clk_set_rate() for both AXI & 2D core clocks without putting
them in async mode causes 2D core hang. Since AXI & 2D core clocks
are in sync mode, ensure that clk_set_rate() is called only for AXI
& 2D core clock is enabled only after it is prepared.
Change-Id: I4634e2342d62ce16ad7afc748b10b0573fbfd913
CRs-fixed: 385393
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Turn io_fraction to 100 so that the kernel
wait_io_interruptible call is not required for io_busy
reporting while using msm policy. Msm policy uses its
own schema to capture busy events.
Change-Id: Iddb63552305974ce4a12446117f27d07b7201387
Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Turn on an additional clock for IOMMU if it is valid. This additional
clock is present on devices which have the IOMMU unit access tied to
the core clock of another component. This has been introduced from
IOMMU-v2 onwards.
Change-Id: I8b0a0f23cb789d820a8d515cae54b44f556e634d
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Set the upper limit for the gpu address that the MMU can access to
be the base address where the first IOMMU units register space
is mapped. Earlier we set it to the last address mapped minus
a PAGE_SIZE, but we can actually set it to the base address of the
first mapped unit since the GPU should never access that space
unless we are updating IOMMU registers.
Change-Id: I6507ee373a9218210c148685e443e948a311bd29
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Limit the size of individual GPU memory allocations to the amount of
free memory on the system minus 32MB. This early check gives us the
chance to verify that the user didn't ask for an obscene amount of
memory, and also to limit the chance that an allocation attempt will
invoke the OOM killer.
The 32MB buffer in particular should keep us out of the clutches of
the OOM killer. That number is the same amount of buffer used in
the page allocation alogrithms and it should keep the GPU from further
throwing fuel on the fire of a low memory situation.
Change-Id: Ic0dedbadcc5ee9cc0d77056b1a22eed5c385d636
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Instead of calling BUG_ON if the user passes a zero length via
IOCTL_KGSL_GPUMEM_ALLOC to kgsl_sharedmem_alloc_user, return
-EINVAL instead and propegate the error back up to the user.
CRs-fixed: 389886
Change-Id: Ic0dedbad2dc1f68ad1d3227498893c73c2a1c59e
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
If a platform has Trustzone support, enable GPU DCVS
automatically without checking the individual soc info
value.
Change-Id: Ie8d965f8d73283a7f3bf55dedc44d550db2408b8
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Add a new sysfs node to communicate available GPU clock frequencies
to userspace for the power daemons.
Change-Id: I2479217aa797e2066cc50476ef7f73c5cae8aebe
Signed-off-by: Anshuman Dani <adani@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Limit the number of pending requests from clients to just 1 for
better stability. More agressive values can be set later if things
are found to be stable.
Switch off gating next write request for certain clients, this
setting seems to be stable and should be better for performance
Set the register values for interleaving requests for A330 VBIF.
Do not set VBIF_OUT_AXI_AMEMTYPE_CONF0 since it was
only being set to POR value.
Change-Id: I2152a30b49545fdbf0c147106a088b71ed562e3f
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Harsh Vardhan Dwivedi <hdwivedi@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
ion_import_dma_buf() can return a NULL without an error code. Detect
this condition & return a -EINVAL as error.
Change-Id: I18d058fd374a8d00c00bb943f496f446c9f1c90d
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Ensure that pagetable is updated during context destruction. This
resolves stability issues during Camera launch/exit scenarios. Applies
only to A20x GPUs. This change is already done for Z180 device.
Change-Id: I978cbce49ed2b45be0209c2939b1b8423c68d5ec
CRs-fixed: 381875
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
it seems even if gpu requests for power rail off, modem might not
process this request as it leads to turn off power rail for mdp in
the case of 7x27a/8x25. This issue specific to 7x27a, since we do
soft reset the GPU on sleep/wake. In the case of suspend/resume,
the powerail is effectively off across the device.
Change-Id: Iad898da67b34e265b2447013c4250ba04a59c0cd
Signed-off-by: Rammohan Basavaraju <rammoh@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
There are two versions of 8960. Set the 8960PRO chip id correctly.
Ensure 8960 clock values do not get changed when the device is 8960PRO.
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
Change-Id: I1d2226c389881f3cadb9067dc1393db168cef309
Conflicts:
arch/arm/mach-msm/board-8960.c
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Currently core_name is used to identify which core the dcvs operates on.
Instead use a type and the type num while registration with dcvs and
return an id (dcvs_core_id) upon successfull registration.
The dcvs_core_id is used by the clients of msm_dcvs to call upon its
apis viz. freq_start, freq_stop, msm_dcvs_idle etc.
The dcvs inturn uses the type num passed in at registration time to
invoke apis on the clients viz. set_freq, get_freq, idle_enable.
This further cleans up the internal dcvs add_core and get_core
implementation. One need not pass around the core_name and use the type
instead.
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
(cherry picked from commit 1bbc0321a6871e018c17da6f244b9df442faead6)
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>
(cherry picked from commit 09456d7d7618e6d0fc6b907b7af75268ea08a942)
Change-Id: Id27751a8ec8f5d3d386bbe7c7625ed56757b8bd7
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
Register the idle enable callback along with the core. The code
becomes cleaner and easy to update.
Importantly, the msm_dcvs_idle driver becomes useless. Remove it
and instead let the msm governor handle idle enabling and disabling.
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
(cherry picked from commit c1ed66c9035b4fbf240e46837d86a9a6442531f1)
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>
(cherry picked from commit b4f5c2274fa2180b53563f2db0922eef212c0fcd)
Change-Id: Ice039e608d45bdeb9b8b718e5fbbf82a698d584d
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
There is no need to register a separate structure for setting and
getting frequency.
Simply pass function pointers to set and get callbacks when a
core is registered.
While at it rename the msm_dcvs_freq_sink_register/unregister to
msm_dcvs_freq_sink_start/stop to better reflect that those
apis are meant to do.
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
(cherry picked from commit 69134111c2a24002d1995a05c99f84403ac6a7e8)
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>
(cherry picked from commit 52cb57c3c6bc1c0d08c1ae9eb5dd0ff1e1125a96)
Change-Id: Iee7aee1cbb2f33ed2852f1816ab62416b96fa7e6
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
The algorithm needs thermal inputs for all the cores. Create members in
the internal core_info strucutre and platform data/device tree to pass
in the sensors they use.
Update the dcvs code to notify the temperature to TZ.
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
(cherry picked from commit fc7dca4c325725492af997fa282e07b9d03154d1)
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>
(cherry picked from commit eb478c5b7b55ea8a57e0336e4cf9979be935b289)
Change-Id: I505903eb8b9779f2065aebfab5b3f2aefc874200
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
This change
-removes the use of group id and instead introduces core type
-rearranges platform data, adds energy curve coefficients and power
parameters
-allow for the energy params to be -ve numbers
The change also mandates updates to the msm8974-gpu.dtsi and the
associated binding documentation.
Also take this opportunity to remove devices for unsupported platform
- 8930 and 8960
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
(cherry picked from commit 4445166ad16be0c45b077bfb10487de355ed2e05)
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>
(cherry picked from commit 24d2351f6a5e7069e5d554dbc999280a69288c5d)
Change-Id: I5c65c0e65cc7652eee72c525f0db10e128061cf9
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
Verify that the user specified length for a PMEM region is smaller than the
size of the entire region as reported by the kernel APIs.
Change-Id: Ic0dedbad0127bdaed70eafc00238b44f982b093b
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Iliyan Malchev <malchev@google.com>
The GPU needs access to the L2 cache while running. If the
CPU is not also active using the cache can lead to stability
issues. Keep the CPU out of idle power collapse at all times
while the GPU is running.
CRs-Fixed: 397489
Change-Id: Iab2d8c601e903aadc4060f7c6d67bc128840edbf
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
If preemted during ion_free after the refcount is updated but
before the handle can be removed from the rb_tree, import
might find that handle in the tree and try to reuse it
when execution returns to free, the handle will be cleaned
up leaving the caller of import with a corrupt handle.
This patch modifies the locking to protect agains this race.
Change-Id: I31d18cc6398f0ca18e05cd919e2bcf86fa18d568
CRs-Fixed: 385283
Signed-off-by: Rebecca Schultz Zavin <rebecca@android.com>
[lauraa@codeaurora.org: Whitespace change and move unlock]
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Ajay Dudani <adudani@codeaurora.org>
The dup and has_signaled functions are not called outside kgsl_sync.c
Change-Id: I69d746f4e4acae9b4f5a3a2cac79ac812e5eff5c
Signed-off-by: Jeff Boody <jboody@codeaurora.org>
The compare callback is required to test the order that
sync pts will signal. Failing to implement the compare
callback results in kernel panics for some use cases.
Change-Id: Ibea1497c12fd8cc66087ff52d3709a07793f215f
Signed-off-by: Jeff Boody <jboody@codeaurora.org>
The Android sync point framework will replace the synchronization
previously implemented by genlock. This change implements the KGSL
component of the sync point framework by creating a fence that is
automatically signaled by KGSL when it's timestamp expires. The
fence FD is returned to the user driver so that another process
can wait for the sync point.
Change-Id: Ifee38dfde00e551f3524f7a37833938dcdb64905
Signed-off-by: Jeff Boody <jboody@codeaurora.org>
There is no point using vmalloc for small temporary allocations. kmalloc will
allocate more quickly and will not fragment the vmalloc space.
Signed-off-by: Iliyan Malchev <malchev@google.com>
Implement the function to map ebi memory to the kernel.
This function is used when from postmortem or snapshot
when there is a hang and we are allocating memory from
kernel ebi space
Change-Id: I4f3e8b3fcb8c0107599ce3d3636c0ed33ace725a
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
The GPU clock statistics show the amount of time the
GPU was busy in the last one second and the time spent
at each individual clock level while it was busy.
Change-Id: I16f8973ca0c683d55406a1f37c1395cdfe43ef5a
Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
Fix the address range checked with no MMU by always
returning true for no MMU as there is no particular
address range when MMU is not used
Change-Id: I522681d13b2281d482bad91dd00d34ec0f440a1f
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Alex Wong <waiw@codeaurora.org>
With the improved hang detection we don't technically need a upper
timeout bound for a process to wait in waitfortimestamp(). Allow
for a idle_timestamp of '0' to allow the loop to wait for ever.
The infrastructure for changing the idle_timeout still exists
so it can be changed to whatever value is appropriate for debugging
or testing.
CRs-fixed: 382366
CRs-fixed: 383999
Change-Id: Ic0dedbadf2c100eb56ed2338914575061776e725
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
There are two distinct parts of the code that may need to loop waiting
for the GPU to complete a task: waiting for a timestamp and waiting
for the entire core to go idle. Waiting for a timestamp technically
doesn't need a timeout since the only downside is a process that sleeps
forever with an interruptible timeout. Waiting for the core to go idle
is more problematic because it is a busy wait and it is the last point
we can safely detect a GPU hang.
Beacuse we can (and will) not use a timeout in wait for timestamp, we
need to institute a new timeout value to be used in idle. Nowhere the
idle function is called uses a custom value for the timeout, so remove
that parameter from the calls and use a static timeout value in the
core specific functions.
Change-Id: Ic0dedbad9ecd2044c34e4cec551dc7f53b253f3d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Differentiate between the screen off case where kgsl shouldn't
hold a pm_qos vote and the screen on case where power rails
may be turned off after a long idle. restore_slumber now
corresponds to the screen on/off while strtstp_sleepwake covers
the power rail collapse.
CRs-Fixed: 386956
Change-Id: Id4318f1aa87d6ad0653fe5db18c5d33bda1cc8bb
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
Because we were using _IO_NR, one could construct a malformed ioctl
code that would avoid allocating memory yet go to a function that
expected that memory. Still use _IO_NR to index the array of ioctls,
but check that the full values match before jumping to the helper
function.
CRs-fixed: 385592
Change-Id: Ic0dedbaded469035bd0a2bb0f20fecb2a3045ca5
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add ringbuffer and register dump as part of postmortem dump for z180
cores. Also, add kgsl_postmortem_dump as a preparatory general function
for postmortem dump for both types of kgsl devices, adreno and z180.
Change-Id: I8b538771bfa8f6bfdfe0b1b993afa3c53f8eb8cf
Signed-off-by: Harsh Vardhan Dwivedi <hdwivedi@codeaurora.org>
GPU MMU is used to control access to IOMMU registers on msm8960.
When pagefaults occurs, accessing mmu_pagefault which is NULL
causes kernel panic. Disable gpummu pagefault interrupts, since
pagefaults are handled through iommu fault handler.
CRs-Fixed: 380470
Change-Id: I9717f4af10b9722b0a14ba5995ee2293ae1de09f
Signed-off-by: Anoop Kumar Yerukala <ayeruk@codeaurora.org>
OCMEM is a on-chip memory bank which is shared by all Multimedia
components. KGSL needs to request space for GMEM usage for platforms
that support OCMEM.
Change-Id: Ic3ff501d7a444a71f75244806af95c62c8a08ed8
Signed-off-by: liu zhong <zhongl@codeaurora.org>
Add GPU ID and VBIF configuration for the A330 GPU
Change-Id: I02f1d6aab60233d0205f930e1813f14a685dd89c
Signed-off-by: liu zhong <zhongl@codeaurora.org>
Change GPU digital circuit head switch name to vddcx to match
devicetree property name convention.
Change-Id: If17b47125f08873106f74fdb21a29c58dbf1496a
Signed-off-by: Pu Chen <puchen@codeaurora.org>
Populate the platform_data structure by reading from the Device Tree
Source file.
Change-Id: Ic8c83d3918510448b76559b095ad414d2f22c7bd
Signed-off-by: Lokesh Batra <lbatra@codeaurora.org>
