Files
ubports_kernel_google_msm/arch/x86/kernel
Peter Zijlstra ab608344bc perf, x86: Improve the PEBS ABI
Rename perf_event_attr::precise to perf_event_attr::precise_ip and
widen it to 2 bits. This new field describes the required precision of
the PERF_SAMPLE_IP field:

  0 - SAMPLE_IP can have arbitrary skid
  1 - SAMPLE_IP must have constant skid
  2 - SAMPLE_IP requested to have 0 skid
  3 - SAMPLE_IP must have 0 skid

And modify the Intel PEBS code accordingly. The PEBS implementation
now supports up to precise_ip == 2, where we perform the IP fixup.

Also s/PERF_RECORD_MISC_EXACT/&_IP/ to clarify its meaning, this bit
should be set for each PERF_SAMPLE_IP field known to match the actual
instruction triggering the event.

This new scheme allows for a PEBS mode that uses the buffer for more
than a single event.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Stephane Eranian <eranian@google.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-07 11:31:02 +02:00
..
2010-05-07 11:31:02 +02:00
2009-07-19 18:27:51 +02:00
2010-02-07 17:47:51 +01:00
2010-01-05 09:17:33 +09:00
2010-02-09 11:13:56 +01:00
2010-03-26 11:33:57 +01:00
2010-04-01 13:31:07 -07:00
2010-02-24 11:01:33 -08:00
2009-07-14 16:25:05 +02:00
2009-09-15 15:08:40 -04:00
2009-12-09 16:28:59 -08:00
2010-03-26 11:33:57 +01:00
2010-03-12 15:52:32 -08:00
2010-03-12 15:52:32 -08:00
2010-02-16 18:21:32 +01:00
2010-03-26 11:33:57 +01:00
2010-03-08 16:55:37 +01:00