This repository has been archived on 2026-03-14. You can view files and clone it, but cannot push or open issues or pull requests.

Michal Simek 598acab44d microblaze: Define correct L1_CACHE_SHIFT value ...

Microblaze cacheline length is configurable and current cpu
uses two cacheline length 4 and 8.

We are taking conservative maximum value to be sure that cacheline
alignment is satisfied for all cases.

Here is the calculation for cacheline lenght 8  32bit=4Byte values
which is corresponding with SHIFT 5.

Signed-off-by: Michal Simek <monstr@monstr.eu>

2010-05-06 11:21:59 +02:00

..

asm

microblaze: Define correct L1_CACHE_SHIFT value

2010-05-06 11:21:59 +02:00