ce21b3c964
This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>