0ee50254df
This corrects a race with the PHY RST bit not being set properly if the PLL status changes right before timeout. This resulted in it potentially failing even if the device came up in time. Special thanks to Mr. Juha Leppanen and Iwamatsu-san for reporting this out and reviewing it. Reported-by: Juha Leppanen <juha_motorsportcom@luukku.com> Reviewed-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Tested-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>