Add snapshot of mach-msm from beginning of msm-3.4
This also includes various documentation files and the devicetree files for msm boards. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Stephen Boyd
91
AndroidKernel.mk
Normal file
91
AndroidKernel.mk
Normal file
@@ -0,0 +1,91 @@
|
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#Android makefile to build kernel as a part of Android Build
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PERL = perl
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ifeq ($(TARGET_PREBUILT_KERNEL),)
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KERNEL_OUT := $(TARGET_OUT_INTERMEDIATES)/KERNEL_OBJ
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KERNEL_CONFIG := $(KERNEL_OUT)/.config
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TARGET_PREBUILT_INT_KERNEL := $(KERNEL_OUT)/arch/arm/boot/zImage
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KERNEL_HEADERS_INSTALL := $(KERNEL_OUT)/usr
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KERNEL_MODULES_INSTALL := system
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KERNEL_MODULES_OUT := $(TARGET_OUT)/lib/modules
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KERNEL_IMG=$(KERNEL_OUT)/arch/arm/boot/Image
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MSM_ARCH ?= $(shell $(PERL) -e 'while (<>) {$$a = $$1 if /CONFIG_ARCH_((?:MSM|QSD)[a-zA-Z0-9]+)=y/; $$r = $$1 if /CONFIG_MSM_SOC_REV_(?!NONE)(\w+)=y/;} print lc("$$a$$r\n");' $(KERNEL_CONFIG))
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KERNEL_USE_OF ?= $(shell $(PERL) -e '$$of = "n"; while (<>) { if (/CONFIG_USE_OF=y/) { $$of = "y"; break; } } print $$of;' kernel/arch/arm/configs/$(KERNEL_DEFCONFIG))
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ifeq "$(KERNEL_USE_OF)" "y"
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DTS_NAME ?= $(MSM_ARCH)
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DTS_FILES = $(wildcard $(TOP)/kernel/arch/arm/boot/dts/$(DTS_NAME)*.dts)
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DTS_FILE = $(lastword $(subst /, ,$(1)))
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DTB_FILE = $(addprefix $(KERNEL_OUT)/arch/arm/boot/,$(patsubst %.dts,%.dtb,$(call DTS_FILE,$(1))))
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ZIMG_FILE = $(addprefix $(KERNEL_OUT)/arch/arm/boot/,$(patsubst %.dts,%-zImage,$(call DTS_FILE,$(1))))
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KERNEL_ZIMG = $(KERNEL_OUT)/arch/arm/boot/zImage
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DTC = $(KERNEL_OUT)/scripts/dtc/dtc
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define append-dtb
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mkdir -p $(KERNEL_OUT)/arch/arm/boot;\
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$(foreach d, $(DTS_FILES), \
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$(DTC) -p 1024 -O dtb -o $(call DTB_FILE,$(d)) $(d); \
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cat $(KERNEL_ZIMG) $(call DTB_FILE,$(d)) > $(call ZIMG_FILE,$(d));)
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endef
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else
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define append-dtb
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endef
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endif
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ifeq ($(TARGET_USES_UNCOMPRESSED_KERNEL),true)
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$(info Using uncompressed kernel)
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TARGET_PREBUILT_KERNEL := $(KERNEL_OUT)/piggy
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else
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TARGET_PREBUILT_KERNEL := $(TARGET_PREBUILT_INT_KERNEL)
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endif
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define mv-modules
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mdpath=`find $(KERNEL_MODULES_OUT) -type f -name modules.dep`;\
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if [ "$$mdpath" != "" ];then\
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mpath=`dirname $$mdpath`;\
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ko=`find $$mpath/kernel -type f -name *.ko`;\
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for i in $$ko; do mv $$i $(KERNEL_MODULES_OUT)/; done;\
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fi
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endef
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define clean-module-folder
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mdpath=`find $(KERNEL_MODULES_OUT) -type f -name modules.dep`;\
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if [ "$$mdpath" != "" ];then\
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mpath=`dirname $$mdpath`; rm -rf $$mpath;\
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fi
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endef
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$(KERNEL_OUT):
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mkdir -p $(KERNEL_OUT)
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$(KERNEL_CONFIG): $(KERNEL_OUT)
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$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi- $(KERNEL_DEFCONFIG)
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$(KERNEL_OUT)/piggy : $(TARGET_PREBUILT_INT_KERNEL)
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$(hide) gunzip -c $(KERNEL_OUT)/arch/arm/boot/compressed/piggy.gzip > $(KERNEL_OUT)/piggy
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$(TARGET_PREBUILT_INT_KERNEL): $(KERNEL_OUT) $(KERNEL_CONFIG) $(KERNEL_HEADERS_INSTALL)
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$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi-
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$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi- modules
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$(MAKE) -C kernel O=../$(KERNEL_OUT) INSTALL_MOD_PATH=../../$(KERNEL_MODULES_INSTALL) ARCH=arm CROSS_COMPILE=arm-eabi- modules_install
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$(mv-modules)
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$(clean-module-folder)
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$(append-dtb)
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$(KERNEL_HEADERS_INSTALL): $(KERNEL_OUT) $(KERNEL_CONFIG)
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$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi- headers_install
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kerneltags: $(KERNEL_OUT) $(KERNEL_CONFIG)
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$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi- tags
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kernelconfig: $(KERNEL_OUT) $(KERNEL_CONFIG)
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env KCONFIG_NOTIMESTAMP=true \
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$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi- menuconfig
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env KCONFIG_NOTIMESTAMP=true \
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$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi- savedefconfig
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cp $(KERNEL_OUT)/defconfig kernel/arch/arm/configs/$(KERNEL_DEFCONFIG)
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endif
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18
Documentation/ABI/testing/sysfs-bus-pil
Normal file
18
Documentation/ABI/testing/sysfs-bus-pil
Normal file
@@ -0,0 +1,18 @@
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What: /sys/bus/pil/devices/.../name
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Date: March 2012
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Contact: Stephen Boyd <sboyd@codeaurora.org>
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Description:
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Shows the name of the peripheral used in pil_get().
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What: /sys/bus/pil/devices/.../state
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Date: March 2012
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Contact: Stephen Boyd <sboyd@codeaurora.org>
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Description:
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Shows the state state of a peripheral. Current states
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supported are:
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OFFLINE - peripheral is offline
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ONLINE - peripheral is online
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This file supports poll() to detect when a peripheral changes
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state.
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@@ -2,112 +2,79 @@ This document provides an overview of the msm_gpiomux interface, which
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is used to provide gpio pin multiplexing and configuration on mach-msm
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targets.
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History
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=======
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The first-generation API for gpio configuration & multiplexing on msm
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is the function gpio_tlmm_config(). This function has a few notable
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shortcomings, which led to its deprecation and replacement by gpiomux:
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The 'disable' parameter: Setting the second parameter to
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gpio_tlmm_config to GPIO_CFG_DISABLE tells the peripheral
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processor in charge of the subsystem to perform a look-up into a
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low-power table and apply the low-power/sleep setting for the pin.
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As the msm family evolved this became problematic. Not all pins
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have sleep settings, not all peripheral processors will accept requests
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to apply said sleep settings, and not all msm targets have their gpio
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subsystems managed by a peripheral processor. In order to get consistent
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behavior on all targets, drivers are forced to ignore this parameter,
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rendering it useless.
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The 'direction' flag: for all mux-settings other than raw-gpio (0),
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the output-enable bit of a gpio is hard-wired to a known
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input (usually VDD or ground). For those settings, the direction flag
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is meaningless at best, and deceptive at worst. In addition, using the
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direction flag to change output-enable (OE) directly can cause trouble in
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gpiolib, which has no visibility into gpio direction changes made
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in this way. Direction control in gpio mode should be made through gpiolib.
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Key Features of gpiomux
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=======================
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- A consistent interface across all generations of msm. Drivers can expect
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the same results on every target.
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- gpiomux plays nicely with gpiolib. Functions that should belong to gpiolib
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are left to gpiolib and not duplicated here. gpiomux is written with the
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intent that gpio_chips will call gpiomux reference-counting methods
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from their request() and free() hooks, providing full integration.
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- Tabular configuration. Instead of having to call gpio_tlmm_config
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hundreds of times, gpio configuration is placed in a single table.
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- Per-gpio sleep. Each gpio is individually reference counted, allowing only
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those lines which are in use to be put in high-power states.
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- 0 means 'do nothing': all flags are designed so that the default memset-zero
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equates to a sensible default of 'no configuration', preventing users
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from having to provide hundreds of 'no-op' configs for unused or
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unwanted lines.
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Usage
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=====
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To use gpiomux, provide configuration information for relevant gpio lines
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in the msm_gpiomux_configs table. Since a 0 equates to "unconfigured",
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only those lines to be managed by gpiomux need to be specified. Here
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is a completely fictional example:
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To use gpiomux, do the following before the msmgpio gpiochips probe:
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struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
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[12] = {
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.active = GPIOMUX_VALID | GPIOMUX_DRV_8MA | GPIOMUX_FUNC_1,
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.suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN,
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},
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[34] = {
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.suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN,
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- Call msm_gpiomux_init to allocate needed resources.
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- Install one or more sets of gpiomux configuration data via
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msm_gpiomux_install and/or msm_gpiomux_write.
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Failing to finish these steps before the probe of msmgpio can result in calls
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from msmgpio to gpiomux to try and activate lines which have not yet
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been configured.
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A basic gpiomux setting is described by a gpiomux_setting structure.
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A gpiomux configuration is a group of those settings (one for each power
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state of the board) paired with a specific gpio, like so:
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struct msm_gpiomux_config gpio123_config __initdata = {
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.gpio = 123,
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.settings = {
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[GPIOMUX_ACTIVE] = {
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.func = GPIOMUX_FUNC_GPIO,
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.drv = GPIOMUX_DRV_2MA,
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.pull = GPIOMUX_PULL_NONE,
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.dir = GPIOMUX_OUT_HIGH,
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},
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[GPIOMUX_SUSPENDED] = {
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.func = GPIOMUX_FUNC_3,
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.drv = GPIOMUX_DRV_8MA,
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.pull = GPIOMUX_PULL_DOWN,
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},
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},
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};
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To indicate that a gpio is in use, call msm_gpiomux_get() to increase
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its reference count. To decrease the reference count, call msm_gpiomux_put().
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The effect of this configuration is as follows:
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When the system boots, gpios 12 and 34 will be initialized with their
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'suspended' configurations. All other gpios, which were left unconfigured,
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will not be touched.
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- When the system boots, gpio 123 will be put into the SUSPENDED setting.
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- When the reference count for gpio 123 rises above 0, the ACTIVE setting
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will be applied.
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- When the reference count falls back to 0, the SUSPENDED setting will be
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reapplied.
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When msm_gpiomux_get() is called on gpio 12 to raise its reference count
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above 0, its active configuration will be applied. Since no other gpio
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line has a valid active configuration, msm_gpiomux_get() will have no
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effect on any other line.
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The reference count rises when msm_gpiomux_get() is called and falls
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when msm_gpiomux_put() is called. msmgpio has hooks to these functions
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in its gpiolib implementation. This means that when you call gpio_request()
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on an msmgpio, msm_gpiomux_get() is automatically called on your behalf.
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Similarly, when you call gpio_free(), msm_gpiomux_put() is called for you.
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This allows generic drivers to obtain low-level management of msmgpio lines
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without having to be aware of the gpiomux layer.
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When msm_gpiomux_put() is called on gpio 12 or 34 to drop their reference
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count to 0, their suspended configurations will be applied.
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Since no other gpio line has a valid suspended configuration, no other
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gpio line will be effected by msm_gpiomux_put(). Since gpio 34 has no valid
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active configuration, this is effectively a no-op for gpio 34 as well,
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with one small caveat, see the section "About Output-Enable Settings".
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Note that the .dir field is ignored if .func != GPIOMUX_FUNC_GPIO, since
|
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software control of gpios is allowed only in GPIO mode. By selecting any
|
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other .func, you assign the gpio to another piece of hardware and lose
|
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control of it from gpiolib. You can still reserve such gpios with gpio_request
|
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to prevent other modules from using them while they're in such a state,
|
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but other gpiolib functions will not behave as you expect if .func != GPIO.
|
||||
|
||||
All of the GPIOMUX_VALID flags may seem like unnecessary overhead, but
|
||||
they address some important issues. As unused entries (all those
|
||||
except 12 and 34) are zero-filled, gpiomux needs a way to distinguish
|
||||
the used fields from the unused. In addition, the all-zero pattern
|
||||
is a valid configuration! Therefore, gpiomux defines an additional bit
|
||||
which is used to indicate when a field is used. This has the pleasant
|
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side-effect of allowing calls to msm_gpiomux_write to use '0' to indicate
|
||||
that a value should not be changed:
|
||||
|
||||
msm_gpiomux_write(0, GPIOMUX_VALID, 0);
|
||||
|
||||
replaces the active configuration of gpio 0 with an all-zero configuration,
|
||||
but leaves the suspended configuration as it was.
|
||||
If a configuration is omitted, nothing will happen at the relevant transitions.
|
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This allows for the creation of 'static configurations' which do not
|
||||
change as the line is requested and freed.
|
||||
|
||||
Static Configurations
|
||||
=====================
|
||||
|
||||
To install a static configuration, which is applied at boot and does
|
||||
not change after that, install a configuration with a suspended component
|
||||
but no active component, as in the previous example:
|
||||
but no active component:
|
||||
|
||||
[34] = {
|
||||
.suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN,
|
||||
.gpio = ...,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = {
|
||||
...
|
||||
},
|
||||
},
|
||||
|
||||
The suspended setting is applied during boot, and the lack of any valid
|
||||
@@ -153,24 +120,3 @@ This provides important functionality:
|
||||
This mechanism allows for "auto-request" of gpiomux lines via gpiolib
|
||||
when it is suitable. Drivers wishing more exact control are, of course,
|
||||
free to also use msm_gpiomux_set and msm_gpiomux_get.
|
||||
|
||||
About Output-Enable Settings
|
||||
============================
|
||||
|
||||
Some msm targets do not have the ability to query the current gpio
|
||||
configuration setting. This means that changes made to the output-enable
|
||||
(OE) bit by gpiolib cannot be consistently detected and preserved by gpiomux.
|
||||
Therefore, when gpiomux applies a configuration setting, any direction
|
||||
settings which may have been applied by gpiolib are lost and the default
|
||||
input settings are re-applied.
|
||||
|
||||
For this reason, drivers should not assume that gpio direction settings
|
||||
continue to hold if they free and then re-request a gpio. This seems like
|
||||
common sense - after all, anybody could have obtained the line in the
|
||||
meantime - but it needs saying.
|
||||
|
||||
This also means that calls to msm_gpiomux_write will reset the OE bit,
|
||||
which means that if the gpio line is held by a client of gpiolib and
|
||||
msm_gpiomux_write is called, the direction setting has been lost and
|
||||
gpiolib's internal state has been broken.
|
||||
Release gpio lines before reconfiguring them.
|
||||
|
||||
267
Documentation/arm/msm/pil.txt
Normal file
267
Documentation/arm/msm/pil.txt
Normal file
@@ -0,0 +1,267 @@
|
||||
Introduction
|
||||
============
|
||||
|
||||
The PIL (Peripheral Image Loader) driver loads peripheral images into memory
|
||||
and interfaces with the Peripheral Authentication Service (PAS) to
|
||||
authenticate and reset peripherals embedded in the SoC.
|
||||
|
||||
The PAS could either be running under secure mode in the application
|
||||
processor (secure boot support) or be running as a non-secure kernel driver
|
||||
(non-secure boot support).
|
||||
|
||||
The PIL driver also does housekeeping to handle cases where more than one
|
||||
client driver is using the same peripheral.
|
||||
|
||||
Some examples of peripherals are modem, DSP and sensors.
|
||||
|
||||
Hardware description
|
||||
====================
|
||||
|
||||
The memory used by the peripherals for code and data storage will be
|
||||
accessible as normal memory to the application processor.
|
||||
|
||||
The non-secure code (Linux kernel) will have read/write permissions to the
|
||||
peripheral memory by default.
|
||||
|
||||
The PAS will have access to a MPU (memory protection unit) that can lock away
|
||||
the pages of memory from the Linux kernel. It will also have access to
|
||||
registers that can reset each peripheral.
|
||||
|
||||
Software description
|
||||
====================
|
||||
|
||||
The PAS provides the following three APIs:
|
||||
|
||||
* Init image - Takes as input the peripheral id and firmware metadata and
|
||||
returns a status indicating the authenticity of the firmware metadata. The
|
||||
firmware metadata consists of a standard ELF32 header followed by a program
|
||||
header table and an optional blob of data used to authenticate the metadata
|
||||
and the rest of the firmware.
|
||||
|
||||
* Verify segment - Takes as input the firmware segment id and the length of
|
||||
the segment. Authenticates whatever amount (specified by the "length"
|
||||
parameter) of the firmware segment that has been loaded and removes
|
||||
non-secure mode read/write permissions for the pages belonging to the
|
||||
firmware segment. Allows multiple calls for the same firmware segment to
|
||||
allow partial loading and authentication.
|
||||
|
||||
* Auth and Reset - Verifies all the necessary firmware segments have been
|
||||
loaded and authenticated and then resets the peripheral.
|
||||
|
||||
The user space is expected to provide the firmware metadata and firmware
|
||||
segments as separate files on persistent storage. See "Interface" section for
|
||||
further details.
|
||||
|
||||
The PIL driver will use the request_firmware API provided by the Linux kernel
|
||||
to read the firmware and firmware metadata from persistent storage.
|
||||
|
||||
When a client driver requests for a peripheral to be enabled, the PIL driver
|
||||
increments the reference count for that peripheral, loads the firmware
|
||||
metadata and calls the PAS Init Image API that initializes the authentication
|
||||
state machine using the firmware metadata.
|
||||
|
||||
If the initialization succeeds, the PIL driver loads the appropriate firmware
|
||||
segments into their respective memory locations and call the PAS Verify
|
||||
segment API on each of the loaded segments to authenticate and lock it.
|
||||
|
||||
After all the firmware segments have been successfully loaded and
|
||||
authenticated, the PAS Auth and Reset API is called to reset the peripheral
|
||||
and initiate its boot sequence.
|
||||
|
||||
A peripheral enable request to the PIL driver will block until it succeeds
|
||||
(or fails) to initiate the peripheral boot sequence but will NOT block until
|
||||
the peripheral is ready. It is not possible to block until a peripheral is
|
||||
ready since the semantics of "ready" is subjective to the caller.
|
||||
|
||||
The PIL driver will maintain a reference count for each of the peripherals.
|
||||
So, if a peripheral is already under use and another client driver requests
|
||||
for the peripheral to be enabled, the PIL driver will immediately return a
|
||||
value to indicate success.
|
||||
|
||||
When all the client drivers of a particular peripheral no longer need the
|
||||
peripheral and the reference count reaches zero, the PIL driver can cleanly
|
||||
shut down the peripheral. Since a lot of drivers in their current state can't
|
||||
handle a peripheral restart, the PIL driver will never let the reference
|
||||
count go back to zero.
|
||||
|
||||
All information about a peripheral, like firmware filenames, peripheral ID
|
||||
passed to PAS, etc, will be hard coded in the PIL driver.
|
||||
|
||||
All the PIL APIs will execute in the context of the caller. This includes
|
||||
calls from the PIL driver to the PAS driver. The PAS driver might decide to
|
||||
switch into secure mode from a separate workqueue or in the same context as
|
||||
the caller, but that shouldn't have any implications for the PIL API callers
|
||||
since all the PIL APIs are blocking calls.
|
||||
|
||||
Dependencies:
|
||||
-------------
|
||||
* Firmware class (CONFIG_FW_LOADER) for using the request_firmware API to
|
||||
load firmware from persistent storage.
|
||||
* PAS to authenticate firmware and bring a peripheral out of reset.
|
||||
|
||||
Error cases:
|
||||
------------
|
||||
The PIL driver could fail to enable a peripheral for several reasons like not
|
||||
having enough memory to load firmware and metadata, being unable to
|
||||
communicate with the PAS, the PAS returning with an error, etc. For all
|
||||
possible error cases, the PIL driver does not perform any retries and returns
|
||||
an appropriate error code. The client drivers should always check for success
|
||||
before trying to access the peripheral.
|
||||
|
||||
Design
|
||||
======
|
||||
|
||||
Design goals:
|
||||
-------------
|
||||
* The PIL driver must be agnostic to the actual format and method used to
|
||||
authenticate the firmware.
|
||||
* Allow for future expansion to support demand loading of parts of firmware
|
||||
for each peripheral.
|
||||
* Move most of the work into the preprocessing/building stage of the firmware.
|
||||
* Provide an API to the client drivers that absolves them from having to know
|
||||
the structure or names of the firmware in persistent storage.
|
||||
* Handle multiple client drivers wanting to enable the same peripheral.
|
||||
|
||||
|
||||
Design reasons:
|
||||
---------------
|
||||
The user space is expected to provide the firmware metadata and segments as
|
||||
separate files for the following reasons:
|
||||
* Don't need to load the whole ELF file if the authentication info is
|
||||
invalid.
|
||||
* Works better during low memory conditions since the amount of memory used
|
||||
at any given instant when loading one segment at a time is smaller than
|
||||
loading the whole ELF file.
|
||||
* Since an ELF segment in memory can be much bigger than on file, having a
|
||||
flat binary would waste a lot of space due to zero-fills.
|
||||
* Allows for future enhancements to the loading procedure.
|
||||
|
||||
Design tradeoffs:
|
||||
-----------------
|
||||
* With appropriate changes to the request_firmware API, the firmware blobs
|
||||
could be directly loaded into the right memory location. But due to the
|
||||
additional work and community approval that would be needed for modifying
|
||||
the request_firmware API, we load the firmware blobs into kernel memory and
|
||||
then copy them into the appropriate locations.
|
||||
|
||||
Alternate designs:
|
||||
------------------
|
||||
One of the alternate designs that were considered required the firmware to be
|
||||
a flat binary. Although this design would simplify the PIL driver, it would
|
||||
result in the waste of a lot of persistent storage space (due to large
|
||||
zero-fills), prevent demand loading of segments in the future and use a lot
|
||||
more memory while loading the firmware.
|
||||
|
||||
Software layering:
|
||||
------------------
|
||||
The peripheral authentication, reset and shutdown implementation is factored
|
||||
away into a Peripheral Authentication Service driver to allow the PIL driver
|
||||
to be agnostic of secure vs. non-secure boot and the mechanisms needed for
|
||||
communicating with any code that might be running in secure mode.
|
||||
|
||||
Power Management
|
||||
================
|
||||
|
||||
Some of the peripherals might support being turned off when not in use.
|
||||
Support for this might be disabled in the initial implementation of the PIL
|
||||
driver since many of the existing drivers can not handle peripheral restart.
|
||||
|
||||
SMP/multi-core
|
||||
==============
|
||||
|
||||
Will use mutexes to protected data that might be shared (reference count,
|
||||
etc).
|
||||
|
||||
Security
|
||||
========
|
||||
|
||||
The PIL driver must validate the physical memory addresses specified in the
|
||||
ELF and program header table before loading firmware segments to make sure
|
||||
it's not overwriting any memory used by the kernel and possibly PMEM regions
|
||||
(if it can be done without being an ugly hack). The PIL driver might need to
|
||||
maintain a white list or black list of physical memory address ranges to
|
||||
perform the address validation.
|
||||
|
||||
Performance
|
||||
===========
|
||||
|
||||
As mentioned in the design section, the loading of firmware segments is not
|
||||
optimal and has room for improvement.
|
||||
|
||||
Interface
|
||||
=========
|
||||
|
||||
In kernel APIs:
|
||||
void * pil_get(char *peripheral_name)
|
||||
- Enables (if not already enabled) a peripheral and returns a handle
|
||||
that can be used to disable the peripheral at a later time. If
|
||||
peripheral can't be enabled successfully, then returns an error
|
||||
(use IS_ERR) indicating the reason.
|
||||
|
||||
void pil_put(void *peripheral_handle)
|
||||
- Inform PIL that this client no longer needs the peripheral to be
|
||||
active. Does not necessarily mean that the peripheral would be
|
||||
disabled or powered off.
|
||||
|
||||
|
||||
User space APIs:
|
||||
All firmware must be located in the path that is expected by the hotplug (or
|
||||
compatible) daemon. A hotplug (or compatible) daemon should be running and be
|
||||
able to handle events from the kernel requesting for a firmware file.
|
||||
|
||||
The basename of the firmware files will depend on the peripheral. For a given
|
||||
peripheral, the metadata filename should end with a ".mdt" and the firmware
|
||||
segment files should end with ".bXX" where XX denotes the index of the
|
||||
firmware segment starting from 0.
|
||||
|
||||
Android hotplug compatible daemon expects the firmware files to be under
|
||||
/etc/firmware.
|
||||
|
||||
Driver parameters
|
||||
=================
|
||||
|
||||
No module or kernel command line parameters supported.
|
||||
|
||||
Config options
|
||||
==============
|
||||
|
||||
This driver is enabled using the MSM_PIL kernel config option and will
|
||||
depend on the CONFIG_FW_LOADER being available.
|
||||
|
||||
Dependencies
|
||||
============
|
||||
|
||||
Depends on firmware class module for the request_firmware API.
|
||||
|
||||
Interacts with the PAS to authenticate the firmware and to initiate the boot
|
||||
sequence of a peripheral.
|
||||
|
||||
Doesn't communicate with other processors since the secure code, if any, will
|
||||
be running on the application processor cores.
|
||||
|
||||
User space utilities
|
||||
====================
|
||||
|
||||
None.
|
||||
|
||||
Other
|
||||
=====
|
||||
|
||||
The firmware_class driver might be changed in the future to directly load the
|
||||
firmware into memory locations provided by the caller of request_firmware().
|
||||
|
||||
Known issues
|
||||
============
|
||||
|
||||
Since support for cleanly shutting down peripherals is yet to be added, the
|
||||
reference count of peripherals will never be allowed to go to zero once it
|
||||
becomes non-zero.
|
||||
|
||||
To do
|
||||
=====
|
||||
|
||||
* Add support for turning off peripherals when they are not in use.
|
||||
* Modify request_firmware() to directly copy firmware blobs into the
|
||||
appropriate memory locations.
|
||||
* Add support for demand loading of firmware segments.
|
||||
* Add support for forced peripheral restarts.
|
||||
157
Documentation/arm/msm/rpm.txt
Normal file
157
Documentation/arm/msm/rpm.txt
Normal file
@@ -0,0 +1,157 @@
|
||||
Introduction
|
||||
============
|
||||
|
||||
Resource Power Manager (RPM)
|
||||
|
||||
RPM is a dedicated hardware engine for managing shared SoC resources,
|
||||
which includes buses, clocks, power rails, etc. The goal of RPM is
|
||||
to achieve the maximum power savings while satisfying the SoC's
|
||||
operational and performance requirements. RPM accepts resource
|
||||
requests from multiple RPM masters. It arbitrates and aggregates the
|
||||
requests, and configures the shared resources. The RPM masters are
|
||||
the application processor, the modem processor, as well as some
|
||||
hardware accelerators.
|
||||
|
||||
The RPM driver provides an API for interacting with RPM. Kernel code
|
||||
calls the RPM driver to request RPM-managed, shared resources.
|
||||
Kernel code can also register with the driver for RPM notifications,
|
||||
which are sent when the status of shared resources change.
|
||||
|
||||
Hardware description
|
||||
====================
|
||||
|
||||
RPM exposes a separate region of registers to each of the RPM masters.
|
||||
In general, each register represents some shared resource(s). At a
|
||||
very basic level, a master requests resources by writing to the
|
||||
registers, then generating an interrupt to RPM. RPM processes the
|
||||
request, writes acknowledgement to the registers, then generates an
|
||||
interrupt to the master.
|
||||
|
||||
In addition to the master-specific regions, RPM also exposes a shared
|
||||
region that contains the current status of the shared resources. Only
|
||||
RPM can write to the status region, but every master can read from it.
|
||||
|
||||
RPM contains internal logics that aggregate and arbitrate among
|
||||
requests from the various RPM masters. It interfaces with the PMIC,
|
||||
the bus arbitration block, and the clock controller block in order to
|
||||
configure the shared resources.
|
||||
|
||||
Software description
|
||||
====================
|
||||
|
||||
The RPM driver encapsulates the low level RPM interactions, which
|
||||
rely on reading/writing registers and generating/processing
|
||||
interrupts, and provides a higher level synchronuous set/clear/get
|
||||
interface. Most functions take an array of id-value pairs.
|
||||
The ids identify the RPM registers which would correspond to some
|
||||
RPM resources, the values specify the new resource values.
|
||||
|
||||
The RPM driver synchronizes accesses to RPM. It protects against
|
||||
simultaneous accesses from multiple tasks, on SMP cores, in task
|
||||
contexts, and in atomic contexts.
|
||||
|
||||
Design
|
||||
======
|
||||
|
||||
Design goals:
|
||||
- Encapsulate low level RPM interactions.
|
||||
- Provide a synchronuous set/clear/get interface.
|
||||
- Synchronize simultaneous software accesses to RPM.
|
||||
|
||||
Power Management
|
||||
================
|
||||
|
||||
RPM is part of the power management architecture for MSM 8660. RPM
|
||||
manages shared system resources to lower system power.
|
||||
|
||||
SMP/multi-core
|
||||
==============
|
||||
|
||||
The RPM driver uses mutex to synchronize client accesses among tasks.
|
||||
It uses spinlocks to synchronize accesses from atomic contexts and
|
||||
SMP cores.
|
||||
|
||||
Security
|
||||
========
|
||||
|
||||
None.
|
||||
|
||||
Performance
|
||||
===========
|
||||
|
||||
None.
|
||||
|
||||
Interface
|
||||
=========
|
||||
|
||||
msm_rpm_get_status():
|
||||
The function reads the shared status region and returns the current
|
||||
resource values, which are the arbitrated/aggregated results across
|
||||
all RPM masters.
|
||||
|
||||
msm_rpm_set():
|
||||
The function makes a resource request to RPM.
|
||||
|
||||
msm_rpm_set_noirq():
|
||||
The function is similar to msm_rpm_set() except that it must be
|
||||
called with interrupts masked. If possible, use msm_rpm_set()
|
||||
instead, to maximize CPU throughput.
|
||||
|
||||
msm_rpm_clear():
|
||||
The function makes a resource request to RPM to clear resource values.
|
||||
Once the values are cleared, the resources revert back to their default
|
||||
values for this RPM master. RPM internally uses the default values as
|
||||
the requests from this RPM master when arbitrating and aggregating with
|
||||
requests from other RPM masters.
|
||||
|
||||
msm_rpm_clear_noirq():
|
||||
The function is similar to msm_rpm_clear() except that it must be
|
||||
called with interrupts masked. If possible, use msm_rpm_clear()
|
||||
instead, to maximize CPU throughput.
|
||||
|
||||
msm_rpm_register_notification():
|
||||
The function registers for RPM notification. When the specified
|
||||
resources change their status on RPM, RPM sends out notifications
|
||||
and the driver will "up" the semaphore in struct
|
||||
msm_rpm_notification.
|
||||
|
||||
msm_rpm_unregister_notification():
|
||||
The function unregisters a notification.
|
||||
|
||||
msm_rpm_init():
|
||||
The function initializes the RPM driver with platform specific data.
|
||||
|
||||
Driver parameters
|
||||
=================
|
||||
|
||||
None.
|
||||
|
||||
Config options
|
||||
==============
|
||||
|
||||
MSM_RPM
|
||||
|
||||
Dependencies
|
||||
============
|
||||
|
||||
None.
|
||||
|
||||
User space utilities
|
||||
====================
|
||||
|
||||
None.
|
||||
|
||||
Other
|
||||
=====
|
||||
|
||||
None.
|
||||
|
||||
Known issues
|
||||
============
|
||||
|
||||
None.
|
||||
|
||||
To do
|
||||
=====
|
||||
|
||||
None.
|
||||
132
Documentation/arm/msm/tz_log.txt
Normal file
132
Documentation/arm/msm/tz_log.txt
Normal file
@@ -0,0 +1,132 @@
|
||||
Introduction:
|
||||
=============
|
||||
|
||||
The tz_log driver is a platform device driver that exposes a debugfs
|
||||
interface for accessing and displaying diagnostic information related
|
||||
to secure code (Trustzone).
|
||||
|
||||
The Secure code (Trustzone) will store the diagnostic data in 4KB of
|
||||
IMEM. The address of this IMEM region varies from platform. The
|
||||
diagnostic data encodes information related to secure code boot-up,
|
||||
reset, interrupt and other attributes in a specific format as shown
|
||||
below:
|
||||
|
||||
----------------------------
|
||||
| |
|
||||
| General info |
|
||||
| (Magic #, CPU cnt etc) |
|
||||
| |
|
||||
----------------------------
|
||||
| |
|
||||
| VMID info |
|
||||
| |
|
||||
----------------------------
|
||||
| |
|
||||
| Boot info (per CPU) |
|
||||
| |
|
||||
----------------------------
|
||||
| |
|
||||
| Reset info (per CPU) |
|
||||
| |
|
||||
----------------------------
|
||||
| |
|
||||
| Interrupt info (per CPU) |
|
||||
| |
|
||||
----------------------------
|
||||
| |
|
||||
| Data logged by TZ |
|
||||
| |
|
||||
----------------------------
|
||||
|
||||
During the initialization of the driver module, this 4KB of IMEM
|
||||
is remapped for access by kernel. Further more, an additonal 4KB
|
||||
memory is allocated for storing the formatted data that will be
|
||||
displayed by the debugfs interface.
|
||||
|
||||
Once the device is booted up and HLOS is up, the standard debugfs
|
||||
interface is used to read out and display this information that
|
||||
was logged in by secure code in a specific format as shown below.
|
||||
|
||||
Debugfs is typically mounted with a command like:
|
||||
mount -t debugfs none /sys/kernel/debug
|
||||
(Or an equivalent /etc/fstab line).
|
||||
|
||||
Note that the debugfs API is exported GPL-only to modules.
|
||||
|
||||
Software description
|
||||
====================
|
||||
|
||||
The tz_log module is a Linux platform device driver with a debugfs
|
||||
interface. The goal of this module is to provide a way to peek into
|
||||
the Trustzone diagnostic information to help debug issues with
|
||||
Trustzone. Although, this tz_log platform device driver will be
|
||||
compiled into the kernel, the debugfs entries will not be exposed
|
||||
unless Trustzone is supported by the platform.
|
||||
|
||||
|
||||
On loading the tz_log driver, tzdbgfs_init() is invoked. tzdbgfs_init()
|
||||
initializes the tz_log debugfs interface. The following is done in
|
||||
this initialization call.
|
||||
|
||||
(1) Create a directory "tzdbg", to hold a set of debugfs files
|
||||
|
||||
(2) Create the following debugfs files in the "tzdbg" directory
|
||||
- boot_info
|
||||
Contains information on the warm boot jump address
|
||||
- reset_info
|
||||
Contains information on the cause of a CPU reset, number of
|
||||
resets occurred on a specific CPU
|
||||
- interrupt_info
|
||||
Contains information on the number of IRQ and FIQ Interrupts
|
||||
(with a brief description), interrupts fired and the number
|
||||
of times it is fired on a specific CPU.
|
||||
- general_info
|
||||
Contains information on number of CPUs supported, magic number,
|
||||
version number.
|
||||
- vmid_info
|
||||
Contains information on VMID supported, with a brief description
|
||||
- log
|
||||
Debug information (ASCII text) that is logged by Trustzone
|
||||
|
||||
Following are the set of file operation defines and register
|
||||
- read()
|
||||
- open()
|
||||
|
||||
(3) Remap the IMEM region where the secure code diagnostic information
|
||||
is stored.
|
||||
|
||||
(4) Allocate 4KB buffer for storing the formatted information
|
||||
to be displayed
|
||||
|
||||
When the tz_log driver is unloaded the tz_log debugfs entries are
|
||||
explicitly removed.
|
||||
|
||||
|
||||
Power Management
|
||||
================
|
||||
|
||||
n/a
|
||||
|
||||
Security
|
||||
========
|
||||
|
||||
None
|
||||
|
||||
Interface
|
||||
=========
|
||||
|
||||
This module will create debugfs files under sys/kernel/debug which
|
||||
contains information that can be displayed by using the "cat" command.
|
||||
|
||||
|
||||
Dependencies
|
||||
============
|
||||
|
||||
This driver interacts with Trustzone operating environment, thus depends
|
||||
on the TZBSP supported architecture. It also depends on debugfs.
|
||||
|
||||
|
||||
To do
|
||||
=====
|
||||
|
||||
TBD
|
||||
47
Documentation/devicetree/bindings/arm/msm/lpm-levels.txt
Normal file
47
Documentation/devicetree/bindings/arm/msm/lpm-levels.txt
Normal file
@@ -0,0 +1,47 @@
|
||||
* Low Power Management Levels
|
||||
|
||||
The application processor in MSM can do a variety of C-States for low power
|
||||
management. These C-States are invoked by the CPUIdle framework when the core
|
||||
becomes idle. But based on the time available until the next scheduled wakeup,
|
||||
the system can do a combination of low power modes of different resources -
|
||||
L2, XO, Vdd Dig and Vdd Mem. The combination is captured in the device tree as
|
||||
lpm-level. The units for voltage are dependent on the PMIC used on the target
|
||||
and are in uV.
|
||||
|
||||
The required nodes for lpm-levels are:
|
||||
|
||||
- compatible: "qcom,lpm-levels"
|
||||
- reg: The numeric level id
|
||||
- qcom,mode: The sleep mode of the processor
|
||||
- qcom,xo: The state of XO clock.
|
||||
- qcom,l2: The state of L2 cache.
|
||||
- qcom,vdd-mem-upper-bound: The upper bound value of mem voltage in uV
|
||||
- qcom,vdd-mem-lower-bound: The lower bound value of mem voltage in uV
|
||||
- qcom,vdd-dig-upper-bound: The upper bound value of dig voltage in uV
|
||||
- qcom,vdd-dig-lower-bound: The lower bound value of dig voltage in uV
|
||||
- qcom,latency-us: The latency in handling the interrupt if this level was
|
||||
chosen, in uSec
|
||||
- qcom,ss-power: The steady state power expelled when the processor is in this
|
||||
level in mWatts
|
||||
- qcom,energy-overhead: The energy used up in entering and exiting this level
|
||||
in mWatts.uSec
|
||||
- qcom,time-overhead: The time spent in entering and exiting this level in uS
|
||||
|
||||
Example:
|
||||
|
||||
qcom,lpm-levels {
|
||||
qcom,lpm-level@0 {
|
||||
reg = <0>;
|
||||
qcom,mode = <0>; /* MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT */
|
||||
qcom,xo = <1>; /* ON */
|
||||
qcom,l2 = <3>; /* ACTIVE */
|
||||
qcom,vdd-mem-upper-bound = <1150000>; /* MAX */
|
||||
qcom,vdd-mem-lower-bound = <1050000>; /* ACTIVE */
|
||||
qcom,vdd-dig-upper-bound = <1150000>; /* MAX */
|
||||
qcom,vdd-dig-lower-bound = <950000>; /* ACTIVE */
|
||||
qcom,latency-us = <100>;
|
||||
qcom,ss-power = <650>;
|
||||
qcom,energy-overhead = <801>;
|
||||
qcom,time-overhead = <200>;
|
||||
};
|
||||
};
|
||||
40
Documentation/devicetree/bindings/arm/msm/pm-boot.txt
Normal file
40
Documentation/devicetree/bindings/arm/msm/pm-boot.txt
Normal file
@@ -0,0 +1,40 @@
|
||||
* Power Management boot configuration (pm-boot)
|
||||
|
||||
Low power management drivers need to specify the warmboot entry path for the
|
||||
application processors to resume from sleep/suspend. The boot configuration
|
||||
can vary if the core does/does not support a secure boot mode. The secure
|
||||
boot configuration boots the core sets up the core sub system registers and
|
||||
calls into the kernel entry point. In the absence of a secure boot mode, the
|
||||
core when powered on from reset will need to be configured with the warmboot
|
||||
entry pointer. The physical and the virtual address for the entry pointer
|
||||
need to provided to the driver.
|
||||
|
||||
|
||||
The device tree parameters for pm-boot are:
|
||||
|
||||
Required parameters:
|
||||
|
||||
- compatible: Must be "qcom,pm-boot"
|
||||
- qcom,mode: The mode that the target will use for booting
|
||||
MSM_PM_BOOT_CONFIG_TZ = 0,
|
||||
MSM_PM_BOOT_CONFIG_RESET_VECTOR_PHYS = 1,
|
||||
MSM_PM_BOOT_CONFIG_RESET_VECTOR_VIRT = 2,
|
||||
MSM_PM_BOOT_CONFIG_REMAP_BOOT_ADDR = 3,
|
||||
|
||||
Optional parameters (based on the mode chosen):
|
||||
|
||||
- qcom,phy-addr: The physical address that will be used for warmboot entry if
|
||||
the processor remap register can be programmed.
|
||||
Needed for modes = { MSM_PM_BOOT_CONFIG_RESET_VECTOR_PHYS,
|
||||
MSM_PM_BOOT_CONFIG_REMAP_BOOT_ADDR }
|
||||
- qcom,virt-addr: The virtual address at which the processor start booting from
|
||||
Needed for modes = { MSM_PM_BOOT_CONFIG_RESET_VECTOR_VIRT,
|
||||
MSM_PM_BOOT_CONFIG_REMAP_BOOT_ADDR }
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
qcom,pm-boot {
|
||||
compatible = "qcom,pm-boot";
|
||||
qcom,mode = <0>; /* MSM_PM_BOOT_CONFIG_TZ */
|
||||
};
|
||||
153
Documentation/devicetree/bindings/arm/msm/rpm-regulator-smd.txt
Normal file
153
Documentation/devicetree/bindings/arm/msm/rpm-regulator-smd.txt
Normal file
@@ -0,0 +1,153 @@
|
||||
Qualcomm RPM Regulators
|
||||
|
||||
rpm-regulator-smd is a regulator driver which supports regulators inside of
|
||||
PMICs which are controlled by the RPM processor. Communication with the RPM
|
||||
processor takes place over SMD.
|
||||
|
||||
Required structure:
|
||||
- RPM regulators must be described in two levels of devices nodes. The first
|
||||
level describes the interface with the RPM. The second level describes
|
||||
properties of one regulator framework interface (of potentially many) to
|
||||
the regulator.
|
||||
|
||||
[First Level Nodes]
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "qcom,rpm-regulator-smd-resource"
|
||||
- qcom,resource-name: Resource name string for this regulator to be used in RPM
|
||||
transactions. Length is 4 characters max.
|
||||
- qcom,resource-id: Resource instance ID for this regulator to be used in RPM
|
||||
transactions.
|
||||
- qcom,regulator-type: Type of this regulator. Supported values are:
|
||||
0 = LDO
|
||||
1 = SMPS
|
||||
2 = VS
|
||||
3 = NCP
|
||||
|
||||
Optional properties:
|
||||
- qcom,allow-atomic: Flag specifying if atomic access is allowed for this
|
||||
regulator. Supported values are:
|
||||
0 or not present = mutex locks used
|
||||
1 = spinlocks used
|
||||
- qcom,enable-time: Time in us to delay after enabling the regulator
|
||||
- qcom,hpm-min-load: Load current in uA which corresponds to the minimum load
|
||||
which requires the regulator to be in high power mode.
|
||||
|
||||
[Second Level Nodes]
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "qcom,rpm-regulator-smd"
|
||||
- regulator-name: A string used as a descriptive name for regulator outputs
|
||||
- qcom,set: Specifies which sets that requests made with this
|
||||
regulator interface should be sent to. Regulator
|
||||
requests sent in the active set take effect immediately.
|
||||
Requests sent in the sleep set take effect when the Apps
|
||||
processor transitions into RPM assisted power collapse.
|
||||
Supported values are:
|
||||
1 = Active set only
|
||||
2 = Sleep set only
|
||||
3 = Both active and sleep sets
|
||||
|
||||
|
||||
|
||||
Optional properties:
|
||||
- parent-supply: phandle to the parent supply/regulator node
|
||||
- qcom,system-load: Load in uA present on regulator that is not
|
||||
captured by any consumer request
|
||||
The following properties specify initial values for parameters to be sent to the
|
||||
RPM in regulator requests.
|
||||
- qcom,init-enable: 0 = regulator disabled
|
||||
1 = regulator enabled
|
||||
- qcom,init-voltage: Voltage in uV
|
||||
- qcom,init-current: Current in mA
|
||||
- qcom,init-ldo-mode: Operating mode to be used with LDO regulators
|
||||
Supported values are:
|
||||
0 = mode determined by current requests
|
||||
1 = force HPM (NPM)
|
||||
- qcom,init-smps-mode: Operating mode to be used with SMPS regulators
|
||||
Supported values are:
|
||||
0 = auto; hardware determines mode
|
||||
1 = mode determined by current requests
|
||||
2 = force HPM (PWM)
|
||||
- qcom,init-pin-ctrl-enable: Bit mask specifying which hardware pins should be
|
||||
used to enable the regulator, if any; supported
|
||||
bits are:
|
||||
0 = ignore all hardware enable signals
|
||||
BIT(0) = follow HW0_EN signal
|
||||
BIT(1) = follow HW1_EN signal
|
||||
BIT(2) = follow HW2_EN signal
|
||||
BIT(3) = follow HW3_EN signal
|
||||
- qcom,init-pin-ctrl-mode: Bit mask specifying which hardware pins should be
|
||||
used to force the regulator into high power
|
||||
mode, if any. Supported bits are:
|
||||
0 = ignore all hardware enable signals
|
||||
BIT(0) = follow HW0_EN signal
|
||||
BIT(1) = follow HW1_EN signal
|
||||
BIT(2) = follow HW2_EN signal
|
||||
BIT(3) = follow HW3_EN signal
|
||||
BIT(4) = follow PMIC awake state
|
||||
- qcom,init-frequency: Switching frequency in MHz for SMPS regulators.
|
||||
Supported values are:
|
||||
0 = Don't care about frequency used
|
||||
1 = 19.20
|
||||
2 = 9.60
|
||||
3 = 6.40
|
||||
4 = 4.80
|
||||
5 = 3.84
|
||||
6 = 3.20
|
||||
7 = 2.74
|
||||
8 = 2.40
|
||||
9 = 2.13
|
||||
10 = 1.92
|
||||
11 = 1.75
|
||||
12 = 1.60
|
||||
13 = 1.48
|
||||
14 = 1.37
|
||||
15 = 1.28
|
||||
16 = 1.20
|
||||
- qcom,init-head-room: Voltage head room in uV required for the
|
||||
regulator
|
||||
- qcom,init-quiet-mode: Specify that quiet mode is needed for an SMPS
|
||||
regulator in order to have lower output noise.
|
||||
Supported values are:
|
||||
0 = No quiet mode
|
||||
1 = Quiet mode
|
||||
2 = Super quiet mode
|
||||
- qcom,init-freq-reason: Consumer requiring specified frequency for an
|
||||
SMPS regulator. Supported values are:
|
||||
0 = None
|
||||
1 = Bluetooth
|
||||
2 = GPS
|
||||
4 = WLAN
|
||||
8 = WAN
|
||||
|
||||
All properties specified within the core regulator framework can also be used in
|
||||
second level nodes. These bindings can be found in:
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt.
|
||||
|
||||
Example:
|
||||
|
||||
rpm-regulator-smpb1 {
|
||||
qcom,resource-name = "smpb";
|
||||
qcom,resource-id = <1>;
|
||||
qcom,regulator-type = <1>;
|
||||
qcom,hpm-min-load = <100000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
pm8841_s1: regulator-s1 {
|
||||
regulator-name = "8841_s1";
|
||||
qcom,set = <3>;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
qcom,init-voltage = <1150000>;
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
pm8841_s1_ao: regulator-s1-ao {
|
||||
regulator-name = "8841_s1_ao";
|
||||
qcom,set = <1>;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
30
Documentation/devicetree/bindings/arm/msm/rpm-smd.txt
Normal file
30
Documentation/devicetree/bindings/arm/msm/rpm-smd.txt
Normal file
@@ -0,0 +1,30 @@
|
||||
Resource Power Manager(RPM)
|
||||
|
||||
RPM is a dedicated hardware engine for managing shared SoC resources,
|
||||
which includes buses, clocks, power rails, etc. The goal of RPM is
|
||||
to achieve the maximum power savings while satisfying the SoC's
|
||||
operational and performance requirements. RPM accepts resource
|
||||
requests from multiple RPM masters. It arbitrates and aggregates the
|
||||
requests, and configures the shared resources. The RPM masters are
|
||||
the application processor, the modem processor, as well as hardware
|
||||
accelerators. The RPM driver communicates with the hardware engine using
|
||||
SMD.
|
||||
|
||||
The devicetree representation of the SPM block should be:
|
||||
|
||||
Required properties
|
||||
|
||||
- compatible: "qcom,rpm-smd"
|
||||
- rpm-channel-name: The string corresponding to the channel name of the
|
||||
peripheral subsystem
|
||||
- rpm-channel-type: The interal SMD edge for this subsystem found in
|
||||
<mach/msm_smd.h>
|
||||
|
||||
Example:
|
||||
|
||||
qcom,rpm-smd {
|
||||
compatible = "qcom,rpm-smd"
|
||||
qcom,rpm-channel-name = "rpm_requests";
|
||||
qcom,rpm-channel-type = 15; /* SMD_APPS_RPM */
|
||||
}
|
||||
}
|
||||
66
Documentation/devicetree/bindings/arm/msm/spm-v2.txt
Normal file
66
Documentation/devicetree/bindings/arm/msm/spm-v2.txt
Normal file
@@ -0,0 +1,66 @@
|
||||
* MSM Subsystem Power Manager (spm-v2)
|
||||
|
||||
S4 generation of MSMs have SPM hardware blocks to control the Application
|
||||
Processor Sub-System power. These SPM blocks run individual state machine
|
||||
to determine what the core (L2 or Krait/Scorpion) would do when the WFI
|
||||
instruction is executed by the core. The SAW hardware block handles SPM and
|
||||
AVS functionality for the cores.
|
||||
|
||||
The devicetree representation of the SPM block should be:
|
||||
|
||||
Required properties
|
||||
|
||||
- compatible: "qcom,spm-v2"
|
||||
- reg: The physical address and the size of the SPM's memory mapped registers
|
||||
- qcom, core-id: The core id the SPM block is attached to.
|
||||
{0..n} for cores {0..n}
|
||||
{0xffff} for L2
|
||||
- qcom,saw2-ver-reg: The location of the version register
|
||||
- qcom,saw2-cfg: SAW2 configuration register
|
||||
- qcom,saw2-avs-ctl: The AVS control register
|
||||
- qcom,saw2-avs-hysterisis: The AVS hysterisis register to delay the AVS
|
||||
controller requests
|
||||
- qcom,saw2-spm-dly: Provides the values for the SPM delay command in the SPM
|
||||
sequence
|
||||
- qcom,saw2-spm-ctl: The SPM control register
|
||||
- qcom,saw2-vctl-timeout-us: The timeout value to wait for voltage to change
|
||||
after sending the voltage command to the PMIC
|
||||
|
||||
Optional properties
|
||||
|
||||
- qcom,saw2-avs-limit: The AVS limit register
|
||||
- qcom,saw2-avs-dly: The AVS delay register is used to specify the delay values
|
||||
between AVS controller requests
|
||||
- qcom,saw2-pmic-dly: The delay values for waiting on PMIC response
|
||||
- qcom,saw2-pmic-data0..7: Specify the pmic data value and the associated FTS
|
||||
index to send the PMIC data to
|
||||
- qcom,saw2-vctl-port: The FTS port used for changing voltage
|
||||
- qcom,saw2-phase-port: The FTS port used for changing the number of phases
|
||||
- qcom,saw2-spm-cmd-wfi: The WFI command sequence
|
||||
- qcom,saw2-spm-cmd-ret: The Retention command sequence
|
||||
- qcom,saw2-spm-cmd-spc: The Standalone PC command sequence
|
||||
- qcom,saw2-spm-cmd-pc: The Power Collapse command sequence
|
||||
|
||||
Example:
|
||||
qcom,spm@f9089000 {
|
||||
compatible = "qcom,spm-v2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xf9089000 0x1000>;
|
||||
qcom,core-id = <0>;
|
||||
qcom,saw2-ver-reg = <0xfd0>;
|
||||
qcom,saw2-cfg = <0x1b>;
|
||||
qcom,saw2-avs-ctl = <0>;
|
||||
qcom,saw2-avs-hysteresis = <0>;
|
||||
qcom,saw2-avs-limit = <0>;
|
||||
qcom,saw2-avs-dly= <0>;
|
||||
qcom,saw2-spm-dly= <0x20000400>;
|
||||
qcom,saw2-spm-ctl = <0x1>;
|
||||
qcom,spm-cmd-wfi = [03 0b 0f];
|
||||
qcom,spm-cmd-spc = [00 20 50 80 60 70 10 92
|
||||
a0 b0 03 68 70 3b 92 a0 b0
|
||||
82 2b 50 10 30 02 22 30 0f];
|
||||
qcom,spm-cmd-pc = [00 20 10 92 a0 b0 07 3b 92
|
||||
a0 b0 82 10 30 02 22 30 0f];
|
||||
};
|
||||
|
||||
15
Documentation/devicetree/bindings/media/video/msm-vidc.txt
Normal file
15
Documentation/devicetree/bindings/media/video/msm-vidc.txt
Normal file
@@ -0,0 +1,15 @@
|
||||
* Qualcomm MSM VIDC
|
||||
|
||||
Required properties:
|
||||
- compatible : one of:
|
||||
- "qcom,msm-vidc"
|
||||
- reg : offset and length of the register set for the device.
|
||||
- interrupts : should contain the vidc interrupt.
|
||||
|
||||
Example:
|
||||
|
||||
qcom,vidc@fdc00000 {
|
||||
compatible = "qcom,msm-vidc";
|
||||
reg = <0xfdc00000 0xff000>;
|
||||
interrupts = <0 44 0>;
|
||||
};
|
||||
41
Documentation/devicetree/bindings/mmc/msm_sdcc.txt
Normal file
41
Documentation/devicetree/bindings/mmc/msm_sdcc.txt
Normal file
@@ -0,0 +1,41 @@
|
||||
Qualcomm Secure Digital Card Controller (SDCC)
|
||||
|
||||
Secure Digital Card Controller provides host interface to
|
||||
SD/MMC/SDIO cards.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "qcom,msm-sdcc"
|
||||
- reg : should contain SDCC, BAM register map.
|
||||
- interrupts : should contain SDCC core interrupt.
|
||||
- qcom,sdcc-clk-rates : specifies supported SDCC clock frequencies, Units - Hz.
|
||||
- qcom,sdcc-sup-voltages: specifies supported voltage ranges for card. Should always be
|
||||
specified in pairs (min, max), Units - mV.
|
||||
|
||||
Optional Properties:
|
||||
- cell-index - defines slot ID.
|
||||
- qcom,sdcc-bus-width - defines the bus I/O width that controller supports.
|
||||
- qcom,sdcc-wp-gpio - defines write protect switch gpio.
|
||||
- qcom,sdcc-wp-polarity - specifies the polarity of wp switch.
|
||||
- qcom,sdcc-cd-gpio - defines card detect gpio number.
|
||||
- qcom,sdcc-cd-polarity - specifies the polarity of cd gpio.
|
||||
- qcom,sdcc-nonremovable - specifies whether the card in slot is
|
||||
hot pluggable or hard wired.
|
||||
- qcom,sdcc-disable_cmd23 - disable sending CMD23 to card when controller can't support it.
|
||||
- qcom,sdcc-hs200 - enable eMMC4.5 HS200 bus speed mode
|
||||
|
||||
Example:
|
||||
|
||||
qcom,sdcc@f9600000 {
|
||||
/* SDC1 used as eMMC slot */
|
||||
cell-index = <1>;
|
||||
compatible = "qcom,msm-sdcc";
|
||||
reg = <0xf9600000 0x800 // SDCC register interface
|
||||
0xf9600800 0x1800 // DML register interface
|
||||
0xf9602000 0x2000> // BAM register interface
|
||||
|
||||
interrupts = <123>;
|
||||
qcom,sdcc-clk-rates = <400000 24000000 48000000>;
|
||||
qcom,sdcc-sup-voltages = <2700 3300>;
|
||||
qcom,sdcc-bus-width = <8>; //8-bit wide
|
||||
qcom,sdcc-nonremovable;
|
||||
};
|
||||
27
Documentation/devicetree/bindings/pil/pil-mba.txt
Normal file
27
Documentation/devicetree/bindings/pil/pil-mba.txt
Normal file
@@ -0,0 +1,27 @@
|
||||
Qualcomm Modem Boot Authenticator Peripheral Image Loader
|
||||
|
||||
pil-mba is a peripheral image loader (PIL) driver. It is used for loading
|
||||
modem images using the self-authenticating hardware and software features
|
||||
of the Modem Boot Authenticator.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "qcom,pil-mba"
|
||||
- reg: Two pairs of physical base addresses and sizes. The
|
||||
first corresponds to the Relay Message Buffer (RMB)
|
||||
register base. The second specifies the address at which
|
||||
the primary modem image metadata should be stored.
|
||||
- qcom,firmware-name: Base name of the firmware image. Ex. "modem"
|
||||
|
||||
Optional properties:
|
||||
- qcom,depends-on: firmware-name of a prerequisite image that must already
|
||||
be running.
|
||||
|
||||
Example:
|
||||
qcom,mba@fc820000 {
|
||||
compatible = "qcom,pil-mba";
|
||||
reg = <0xfc820000 0x0020>,
|
||||
<0x0d1f0000 0x4000>;
|
||||
|
||||
qcom,firmware-name = "modem";
|
||||
qcom,depends-on = "mba";
|
||||
};
|
||||
25
Documentation/devicetree/bindings/pil/pil-pronto.txt
Normal file
25
Documentation/devicetree/bindings/pil/pil-pronto.txt
Normal file
@@ -0,0 +1,25 @@
|
||||
* Qualcomm WCNSS Pronto Peripheral Image Loader
|
||||
|
||||
pil-pronto is a peripheral image loading (PIL) driver. It is used for loading
|
||||
Pronto firmware images for wireless connectivity subsystems into memory and
|
||||
preparing the subsystem's processor to execute code. It is also used for
|
||||
shutting down the processor when it's not needed.
|
||||
|
||||
Required properties:
|
||||
- compatible: "pil-pronto"
|
||||
- reg: offset and length of the register set for the device. The first pair
|
||||
corresponds to PRONTO_PMU, the second pair corresponds to CLK_CTL_WCNSS
|
||||
the third pair corresponds to WCNSS_HALTREQ.
|
||||
- vdd_pronto_pll-supply: regulator to supply pronto pll.
|
||||
- qcom,firmware-name: Base name of the firmware image. Ex. "wcnss"
|
||||
|
||||
Example:
|
||||
qcom,pronto@fb21b000 {
|
||||
compatible = "qcom,pil-pronto";
|
||||
reg = <0xfb21b000 0x3000>,
|
||||
<0xfc401700 0x4>,
|
||||
<0xfd485300 0xc>;
|
||||
vdd_pronto_pll-supply = <&pm8941_l12>;
|
||||
|
||||
qcom,firmware-name = "wcnss";
|
||||
};
|
||||
22
Documentation/devicetree/bindings/pil/pil-q6v5-lpass.txt
Normal file
22
Documentation/devicetree/bindings/pil/pil-q6v5-lpass.txt
Normal file
@@ -0,0 +1,22 @@
|
||||
Qualcomm LPASS QDSP6v5 Peripheral Image Loader
|
||||
|
||||
pil-qdsp6v5-lpass is a peripheral image loader (PIL) driver. It is used for
|
||||
loading QDSP6v5 (Hexagon) firmware images for Low Power Audio Subsystems
|
||||
into memory and preparing the subsystem's processor to execute code. It's
|
||||
also responsible for shutting down the processor when it's not needed.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "qcom,pil-q6v5-lpass"
|
||||
- reg: Two pairs of physical base addresses and region sizes
|
||||
of memory mapped registers. The first region corresponds
|
||||
to QDSP6SS_PUB, and the second to LPASS_HALTREQ.
|
||||
- qcom,firmware-name: Base name of the firmware image. Ex. "lpass"
|
||||
|
||||
Example:
|
||||
qcom,lpass@fe200000 {
|
||||
compatible = "qcom,pil-q6v5-lpass";
|
||||
reg = <0xfe200000 0x00100>,
|
||||
<0xfd485100 0x00010>;
|
||||
|
||||
qcom,firmware-name = "lpass";
|
||||
};
|
||||
32
Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
Normal file
32
Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
Normal file
@@ -0,0 +1,32 @@
|
||||
Qualcomm MSS QDSP6v5 Peripheral Image Loader
|
||||
|
||||
pil-qdsp6v5-mss is a peripheral image loader (PIL) driver. It is used for
|
||||
loading QDSP6v5 (Hexagon) firmware images for modem subsystems into memory and
|
||||
preparing the subsystem's processor to execute code. It's also responsible for
|
||||
shutting down the processor when it's not needed.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "qcom,pil-q6v5-mss"
|
||||
- reg: Four pairs of physical base addresses and region sizes of
|
||||
memory mapped registers. The first region corresponds to
|
||||
QDSP6SS_PUB, the second to the bus port halt register
|
||||
base, the third to the MSS_RELAY_MSG_BUFFER base, and the
|
||||
fourth to the MSS_RESTART register.
|
||||
- vdd_mss-supply: Reference to the regulator that supplies the processor.
|
||||
- qcom,firmware-name: Base name of the firmware image. Ex. "mdsp"
|
||||
- qcom,pil-self-auth: <0> if the hardware does not require self-authenticating
|
||||
images and self-authentication is not desired;
|
||||
<1> if the hardware requires self-authenticating images.
|
||||
|
||||
Example:
|
||||
qcom,mss@fc880000 {
|
||||
compatible = "qcom,pil-q6v5-mss";
|
||||
reg = <0xfc880000 0x100>,
|
||||
<0xfd485000 0x400>,
|
||||
<0xfc820000 0x020>,
|
||||
<0xfc401680 0x004>;
|
||||
vdd_mss-supply = <&pm8841_s3>;
|
||||
|
||||
qcom,firmware-name = "mba";
|
||||
qcom,pil-self-auth = <1>;
|
||||
};
|
||||
@@ -0,0 +1,21 @@
|
||||
Qualcomm Global Distributed Switch Controller (GDSC) Regulator Driver
|
||||
|
||||
The GDSC driver, implemented under the regulator framework, is responsible for
|
||||
safely collapsing and restoring power to peripheral cores on chipsets like
|
||||
msm-copper for power savings.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "qcom,gdsc"
|
||||
- regulator-name: A string used as a descriptive name for regulator outputs
|
||||
- reg: The address of the GDSCR register
|
||||
|
||||
Optional properties:
|
||||
- parent-supply: phandle to the parent supply/regulator node
|
||||
|
||||
Example:
|
||||
gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
|
||||
compatible = "qcom,gdsc";
|
||||
regulator-name = "gdsc_oxili_gx";
|
||||
parent-supply = <&pm8841_s4>;
|
||||
reg = <0xfd8c4024 0x4>;
|
||||
};
|
||||
@@ -35,16 +35,16 @@ Optional properties :
|
||||
- qcom,hsusb-otg-pmic-id-irq: ID, routed to PMIC IRQ number
|
||||
|
||||
Example HSUSB OTG controller device node :
|
||||
usb@F9690000 {
|
||||
usb@f9690000 {
|
||||
compatible = "qcom,hsusb-otg";
|
||||
reg = <0xF9690000 0x400>;
|
||||
reg = <0xf9690000 0x400>;
|
||||
interrupts = <134>;
|
||||
|
||||
qcom,hsusb-otg-phy-type = <2>;
|
||||
qcom,hsusb-otg-mode = <1>;
|
||||
qcom,hsusb-otg-otg-control = <1>;
|
||||
qcom,hsusb-otg-default-mode = <2>;
|
||||
qcom,hsusb-otg-phy-init-seq = <0x01 0x90 0xFFFFFFFF>;
|
||||
qcom,hsusb-otg-phy-init-seq = <0x01 0x90 0xffffffff>;
|
||||
qcom,hsusb-otg-power-budget = <500>;
|
||||
qcom,hsusb-otg-pclk-src-name = "dfab_usb_clk";
|
||||
qcom,hsusb-otg-pmic-id-irq = <47>
|
||||
|
||||
@@ -2522,6 +2522,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
||||
1: Fast pin select (default)
|
||||
2: ATC IRMode
|
||||
|
||||
snddev_icodec.msm_codec_i2s_slave_mode= [ARM-MSM]
|
||||
1, codec is I2S master
|
||||
0, MSM is I2S master (default)
|
||||
|
||||
softlockup_panic=
|
||||
[KNL] Should the soft-lockup detector generate panics.
|
||||
Format: <integer>
|
||||
|
||||
187
Documentation/sound/alsa/compress/snd_compress_data.txt
Normal file
187
Documentation/sound/alsa/compress/snd_compress_data.txt
Normal file
@@ -0,0 +1,187 @@
|
||||
snd_compress_data.txt
|
||||
=====================
|
||||
Pierre-Louis.Bossart <pierre-louis.bossart@linux.intel.com>
|
||||
Vinod Koul <vinod.koul@linux.intel.com>
|
||||
|
||||
Overview
|
||||
|
||||
Since its early days, the ALSA API was defined with PCM support or
|
||||
constant bitrates payloads such as IEC61937 in mind. Arguments and
|
||||
returned values in frames are the norm, making it a challenge to
|
||||
extend the existing API to compressed data streams.
|
||||
|
||||
In recent years, audio digital signal processors (DSP) were integrated
|
||||
in system-on-chip designs, and DSPs are also integrated in audio
|
||||
codecs. Processing compressed data on such DSPs results in a dramatic
|
||||
reduction of power consumption compared to host-based
|
||||
processing. Support for such hardware has not been very good in Linux,
|
||||
mostly because of a lack of a generic API available in the mainline
|
||||
kernel.
|
||||
|
||||
Rather than requiring a compability break with an API change of the
|
||||
ALSA PCM interface, a new 'Compressed Data' API is introduced to
|
||||
provide a control and data-streaming interface for audio DSPs.
|
||||
|
||||
The design of this API was inspired by the 2-year experience with the
|
||||
Intel Moorestown SOC, with many corrections required to upstream the
|
||||
API in the mainline kernel instead of the staging tree and make it
|
||||
usable by others.
|
||||
|
||||
Requirements
|
||||
|
||||
The main requirements are:
|
||||
|
||||
- separation between byte counts and time. Compressed formats may have
|
||||
a header per file, per frame, or no header at all. The payload size
|
||||
may vary from frame-to-frame. As a result, it is not possible to
|
||||
estimate reliably the duration of audio buffers when handling
|
||||
compressed data. Dedicated mechanisms are required to allow for
|
||||
reliable audio-video synchronization, which requires precise
|
||||
reporting of the number of samples rendered at any given time.
|
||||
|
||||
- Handling of multiple formats. PCM data only requires a specification
|
||||
of the sampling rate, number of channels and bits per sample. In
|
||||
contrast, compressed data comes in a variety of formats. Audio DSPs
|
||||
may also provide support for a limited number of audio encoders and
|
||||
decoders embedded in firmware, or may support more choices through
|
||||
dynamic download of libraries.
|
||||
|
||||
- Focus on main formats. This API provides support for the most
|
||||
popular formats used for audio and video capture and playback. It is
|
||||
likely that as audio compression technology advances, new formats
|
||||
will be added.
|
||||
|
||||
- Handling of multiple configurations. Even for a given format like
|
||||
AAC, some implementations may support AAC multichannel but HE-AAC
|
||||
stereo. Likewise WMA10 level M3 may require too much memory and cpu
|
||||
cycles. The new API needs to provide a generic way of listing these
|
||||
formats.
|
||||
|
||||
- Rendering/Grabbing only. This API does not provide any means of
|
||||
hardware acceleration, where PCM samples are provided back to
|
||||
user-space for additional processing. This API focuses instead on
|
||||
streaming compressed data to a DSP, with the assumption that the
|
||||
decoded samples are routed to a physical output or logical back-end.
|
||||
|
||||
- Complexity hiding. Existing user-space multimedia frameworks all
|
||||
have existing enums/structures for each compressed format. This new
|
||||
API assumes the existence of a platform-specific compatibility layer
|
||||
to expose, translate and make use of the capabilities of the audio
|
||||
DSP, eg. Android HAL or PulseAudio sinks. By construction, regular
|
||||
applications are not supposed to make use of this API.
|
||||
|
||||
|
||||
Design
|
||||
|
||||
The new API shares a number of concepts with with the PCM API for flow
|
||||
control. Start, pause, resume, drain and stop commands have the same
|
||||
semantics no matter what the content is.
|
||||
|
||||
The concept of memory ring buffer divided in a set of fragments is
|
||||
borrowed from the ALSA PCM API. However, only sizes in bytes can be
|
||||
specified.
|
||||
|
||||
Seeks/trick modes are assumed to be handled by the host.
|
||||
|
||||
The notion of rewinds/forwards is not supported. Data committed to the
|
||||
ring buffer cannot be invalidated, except when dropping all buffers.
|
||||
|
||||
The Compressed Data API does not make any assumptions on how the data
|
||||
is transmitted to the audio DSP. DMA transfers from main memory to an
|
||||
embedded audio cluster or to a SPI interface for external DSPs are
|
||||
possible. As in the ALSA PCM case, a core set of routines is exposed;
|
||||
each driver implementer will have to write support for a set of
|
||||
mandatory routines and possibly make use of optional ones.
|
||||
|
||||
The main additions are
|
||||
|
||||
- get_codecs
|
||||
This routine returns the list of audio formats supported. Querying the
|
||||
codecs on a capture stream will return encoders, decoders will be
|
||||
listed for playback streams.
|
||||
|
||||
- get_codec_caps
|
||||
For each codec, this routine returns a list of capabilities. The
|
||||
intent is to make sure all the capabilities correspond to valid
|
||||
settings, and to minimize the risks of configuration failures. For
|
||||
example, for a complex codec such as AAC, the number of channels
|
||||
supported may depend on a specific profile. If the capabilities were
|
||||
exposed with a single descriptor, it may happen that a specific
|
||||
combination of profiles/channels/formats may not be
|
||||
supported. Likewise, embedded DSPs have limited memory and cpu cycles,
|
||||
it is likely that some implementations make the list of capabilities
|
||||
dynamic and dependent on existing workloads.
|
||||
|
||||
- set_params
|
||||
This routine sets the configuration chosen for a specific codec. The
|
||||
most important field in the parameters is the codec type; in most
|
||||
cases decoders will ignore other fields, while encoders will strictly
|
||||
comply to the settings
|
||||
|
||||
- get_params
|
||||
This routines returns the actual settings used by the DSP. Changes to
|
||||
the settings should remain the exception.
|
||||
|
||||
- get_timestamp
|
||||
The timestamp becomes a multiple field structure. It lists the number
|
||||
of bytes transferred, the number of samples processed and the number
|
||||
of samples rendered/grabbed. All these values can be used to determine
|
||||
the avarage bitrate, figure out if the ring buffer needs to be
|
||||
refilled or the delay due to decoding/encoding/io on the DSP.
|
||||
|
||||
Note that the list of codecs/profiles/modes was derived from the
|
||||
OpenMAX AL specification instead of reinventing the wheel.
|
||||
Modifications include:
|
||||
- Addition of FLAC and IEC formats
|
||||
- Merge of encoder/decoder capabilities
|
||||
- Profiles/modes listed as bitmasks to make descriptors more compact
|
||||
- Addition of set_params for decoders (missing in OpenMAX AL)
|
||||
- Addition of AMR/AMR-WB encoding modes (missing in OpenMAX AL)
|
||||
- Addition of format information for WMA
|
||||
- Addition of encoding options when required (derived from OpenMAX IL)
|
||||
- Addition of rateControlSupported (missing in OpenMAX AL)
|
||||
|
||||
Not supported:
|
||||
|
||||
- Support for VoIP/circuit-switched calls is not the target of this
|
||||
API. Support for dynamic bit-rate changes would require a tight
|
||||
coupling between the DSP and the host stack, limiting power savings.
|
||||
|
||||
- Packet-loss concealment is not supported. This would require an
|
||||
additional interface to let the decoder synthesize data when frames
|
||||
are lost during transmission. This may be added in the future.
|
||||
|
||||
- Volume control/routing is not handled by this API. Devices exposing a
|
||||
compressed data interface will be considered as regular ALSA devices
|
||||
|
||||
Instead,
|
||||
offloaded processing will be considered as regular ALSA devices;
|
||||
volume changes and routing information will be provided with regular
|
||||
ALSA kcontrols.
|
||||
|
||||
- Embedded audio effects. Such effects should be enabled in the same
|
||||
manner, no matter if the input was PCM or compressed.
|
||||
|
||||
- multichannel IEC encoding. Unclear if this is required.
|
||||
|
||||
- Encoding/decoding acceleration is not supported as mentioned
|
||||
above. It is possible to route the output of a decoder to a capture
|
||||
stream, or even implement transcoding capabilities. This routing
|
||||
would be enabled with ALSA kcontrols.
|
||||
|
||||
- Audio policy/resource management. This API does not provide any
|
||||
hooks to query the utilization of the audio DSP, nor any premption
|
||||
mechanisms.
|
||||
|
||||
- No notion of underun/overrun. Since the bytes written are compressed
|
||||
in nature and data written/read doesn't translate directly to
|
||||
rendered output in time, this does not deal with underrun/overun and
|
||||
maybe dealt in user-library
|
||||
|
||||
Credits:
|
||||
- Mark Brown and Liam Girdwood for discussions on the need for this API
|
||||
- Harsha Priya for her work on intel_sst compressed API
|
||||
- Rakesh Ughreja for valuable feedback
|
||||
- Sing Nallasellan, Sikkandar Madar and Prasanna Samaga for
|
||||
demonstrating and quantifying the benefits of audio offload on a
|
||||
real platform.
|
||||
@@ -27,7 +27,7 @@ config ARM
|
||||
select HAVE_PERF_EVENTS
|
||||
select PERF_USE_VMALLOC
|
||||
select HAVE_REGS_AND_STACK_ACCESS_API
|
||||
select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
|
||||
#select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
|
||||
select HAVE_C_RECORDMCOUNT
|
||||
select HAVE_GENERIC_HARDIRQS
|
||||
select GENERIC_IRQ_SHOW
|
||||
@@ -741,8 +741,14 @@ config ARCH_MSM
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select CLKDEV_LOOKUP
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select GENERIC_GPIO
|
||||
select GENERIC_TIME
|
||||
select GENERIC_ALLOCATOR
|
||||
select HAVE_SCHED_CLOCK
|
||||
select HAVE_CLK_PREPARE
|
||||
select NEED_MACH_MEMORY_H
|
||||
select NEED_MACH_IO_H
|
||||
help
|
||||
Support for Qualcomm MSM/QSD based systems. This runs on the
|
||||
apps processor of the MSM/QSD and depends on a shared memory
|
||||
@@ -1638,7 +1644,7 @@ config LOCAL_TIMERS
|
||||
bool "Use local timer interrupts"
|
||||
depends on SMP
|
||||
default y
|
||||
select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
|
||||
select HAVE_ARM_TWD if (!MSM_SMP && !EXYNOS4_MCT)
|
||||
help
|
||||
Enable support for local timers on SMP platforms, rather then the
|
||||
legacy IPI broadcast method. Local timers allows the system
|
||||
@@ -1732,7 +1738,7 @@ config AEABI
|
||||
config OABI_COMPAT
|
||||
bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
|
||||
depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
|
||||
default y if !SMP
|
||||
default y
|
||||
help
|
||||
This option preserves the old syscall interface along with the
|
||||
new (ARM EABI) one. It also provides a compatibility layer to
|
||||
@@ -2377,7 +2383,7 @@ menu "Power management options"
|
||||
source "kernel/power/Kconfig"
|
||||
|
||||
config ARCH_SUSPEND_POSSIBLE
|
||||
depends on !ARCH_S5PC100
|
||||
depends on !ARCH_S5PC100 && !ARCH_FSM9XXX
|
||||
depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
|
||||
CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
|
||||
def_bool y
|
||||
|
||||
@@ -208,43 +208,6 @@ choice
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX6Q UART4.
|
||||
|
||||
config DEBUG_MSM_UART1
|
||||
bool "Kernel low-level debugging messages via MSM UART1"
|
||||
depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the first serial port on MSM devices.
|
||||
|
||||
config DEBUG_MSM_UART2
|
||||
bool "Kernel low-level debugging messages via MSM UART2"
|
||||
depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the second serial port on MSM devices.
|
||||
|
||||
config DEBUG_MSM_UART3
|
||||
bool "Kernel low-level debugging messages via MSM UART3"
|
||||
depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the third serial port on MSM devices.
|
||||
|
||||
config DEBUG_MSM8660_UART
|
||||
bool "Kernel low-level debugging messages via MSM 8660 UART"
|
||||
depends on ARCH_MSM8X60
|
||||
select MSM_HAS_DEBUG_UART_HS
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the serial port on MSM 8660 devices.
|
||||
|
||||
config DEBUG_MSM8960_UART
|
||||
bool "Kernel low-level debugging messages via MSM 8960 UART"
|
||||
depends on ARCH_MSM8960
|
||||
select MSM_HAS_DEBUG_UART_HS
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the serial port on MSM 8960 devices.
|
||||
|
||||
config DEBUG_REALVIEW_STD_PORT
|
||||
bool "RealView Default UART"
|
||||
depends on ARCH_REALVIEW
|
||||
|
||||
@@ -128,9 +128,6 @@ textofs-$(CONFIG_PM_H1940) := 0x00108000
|
||||
ifeq ($(CONFIG_ARCH_SA1100),y)
|
||||
textofs-$(CONFIG_SA1111) := 0x00208000
|
||||
endif
|
||||
textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000
|
||||
textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
|
||||
textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
|
||||
|
||||
# Machine directory name. This list is sorted alphanumerically
|
||||
# by CONFIG_* macro name.
|
||||
|
||||
58
arch/arm/boot/dts/msm-gdsc.dtsi
Normal file
58
arch/arm/boot/dts/msm-gdsc.dtsi
Normal file
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
gdsc_venus: qcom,gdsc@fd8c1024 {
|
||||
compatible = "qcom,gdsc";
|
||||
regulator-name = "gdsc_venus";
|
||||
reg = <0xfd8c1024 0x4>;
|
||||
};
|
||||
|
||||
gdsc_mdss: qcom,gdsc@fd8c2304 {
|
||||
compatible = "qcom,gdsc";
|
||||
regulator-name = "gdsc_mdss";
|
||||
reg = <0xfd8c2304 0x4>;
|
||||
};
|
||||
|
||||
gdsc_jpeg: qcom,gdsc@fd8c35a4 {
|
||||
compatible = "qcom,gdsc";
|
||||
regulator-name = "gdsc_jpeg";
|
||||
reg = <0xfd8c35a4 0x4>;
|
||||
};
|
||||
|
||||
gdsc_vfe: qcom,gdsc@fd8c36a4 {
|
||||
compatible = "qcom,gdsc";
|
||||
regulator-name = "gdsc_vfe";
|
||||
reg = <0xfd8c36a4 0x4>;
|
||||
};
|
||||
|
||||
gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
|
||||
compatible = "qcom,gdsc";
|
||||
regulator-name = "gdsc_oxili_gx";
|
||||
reg = <0xfd8c4024 0x4>;
|
||||
};
|
||||
|
||||
gdsc_oxili_cx: qcom,gdsc@fd8c4034 {
|
||||
compatible = "qcom,gdsc";
|
||||
regulator-name = "gdsc_oxili_cx";
|
||||
reg = <0xfd8c4034 0x4>;
|
||||
};
|
||||
|
||||
gdsc_usb_hsic: qcom,gdsc@fc400404 {
|
||||
compatible = "qcom,gdsc";
|
||||
regulator-name = "gdsc_usb_hsic";
|
||||
reg = <0xfc400404 0x4>;
|
||||
};
|
||||
};
|
||||
187
arch/arm/boot/dts/msm-pm8841.dtsi
Normal file
187
arch/arm/boot/dts/msm-pm8841.dtsi
Normal file
@@ -0,0 +1,187 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/ {
|
||||
qcom,spmi@fc4c0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
|
||||
qcom,pm8841@5 {
|
||||
spmi-slave-container;
|
||||
reg = <0x5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
regulator@1400 {
|
||||
regulator-name = "8841_s1";
|
||||
spmi-dev-container;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
reg = <0x1400 0x300>;
|
||||
status = "disabled";
|
||||
|
||||
qcom,ctl@1400 {
|
||||
reg = <0x1400 0x100>;
|
||||
};
|
||||
qcom,ps@1500 {
|
||||
reg = <0x1500 0x100>;
|
||||
};
|
||||
qcom,freq@1600 {
|
||||
reg = <0x1600 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator@1700 {
|
||||
regulator-name = "8841_s2";
|
||||
spmi-dev-container;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
reg = <0x1700 0x300>;
|
||||
status = "disabled";
|
||||
|
||||
qcom,ctl@1700 {
|
||||
reg = <0x1700 0x100>;
|
||||
};
|
||||
qcom,ps@1800 {
|
||||
reg = <0x1800 0x100>;
|
||||
};
|
||||
qcom,freq@1900 {
|
||||
reg = <0x1900 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator@1a00 {
|
||||
regulator-name = "8841_s3";
|
||||
spmi-dev-container;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
reg = <0x1a00 0x300>;
|
||||
status = "disabled";
|
||||
|
||||
qcom,ctl@1a00 {
|
||||
reg = <0x1a00 0x100>;
|
||||
};
|
||||
qcom,ps@1b00 {
|
||||
reg = <0x1b00 0x100>;
|
||||
};
|
||||
qcom,freq@1c00 {
|
||||
reg = <0x1c00 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator@1d00 {
|
||||
regulator-name = "8841_s4";
|
||||
spmi-dev-container;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
reg = <0x1d00 0x300>;
|
||||
status = "disabled";
|
||||
|
||||
qcom,ctl@1d00 {
|
||||
reg = <0x1d00 0x100>;
|
||||
};
|
||||
qcom,ps@1e00 {
|
||||
reg = <0x1e00 0x100>;
|
||||
};
|
||||
qcom,freq@1f00 {
|
||||
reg = <0x1f00 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator@2000 {
|
||||
regulator-name = "8841_s5";
|
||||
spmi-dev-container;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
reg = <0x2000 0x300>;
|
||||
status = "disabled";
|
||||
|
||||
qcom,ctl@0 {
|
||||
reg = <0x2000 0x100>;
|
||||
};
|
||||
qcom,ps@100 {
|
||||
reg = <0x2100 0x100>;
|
||||
};
|
||||
qcom,freq@200 {
|
||||
reg = <0x2200 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator@2300 {
|
||||
regulator-name = "8841_s6";
|
||||
spmi-dev-container;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
reg = <0x2300 0x300>;
|
||||
status = "disabled";
|
||||
|
||||
qcom,ctl@2300 {
|
||||
reg = <0x2300 0x100>;
|
||||
};
|
||||
qcom,ps@2400 {
|
||||
reg = <0x2400 0x100>;
|
||||
};
|
||||
qcom,freq@2500 {
|
||||
reg = <0x2500 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator@2600 {
|
||||
regulator-name = "8841_s7";
|
||||
spmi-dev-container;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
reg = <0x2600 0x300>;
|
||||
status = "disabled";
|
||||
|
||||
qcom,ctl@2600 {
|
||||
reg = <0x2300 0x100>;
|
||||
};
|
||||
qcom,ps@2700 {
|
||||
reg = <0x2400 0x100>;
|
||||
};
|
||||
qcom,freq@2800 {
|
||||
reg = <0x2500 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator@2900 {
|
||||
regulator-name = "8841_s8";
|
||||
spmi-dev-container;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
reg = <0x2900 0x300>;
|
||||
status = "disabled";
|
||||
|
||||
qcom,ctl@2900 {
|
||||
reg = <0x2900 0x100>;
|
||||
};
|
||||
qcom,ps@2a000 {
|
||||
reg = <0x2a00 0x100>;
|
||||
};
|
||||
qcom,freq@2b00 {
|
||||
reg = <0x2b00 0x100>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
529
arch/arm/boot/dts/msm-pm8941.dtsi
Normal file
529
arch/arm/boot/dts/msm-pm8941.dtsi
Normal file
@@ -0,0 +1,529 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/ {
|
||||
qcom,spmi@fc4c0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
|
||||
qcom,pm8941@0 {
|
||||
spmi-slave-container;
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
pm8941_gpios {
|
||||
spmi-dev-container;
|
||||
compatible = "qcom,qpnp-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
gpio@c000 {
|
||||
reg = <0xc000 0x100>;
|
||||
qcom,gpio-num = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@c100 {
|
||||
reg = <0xc100 0x100>;
|
||||
qcom,gpio-num = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@c200 {
|
||||
reg = <0xc200 0x100>;
|
||||
qcom,gpio-num = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@c300 {
|
||||
reg = <0xc300 0x100>;
|
||||
qcom,gpio-num = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@c400 {
|
||||
reg = <0xc400 0x100>;
|
||||
qcom,gpio-num = <5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@c500 {
|
||||
reg = <0xc500 0x100>;
|
||||
qcom,gpio-num = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@c600 {
|
||||
reg = <0xc600 0x100>;
|
||||
qcom,gpio-num = <7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@c700 {
|
||||
reg = <0xc700 0x100>;
|
||||
qcom,gpio-num = <8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@c800 {
|
||||
reg = <0xc800 0x100>;
|
||||
qcom,gpio-num = <9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@c900 {
|
||||
reg = <0xc900 0x100>;
|
||||
qcom,gpio-num = <10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@ca00 {
|
||||
reg = <0xca00 0x100>;
|
||||
qcom,gpio-num = <11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@cb00 {
|
||||
reg = <0xcb00 0x100>;
|
||||
qcom,gpio-num = <12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@cc00 {
|
||||
reg = <0xcc00 0x100>;
|
||||
qcom,gpio-num = <13>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@cd00 {
|
||||
reg = <0xcd00 0x100>;
|
||||
qcom,gpio-num = <14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@ce00 {
|
||||
reg = <0xce00 0x100>;
|
||||
qcom,gpio-num = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@cf00 {
|
||||
reg = <0xcf00 0x100>;
|
||||
qcom,gpio-num = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@d000 {
|
||||
reg = <0xd000 0x100>;
|
||||
qcom,gpio-num = <17>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@d100 {
|
||||
reg = <0xd100 0x100>;
|
||||
qcom,gpio-num = <18>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@d200 {
|
||||
reg = <0xd200 0x100>;
|
||||
qcom,gpio-num = <19>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@d300 {
|
||||
reg = <0xd300 0x100>;
|
||||
qcom,gpio-num = <20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@d400 {
|
||||
reg = <0xd400 0x100>;
|
||||
qcom,gpio-num = <21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@d500 {
|
||||
reg = <0xd500 0x100>;
|
||||
qcom,gpio-num = <22>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@d600 {
|
||||
reg = <0xd600 0x100>;
|
||||
qcom,gpio-num = <23>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@d700 {
|
||||
reg = <0xd700 0x100>;
|
||||
qcom,gpio-num = <24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@d800 {
|
||||
reg = <0xd800 0x100>;
|
||||
qcom,gpio-num = <25>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@d900 {
|
||||
reg = <0xd900 0x100>;
|
||||
qcom,gpio-num = <26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@da00 {
|
||||
reg = <0xda00 0x100>;
|
||||
qcom,gpio-num = <27>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@db00 {
|
||||
reg = <0xdb00 0x100>;
|
||||
qcom,gpio-num = <28>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@dc00 {
|
||||
reg = <0xdc00 0x100>;
|
||||
qcom,gpio-num = <29>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@dd00 {
|
||||
reg = <0xdd00 0x100>;
|
||||
qcom,gpio-num = <30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@de00 {
|
||||
reg = <0xde00 0x100>;
|
||||
qcom,gpio-num = <31>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@df00 {
|
||||
reg = <0xdf00 0x100>;
|
||||
qcom,gpio-num = <32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@e000 {
|
||||
reg = <0xe000 0x100>;
|
||||
qcom,gpio-num = <33>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@e100 {
|
||||
reg = <0xe100 0x100>;
|
||||
qcom,gpio-num = <34>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@e200 {
|
||||
reg = <0xe200 0x100>;
|
||||
qcom,gpio-num = <35>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio@e300 {
|
||||
reg = <0xe300 0x100>;
|
||||
qcom,gpio-num = <36>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qcom,pm8941@1 {
|
||||
spmi-slave-container;
|
||||
reg = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
regulator@1400 {
|
||||
regulator-name = "8941_s1";
|
||||
spmi-dev-container;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
reg = <0x1400 0x300>;
|
||||
status = "disabled";
|
||||
|
||||
qcom,ctl@1400 {
|
||||
reg = <0x1400 0x100>;
|
||||
};
|
||||
qcom,ps@1500 {
|
||||
reg = <0x1500 0x100>;
|
||||
};
|
||||
qcom,freq@1600 {
|
||||
reg = <0x1600 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator@1700 {
|
||||
regulator-name = "8941_s2";
|
||||
spmi-dev-container;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
reg = <0x1700 0x300>;
|
||||
status = "disabled";
|
||||
|
||||
qcom,ctl@1700 {
|
||||
reg = <0x1700 0x100>;
|
||||
};
|
||||
qcom,ps@1800 {
|
||||
reg = <0x1800 0x100>;
|
||||
};
|
||||
qcom,freq@1900 {
|
||||
reg = <0x1900 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator@1a00 {
|
||||
regulator-name = "8941_s3";
|
||||
spmi-dev-container;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
reg = <0x1400 0x300>;
|
||||
status = "disabled";
|
||||
|
||||
qcom,ctl@1a00 {
|
||||
reg = <0x1a00 0x100>;
|
||||
};
|
||||
qcom,ps@1b00 {
|
||||
reg = <0x1b00 0x100>;
|
||||
};
|
||||
qcom,freq@1c00 {
|
||||
reg = <0x1c00 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator@a000 {
|
||||
regulator-name = "8941_boost";
|
||||
reg = <0xa000 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4000 {
|
||||
regulator-name = "8941_l1";
|
||||
reg = <0x4000 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4100 {
|
||||
regulator-name = "8941_l2";
|
||||
reg = <0x4100 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4200 {
|
||||
regulator-name = "8941_l3";
|
||||
reg = <0x4200 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4300 {
|
||||
regulator-name = "8941_l4";
|
||||
reg = <0x4300 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4400 {
|
||||
regulator-name = "8941_l5";
|
||||
reg = <0x4400 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4500 {
|
||||
regulator-name = "8941_l6";
|
||||
reg = <0x4500 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4600 {
|
||||
regulator-name = "8941_l7";
|
||||
reg = <0x4600 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4700 {
|
||||
regulator-name = "8941_l8";
|
||||
reg = <0x4700 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4800 {
|
||||
regulator-name = "8941_l9";
|
||||
reg = <0x4800 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4900 {
|
||||
regulator-name = "8941_l10";
|
||||
reg = <0x4900 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4a00 {
|
||||
regulator-name = "8941_l11";
|
||||
reg = <0x4a00 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4b00 {
|
||||
regulator-name = "8941_l12";
|
||||
reg = <0x4b00 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4c00 {
|
||||
regulator-name = "8941_l13";
|
||||
reg = <0x4c00 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4d00 {
|
||||
regulator-name = "8941_l14";
|
||||
reg = <0x4d00 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4e00 {
|
||||
regulator-name = "8941_l15";
|
||||
reg = <0x4e00 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@4f00 {
|
||||
regulator-name = "8941_l16";
|
||||
reg = <0x4f00 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@5000 {
|
||||
regulator-name = "8941_l17";
|
||||
reg = <0x5000 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@5100 {
|
||||
regulator-name = "8941_l18";
|
||||
reg = <0x5100 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@5200 {
|
||||
regulator-name = "8941_l19";
|
||||
reg = <0x5200 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@5300 {
|
||||
regulator-name = "8941_l20";
|
||||
reg = <0x5300 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@5400 {
|
||||
regulator-name = "8941_l21";
|
||||
reg = <0x5400 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@5500 {
|
||||
regulator-name = "8941_l22";
|
||||
reg = <0x5500 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@5600 {
|
||||
regulator-name = "8941_l23";
|
||||
reg = <0x5600 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@5700 {
|
||||
regulator-name = "8941_l24";
|
||||
reg = <0x5700 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@8000 {
|
||||
regulator-name = "8941_lvs1";
|
||||
reg = <0x8000 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@8100 {
|
||||
regulator-name = "8941_lvs2";
|
||||
reg = <0x8100 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@8200 {
|
||||
regulator-name = "8941_lvs3";
|
||||
reg = <0x8200 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@8300 {
|
||||
regulator-name = "8941_mvs1";
|
||||
reg = <0x8300 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
regulator@8400 {
|
||||
regulator-name = "8941_mvs2";
|
||||
reg = <0x8400 0x100>;
|
||||
compatible = "qcom,qpnp-regulator";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
587
arch/arm/boot/dts/msm-pm8x41-rpm-regulator.dtsi
Normal file
587
arch/arm/boot/dts/msm-pm8x41-rpm-regulator.dtsi
Normal file
@@ -0,0 +1,587 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/ {
|
||||
qcom,rpm-smd {
|
||||
rpm-regulator-smpb1 {
|
||||
qcom,resource-name = "smpb";
|
||||
qcom,resource-id = <1>;
|
||||
qcom,regulator-type = <1>;
|
||||
qcom,hpm-min-load = <100000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-s1 {
|
||||
regulator-name = "8841_s1";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-smpb2 {
|
||||
qcom,resource-name = "smpb";
|
||||
qcom,resource-id = <2>;
|
||||
qcom,regulator-type = <1>;
|
||||
qcom,hpm-min-load = <100000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-s2 {
|
||||
regulator-name = "8841_s2";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-smpb3 {
|
||||
qcom,resource-name = "smpb";
|
||||
qcom,resource-id = <3>;
|
||||
qcom,regulator-type = <1>;
|
||||
qcom,hpm-min-load = <100000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-s3 {
|
||||
regulator-name = "8841_s3";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-smpb4 {
|
||||
qcom,resource-name = "smpb";
|
||||
qcom,resource-id = <4>;
|
||||
qcom,regulator-type = <1>;
|
||||
qcom,hpm-min-load = <100000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-s4 {
|
||||
regulator-name = "8841_s4";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-smpa1 {
|
||||
qcom,resource-name = "smpa";
|
||||
qcom,resource-id = <1>;
|
||||
qcom,regulator-type = <1>;
|
||||
qcom,hpm-min-load = <100000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-s1 {
|
||||
regulator-name = "8941_s1";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-smpa2 {
|
||||
qcom,resource-name = "smpa";
|
||||
qcom,resource-id = <2>;
|
||||
qcom,regulator-type = <1>;
|
||||
qcom,hpm-min-load = <100000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-s2 {
|
||||
regulator-name = "8941_s2";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-smpa3 {
|
||||
qcom,resource-name = "smpa";
|
||||
qcom,resource-id = <3>;
|
||||
qcom,regulator-type = <1>;
|
||||
qcom,hpm-min-load = <100000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-s3 {
|
||||
regulator-name = "8941_s3";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa1 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <1>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l1 {
|
||||
regulator-name = "8941_l1";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa2 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <2>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l2 {
|
||||
regulator-name = "8941_l2";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa3 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <3>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l3 {
|
||||
regulator-name = "8941_l3";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa4 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <4>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l4 {
|
||||
regulator-name = "8941_l4";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa5 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <5>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l5 {
|
||||
regulator-name = "8941_l5";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa6 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <6>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l6 {
|
||||
regulator-name = "8941_l6";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa7 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <7>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l7 {
|
||||
regulator-name = "8941_l7";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa8 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <8>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l8 {
|
||||
regulator-name = "8941_l8";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa9 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <9>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l9 {
|
||||
regulator-name = "8941_l9";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa10 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <10>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l10 {
|
||||
regulator-name = "8941_l10";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa11 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <11>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l11 {
|
||||
regulator-name = "8941_l11";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa12 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <12>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l12 {
|
||||
regulator-name = "8941_l12";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa13 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <13>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l13 {
|
||||
regulator-name = "8941_l13";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa14 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <14>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l14 {
|
||||
regulator-name = "8941_l14";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa15 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <15>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l15 {
|
||||
regulator-name = "8941_l15";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa16 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <16>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l16 {
|
||||
regulator-name = "8941_l16";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa17 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <17>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l17 {
|
||||
regulator-name = "8941_l17";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa18 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <18>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l18 {
|
||||
regulator-name = "8941_l18";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa19 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <19>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l19 {
|
||||
regulator-name = "8941_l19";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa20 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <20>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l20 {
|
||||
regulator-name = "8941_l20";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa21 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <21>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l21 {
|
||||
regulator-name = "8941_l21";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa22 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <22>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l22 {
|
||||
regulator-name = "8941_l22";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa23 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <23>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l23 {
|
||||
regulator-name = "8941_l23";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-ldoa24 {
|
||||
qcom,resource-name = "ldoa";
|
||||
qcom,resource-id = <24>;
|
||||
qcom,regulator-type = <0>;
|
||||
qcom,hpm-min-load = <10000>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-l24 {
|
||||
regulator-name = "8941_l24";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
/* TODO: find out correct resource names for LVS vs MVS */
|
||||
rpm-regulator-vsa1 {
|
||||
qcom,resource-name = "vsa";
|
||||
qcom,resource-id = <1>;
|
||||
qcom,regulator-type = <2>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-lvs1 {
|
||||
regulator-name = "8941_lvs1";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-vsa2 {
|
||||
qcom,resource-name = "vsa";
|
||||
qcom,resource-id = <2>;
|
||||
qcom,regulator-type = <2>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-lvs2 {
|
||||
regulator-name = "8941_lvs2";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-vsa3 {
|
||||
qcom,resource-name = "vsa";
|
||||
qcom,resource-id = <3>;
|
||||
qcom,regulator-type = <2>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-lvs3 {
|
||||
regulator-name = "8941_lvs3";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-vsa4 {
|
||||
qcom,resource-name = "vsa";
|
||||
qcom,resource-id = <4>;
|
||||
qcom,regulator-type = <2>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-mvs1 {
|
||||
regulator-name = "8941_mvs1";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
|
||||
rpm-regulator-vsa5 {
|
||||
qcom,resource-name = "vsa";
|
||||
qcom,resource-id = <5>;
|
||||
qcom,regulator-type = <2>;
|
||||
compatible = "qcom,rpm-regulator-smd-resource";
|
||||
status = "disabled";
|
||||
|
||||
regulator-mvs2 {
|
||||
regulator-name = "8941_mvs2";
|
||||
qcom,set = <3>;
|
||||
status = "disabled";
|
||||
compatible = "qcom,rpm-regulator-smd";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
47
arch/arm/boot/dts/msm9625.dts
Normal file
47
arch/arm/boot/dts/msm9625.dts
Normal file
@@ -0,0 +1,47 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm MSM 9625";
|
||||
compatible = "qcom,msm9625";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
intc: interrupt-controller@F9000000 {
|
||||
compatible = "qcom,msm-qgic2";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0xF9000000 0x1000>,
|
||||
<0xF9002000 0x1000>;
|
||||
};
|
||||
|
||||
msmgpio: gpio@fd510000 {
|
||||
compatible = "qcom,msm-gpio";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0xfd510000 0x4000>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "qcom,msm-qtimer", "arm,armv7-timer";
|
||||
interrupts = <0 7 0>;
|
||||
clock-frequency = <5000000>;
|
||||
};
|
||||
|
||||
serial@f991f000 {
|
||||
compatible = "qcom,msm-lsuart-v14";
|
||||
reg = <0xf991f000 0x1000>;
|
||||
interrupts = <0 109 0>;
|
||||
};
|
||||
};
|
||||
214
arch/arm/boot/dts/msmcopper-gpio.dtsi
Normal file
214
arch/arm/boot/dts/msmcopper-gpio.dtsi
Normal file
@@ -0,0 +1,214 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/ {
|
||||
qcom,spmi@fc4c0000 {
|
||||
|
||||
qcom,pm8941@0 {
|
||||
|
||||
pm8941_gpios: pm8941_gpios {
|
||||
|
||||
gpio@c000 {
|
||||
qcom,gpio-num = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@c100 {
|
||||
qcom,gpio-num = <2>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@c200 {
|
||||
qcom,gpio-num = <3>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@c300 {
|
||||
qcom,gpio-num = <4>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@c400 {
|
||||
qcom,gpio-num = <5>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@c500 {
|
||||
qcom,gpio-num = <6>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@c600 {
|
||||
qcom,gpio-num = <7>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@c700 {
|
||||
qcom,gpio-num = <8>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@c800 {
|
||||
qcom,gpio-num = <9>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@c900 {
|
||||
qcom,gpio-num = <10>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@ca00 {
|
||||
qcom,gpio-num = <11>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@cb00 {
|
||||
qcom,gpio-num = <12>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@cc00 {
|
||||
qcom,gpio-num = <13>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@cd00 {
|
||||
qcom,gpio-num = <14>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@ce00 {
|
||||
qcom,gpio-num = <15>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@cf00 {
|
||||
qcom,gpio-num = <16>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@d000 {
|
||||
qcom,gpio-num = <17>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@d100 {
|
||||
qcom,gpio-num = <18>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@d200 {
|
||||
qcom,gpio-num = <19>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@d300 {
|
||||
qcom,gpio-num = <20>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@d400 {
|
||||
qcom,gpio-num = <21>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@d500 {
|
||||
qcom,gpio-num = <22>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@d600 {
|
||||
qcom,gpio-num = <23>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@d700 {
|
||||
qcom,gpio-num = <24>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@d800 {
|
||||
qcom,gpio-num = <25>;
|
||||
qcom,out-strength = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@d900 {
|
||||
qcom,gpio-num = <26>;
|
||||
qcom,out-strength = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@da00 {
|
||||
qcom,gpio-num = <27>;
|
||||
qcom,out-strength = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@db00 {
|
||||
qcom,gpio-num = <28>;
|
||||
qcom,out-strength = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@dc00 {
|
||||
qcom,gpio-num = <29>;
|
||||
qcom,out-strength = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@dd00 {
|
||||
qcom,gpio-num = <30>;
|
||||
qcom,out-strength = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@de00 {
|
||||
qcom,gpio-num = <31>;
|
||||
qcom,out-strength = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@df00 {
|
||||
qcom,gpio-num = <32>;
|
||||
qcom,out-strength = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@e000 {
|
||||
qcom,gpio-num = <33>;
|
||||
qcom,out-strength = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@e100 {
|
||||
qcom,gpio-num = <34>;
|
||||
qcom,out-strength = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@e200 {
|
||||
qcom,gpio-num = <35>;
|
||||
qcom,out-strength = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio@e300 {
|
||||
qcom,gpio-num = <36>;
|
||||
qcom,out-strength = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
394
arch/arm/boot/dts/msmcopper-regulator.dtsi
Normal file
394
arch/arm/boot/dts/msmcopper-regulator.dtsi
Normal file
@@ -0,0 +1,394 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/ {
|
||||
qcom,spmi@fc4c0000 {
|
||||
|
||||
qcom,pm8941@1 {
|
||||
|
||||
pm8941_s1: regulator@1400 {
|
||||
regulator-min-microvolt = <1300000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
qcom,enable-time = <500>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
regulator-always-on;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_s2: regulator@1700 {
|
||||
regulator-min-microvolt = <2150000>;
|
||||
regulator-max-microvolt = <2150000>;
|
||||
qcom,enable-time = <500>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_s3: regulator@1a00 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,enable-time = <500>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
regulator-always-on;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_boost: regulator@a000 {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
qcom,enable-time = <500>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l1: regulator@4000 {
|
||||
parent-supply = <&pm8941_s1>;
|
||||
regulator-min-microvolt = <1225000>;
|
||||
regulator-max-microvolt = <1225000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
regulator-always-on;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l2: regulator@4100 {
|
||||
parent-supply = <&pm8941_s3>;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l3: regulator@4200 {
|
||||
parent-supply = <&pm8941_s1>;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l4: regulator@4300 {
|
||||
parent-supply = <&pm8941_s1>;
|
||||
regulator-min-microvolt = <1150000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l5: regulator@4400 {
|
||||
parent-supply = <&pm8941_s2>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l6: regulator@4500 {
|
||||
parent-supply = <&pm8941_s2>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l7: regulator@4600 {
|
||||
parent-supply = <&pm8941_s2>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l8: regulator@4700 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l9: regulator@4800 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l10: regulator@4900 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l11: regulator@4a00 {
|
||||
parent-supply = <&pm8941_s1>;
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l12: regulator@4b00 {
|
||||
parent-supply = <&pm8941_s2>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l13: regulator@4c00 {
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l14: regulator@4d00 {
|
||||
parent-supply = <&pm8941_s2>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l15: regulator@4e00 {
|
||||
parent-supply = <&pm8941_s2>;
|
||||
regulator-min-microvolt = <2050000>;
|
||||
regulator-max-microvolt = <2050000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l16: regulator@4f00 {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l17: regulator@5000 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l18: regulator@5100 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l19: regulator@5200 {
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l20: regulator@5300 {
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l21: regulator@5400 {
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l22: regulator@5500 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l23: regulator@5600 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_l24: regulator@5700 {
|
||||
regulator-min-microvolt = <3075000>;
|
||||
regulator-max-microvolt = <3075000>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_lvs1: regulator@8000 {
|
||||
parent-supply = <&pm8941_s3>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_lvs2: regulator@8100 {
|
||||
parent-supply = <&pm8941_s3>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_lvs3: regulator@8200 {
|
||||
parent-supply = <&pm8941_s3>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_mvs1: regulator@8300 {
|
||||
parent-supply = <&pm8941_boost>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8941_mvs2: regulator@8400 {
|
||||
parent-supply = <&pm8941_boost>;
|
||||
qcom,enable-time = <200>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,pm8841@5 {
|
||||
|
||||
pm8841_s1: regulator@1400 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
qcom,enable-time = <500>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
regulator-always-on;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8841_s2: regulator@1700 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
qcom,enable-time = <500>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
regulator-always-on;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8841_s3: regulator@1a00 {
|
||||
regulator-min-microvolt = <1150000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
qcom,enable-time = <500>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
regulator-always-on;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8841_s4: regulator@1d00 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
qcom,enable-time = <500>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8841_s5: regulator@2000 {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
qcom,enable-time = <500>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
regulator-always-on;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8841_s6: regulator@2300 {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
qcom,enable-time = <500>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8841_s7: regulator@2600 {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
qcom,enable-time = <500>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pm8841_s8: regulator@2900 {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
qcom,enable-time = <500>;
|
||||
qcom,pull-down-enable = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
krait0_vreg: regulator@f9088000 {
|
||||
compatible = "qcom,krait-regulator";
|
||||
regulator-name = "krait0";
|
||||
reg = <0xf9088000 0x1000>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
krait1_vreg: regulator@f9098000 {
|
||||
compatible = "qcom,krait-regulator";
|
||||
regulator-name = "krait1";
|
||||
reg = <0xf9098000 0x1000>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
krait2_vreg: regulator@f90a8000 {
|
||||
compatible = "qcom,krait-regulator";
|
||||
regulator-name = "krait2";
|
||||
reg = <0xf90a8000 0x1000>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
krait3_vreg: regulator@f90b8000 {
|
||||
compatible = "qcom,krait-regulator";
|
||||
regulator-name = "krait3";
|
||||
reg = <0xf90b8000 0x1000>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
};
|
||||
106
arch/arm/boot/dts/msmcopper-rumi.dts
Normal file
106
arch/arm/boot/dts/msmcopper-rumi.dts
Normal file
@@ -0,0 +1,106 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "msmcopper.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm MSM Copper RUMI";
|
||||
compatible = "qcom,msmcopper-rumi", "qcom,msmcopper";
|
||||
|
||||
timer {
|
||||
clock-frequency = <5000000>;
|
||||
};
|
||||
|
||||
serial@f991f000 {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
usb@f9a55000 {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
qcom,sdcc@f9824000 {
|
||||
qcom,sdcc-clk-rates = <400000 19200000>;
|
||||
};
|
||||
|
||||
qcom,sdcc@f98a4000 {
|
||||
qcom,sdcc-clk-rates = <400000 19200000>;
|
||||
};
|
||||
|
||||
qcom,sps@f998000 {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
spi@f9924000 {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
spi@f9923000 {
|
||||
compatible = "qcom,spi-qup-v2";
|
||||
reg = <0xf9923000 0x1000>;
|
||||
interrupts = <0 95 0>;
|
||||
spi-max-frequency = <24000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
gpios = <&msmgpio 3 0>, /* CLK */
|
||||
<&msmgpio 1 0>, /* MISO */
|
||||
<&msmgpio 0 0>; /* MOSI */
|
||||
cs-gpios = <&msmgpio 9 0>;
|
||||
|
||||
ethernet-switch@2 {
|
||||
compatible = "simtec,ks8851";
|
||||
reg = <2>;
|
||||
interrupt-parent = <&msmgpio>;
|
||||
interrupts = <90 0>;
|
||||
spi-max-frequency = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@f9966000 {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
i2c@f9967000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,i2c-qup";
|
||||
reg = <0Xf9967000 0x1000>;
|
||||
reg-names = "qup_phys_addr";
|
||||
interrupts = <0 105 0>;
|
||||
interrupt-names = "qup_err_intr";
|
||||
qcom,i2c-bus-freq = <100000>;
|
||||
qcom,i2c-src-freq = <24000000>;
|
||||
gpios = <&msmgpio 83 0>, /* DAT */
|
||||
<&msmgpio 84 0>; /* CLK */
|
||||
};
|
||||
|
||||
slim@fe12f000 {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
qcom,spmi@fc4c0000 {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
qcom,ssusb@F9200000 {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
qcom,lpass@fe200000 {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
qcom,pronto@fb21b000 {
|
||||
status = "disable";
|
||||
};
|
||||
};
|
||||
20
arch/arm/boot/dts/msmcopper-sim.dts
Normal file
20
arch/arm/boot/dts/msmcopper-sim.dts
Normal file
@@ -0,0 +1,20 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "msmcopper.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm MSM Copper Simulator";
|
||||
compatible = "qcom,msmcopper-sim", "qcom,msmcopper";
|
||||
};
|
||||
339
arch/arm/boot/dts/msmcopper.dtsi
Normal file
339
arch/arm/boot/dts/msmcopper.dtsi
Normal file
@@ -0,0 +1,339 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
/include/ "msmcopper_pm.dtsi"
|
||||
/include/ "msm-pm8x41-rpm-regulator.dtsi"
|
||||
/include/ "msm-pm8841.dtsi"
|
||||
/include/ "msm-pm8941.dtsi"
|
||||
/include/ "msmcopper-regulator.dtsi"
|
||||
/include/ "msmcopper-gpio.dtsi"
|
||||
/include/ "msmcopper-iommu.dtsi"
|
||||
/include/ "msm-gdsc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm MSM Copper";
|
||||
compatible = "qcom,msmcopper";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
intc: interrupt-controller@F9000000 {
|
||||
compatible = "qcom,msm-qgic2";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0xF9000000 0x1000>,
|
||||
<0xF9002000 0x1000>;
|
||||
};
|
||||
|
||||
msmgpio: gpio@fd510000 {
|
||||
compatible = "qcom,msm-gpio";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0xfd510000 0x4000>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "qcom,msm-qtimer", "arm,armv7-timer";
|
||||
interrupts = <1 2 0 1 3 0>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
qcom,vidc@fdc00000 {
|
||||
compatible = "qcom,msm-vidc";
|
||||
reg = <0xfdc00000 0xff000>;
|
||||
interrupts = <0 44 0>;
|
||||
};
|
||||
|
||||
serial@f991f000 {
|
||||
compatible = "qcom,msm-lsuart-v14";
|
||||
reg = <0xf991f000 0x1000>;
|
||||
interrupts = <0 109 0>;
|
||||
};
|
||||
|
||||
serial@f995e000 {
|
||||
compatible = "qcom,msm-lsuart-v14";
|
||||
reg = <0xf995e000 0x1000>;
|
||||
interrupts = <0 114 0>;
|
||||
};
|
||||
|
||||
usb@f9a55000 {
|
||||
compatible = "qcom,hsusb-otg";
|
||||
reg = <0xf9a55000 0x400>;
|
||||
interrupts = <0 134 0>;
|
||||
HSUSB_VDDCX-supply = <&pm8841_s2>;
|
||||
HSUSB_1p8-supply = <&pm8941_l6>;
|
||||
HSUSB_3p3-supply = <&pm8941_l24>;
|
||||
|
||||
qcom,hsusb-otg-phy-type = <2>;
|
||||
qcom,hsusb-otg-mode = <1>;
|
||||
qcom,hsusb-otg-otg-control = <1>;
|
||||
};
|
||||
|
||||
qcom,sdcc@f9824000 {
|
||||
cell-index = <1>;
|
||||
compatible = "qcom,msm-sdcc";
|
||||
reg = <0xf9824000 0x1000>;
|
||||
interrupts = <0 123 0>;
|
||||
|
||||
qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
|
||||
qcom,sdcc-sup-voltages = <2950 2950>;
|
||||
qcom,sdcc-bus-width = <8>;
|
||||
qcom,sdcc-hs200;
|
||||
qcom,sdcc-nonremovable;
|
||||
};
|
||||
|
||||
qcom,sdcc@f98a4000 {
|
||||
cell-index = <2>;
|
||||
compatible = "qcom,msm-sdcc";
|
||||
reg = <0xf98a4000 0x1000>;
|
||||
interrupts = <0 125 0>;
|
||||
|
||||
qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
|
||||
qcom,sdcc-sup-voltages = <2950 2950>;
|
||||
qcom,sdcc-bus-width = <4>;
|
||||
};
|
||||
|
||||
qcom,sdcc@f9864000 {
|
||||
cell-index = <3>;
|
||||
compatible = "qcom,msm-sdcc";
|
||||
reg = <0xf9864000 0x1000>;
|
||||
interrupts = <0 127 0>;
|
||||
|
||||
qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
|
||||
qcom,sdcc-sup-voltages = <1800 1800>;
|
||||
qcom,sdcc-bus-width = <4>;
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
qcom,sdcc@f98e4000 {
|
||||
cell-index = <4>;
|
||||
compatible = "qcom,msm-sdcc";
|
||||
reg = <0xf98e4000 0x1000>;
|
||||
interrupts = <0 129 0>;
|
||||
|
||||
qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
|
||||
qcom,sdcc-sup-voltages = <1800 1800>;
|
||||
qcom,sdcc-bus-width = <4>;
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
qcom,sps@f9980000 {
|
||||
compatible = "qcom,msm_sps";
|
||||
reg = <0xf9984000 0x15000>,
|
||||
<0xf9999000 0xb000>;
|
||||
interrupts = <0 94 0>;
|
||||
|
||||
qcom,bam-dma-res-pipes = <6>;
|
||||
};
|
||||
|
||||
|
||||
spi@f9924000 {
|
||||
compatible = "qcom,spi-qup-v2";
|
||||
reg = <0xf9924000 0x1000>;
|
||||
interrupts = <0 96 0>;
|
||||
spi-max-frequency = <25000000>;
|
||||
};
|
||||
|
||||
slim@fe12f000 {
|
||||
cell-index = <1>;
|
||||
compatible = "qcom,slim-msm";
|
||||
reg = <0xfe12f000 0x35000>,
|
||||
<0xfe104000 0x20000>;
|
||||
reg-names = "slimbus_physical", "slimbus_bam_physical";
|
||||
interrupts = <0 163 0 0 164 0>;
|
||||
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
|
||||
qcom,min-clk-gear = <10>;
|
||||
};
|
||||
|
||||
qcom,spmi@fc4c0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,spmi-pmic-arb";
|
||||
reg = <0xfc4cf000 0x1000>,
|
||||
<0Xfc4cb000 0x1000>;
|
||||
/* 190,ee0_krait_hlos_spmi_periph_irq */
|
||||
/* 187,channel_0_krait_hlos_trans_done_irq */
|
||||
interrupts = <0 190 0 0 187 0>;
|
||||
qcom,pmic-arb-ee = <0>;
|
||||
qcom,pmic-arb-channel = <0>;
|
||||
qcom,pmic-arb-ppid-map = <0x13000000>, /* PM8941_LDO1 */
|
||||
<0x13100001>, /* PM8941_LDO2 */
|
||||
<0x13200002>, /* PM8941_LDO3 */
|
||||
<0x13300003>, /* PM8941_LDO4 */
|
||||
<0x13400004>, /* PM8941_LDO5 */
|
||||
<0x13500005>, /* PM8941_LDO6 */
|
||||
<0x13600006>, /* PM8941_LDO7 */
|
||||
<0x13700007>, /* PM8941_LDO8 */
|
||||
<0x13800008>, /* PM8941_LDO9 */
|
||||
<0x13900009>, /* PM8941_LDO10 */
|
||||
<0x13a0000a>, /* PM8941_LDO11 */
|
||||
<0x13b0000b>, /* PM8941_LDO12 */
|
||||
<0x13c0000c>, /* PM8941_LDO13 */
|
||||
<0x13d0000d>, /* PM8941_LDO14 */
|
||||
<0x13e0000e>, /* PM8941_LDO15 */
|
||||
<0x13f0000f>, /* PM8941_LDO16 */
|
||||
<0x14000010>, /* PM8941_LDO17 */
|
||||
<0x14100011>, /* PM8941_LDO18 */
|
||||
<0x14200012>, /* PM8941_LDO19 */
|
||||
<0x14300013>, /* PM8941_LDO20 */
|
||||
<0x14400014>, /* PM8941_LDO21 */
|
||||
<0x14500015>, /* PM8941_LDO22 */
|
||||
<0x14600016>, /* PM8941_LDO23 */
|
||||
<0x14700017>, /* PM8941_LDO24 */
|
||||
<0x14800018>, /* PM8941_LDO25 */
|
||||
<0x14900019>, /* PM8941_LDO26 */
|
||||
<0x0c00001a>, /* PM8941_GPIO1 */
|
||||
<0x0c10001b>, /* PM8941_GPIO2 */
|
||||
<0x0c20001c>, /* PM8941_GPIO3 */
|
||||
<0x0c30001d>, /* PM8941_GPIO4 */
|
||||
<0x0c40001e>, /* PM8941_GPIO5 */
|
||||
<0x0c50001f>, /* PM8941_GPIO6 */
|
||||
<0x0c600020>, /* PM8941_GPIO7 */
|
||||
<0x0c700021>, /* PM8941_GPIO8 */
|
||||
<0x0c800022>, /* PM8941_GPIO9 */
|
||||
<0x0c900023>, /* PM8941_GPIO10 */
|
||||
<0x0ca00024>, /* PM8941_GPIO11 */
|
||||
<0x0cb00025>, /* PM8941_GPIO12 */
|
||||
<0x0cc00026>, /* PM8941_GPIO13 */
|
||||
<0x0cd00027>, /* PM8941_GPIO14 */
|
||||
<0x0ce00028>, /* PM8941_GPIO15 */
|
||||
<0x0cf00029>, /* PM8941_GPIO16 */
|
||||
<0x0d00002a>, /* PM8941_GPIO17 */
|
||||
<0x0d10002b>, /* PM8941_GPIO18 */
|
||||
<0x0d20002c>, /* PM8941_GPIO19 */
|
||||
<0x0d30002d>, /* PM8941_GPIO20 */
|
||||
<0x0d40002e>, /* PM8941_GPIO21 */
|
||||
<0x0d50002f>, /* PM8941_GPIO22 */
|
||||
<0x0d600030>, /* PM8941_GPIO23 */
|
||||
<0x0d700031>, /* PM8941_GPIO24 */
|
||||
<0x0d800032>, /* PM8941_GPIO25 */
|
||||
<0x0d900033>, /* PM8941_GPIO26 */
|
||||
<0x0da00034>, /* PM8941_GPIO27 */
|
||||
<0x0db00035>, /* PM8941_GPIO28 */
|
||||
<0x0dc00036>, /* PM8941_GPIO29 */
|
||||
<0x0dd00037>, /* PM8941_GPIO30 */
|
||||
<0x0de00038>, /* PM8941_GPIO31 */
|
||||
<0x0df00039>, /* PM8941_GPIO32 */
|
||||
<0x0e00003a>, /* PM8941_GPIO33 */
|
||||
<0x0e10003b>, /* PM8941_GPIO34 */
|
||||
<0x0e20003c>, /* PM8941_GPIO35 */
|
||||
<0x0e30003d>, /* PM8941_GPIO36 */
|
||||
<0x0280003e>, /* COINCELL */
|
||||
<0x0100003f>, /* SMBC_OVP */
|
||||
<0x01100040>, /* SMBC_CHG */
|
||||
<0x01200041>, /* SMBC_BIF */
|
||||
<0x00500042>, /* INTERRUPT */
|
||||
<0x00100043>, /* PM8941_0 */
|
||||
<0x20100044>, /* PM8841_0 */
|
||||
<0x10100045>, /* PM8941_1 */
|
||||
<0x30100046>, /* PM8841_1 */
|
||||
<0x00800047>, /* PON0 */
|
||||
<0x20800048>, /* PON1 */
|
||||
<0x11000049>, /* PM8941_SMPS1 */
|
||||
<0x1110004a>, /* PM8941_SMPS2 */
|
||||
<0x1120004b>, /* PM8941_SMPS3 */
|
||||
<0x3100004c>, /* PM8841_SMPS1 */
|
||||
<0x3110004d>, /* PM8841_SMPS2 */
|
||||
<0x3120004e>, /* PM8841_SMPS3 */
|
||||
<0x3130004f>, /* PM8841_SMPS4 */
|
||||
<0x31400050>, /* PM8841_SMPS5 */
|
||||
<0x31500051>, /* PM8841_SMPS6 */
|
||||
<0x31600052>, /* PM8841_SMPS7 */
|
||||
<0x31700053>, /* PM8841_SMPS8 */
|
||||
<0x05000054>, /* SHARED_XO */
|
||||
<0x05100055>, /* BB_CLK1 */
|
||||
<0x05200056>, /* BB_CLK2 */
|
||||
<0x05900057>, /* SLEEP_CLK */
|
||||
<0x07000058>, /* PBS_CORE */
|
||||
<0x07100059>, /* PBS_CLIENT1 */
|
||||
<0x0720005a>; /* PBS_CLIENT2 */
|
||||
};
|
||||
|
||||
i2c@f9966000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,i2c-qup";
|
||||
reg = <0Xf9966000 0x1000>;
|
||||
reg-names = "qup_phys_addr";
|
||||
interrupts = <0 104 0>;
|
||||
interrupt-names = "qup_err_intr";
|
||||
qcom,i2c-bus-freq = <100000>;
|
||||
qcom,i2c-src-freq = <24000000>;
|
||||
};
|
||||
|
||||
qcom,acpuclk@f9000000 {
|
||||
compatible = "qcom,acpuclk-copper";
|
||||
};
|
||||
|
||||
qcom,ssusb@F9200000 {
|
||||
compatible = "qcom,dwc-usb3-msm";
|
||||
reg = <0xF9200000 0xCCFF>;
|
||||
interrupts = <0 131 0>;
|
||||
qcom,dwc-usb3-msm-dbm-eps = <4>;
|
||||
};
|
||||
|
||||
gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
|
||||
parent-supply = <&pm8841_s4>;
|
||||
};
|
||||
|
||||
qcom,lpass@fe200000 {
|
||||
compatible = "qcom,pil-q6v5-lpass";
|
||||
reg = <0xfe200000 0x00100>,
|
||||
<0xfd485100 0x00010>;
|
||||
|
||||
qcom,firmware-name = "adsp";
|
||||
};
|
||||
|
||||
qcom,mss@fc880000 {
|
||||
compatible = "qcom,pil-q6v5-mss";
|
||||
reg = <0xfc880000 0x100>,
|
||||
<0xfd485000 0x400>,
|
||||
<0xfc820000 0x020>,
|
||||
<0xfc401680 0x004>;
|
||||
vdd_mss-supply = <&pm8841_s3>;
|
||||
|
||||
qcom,firmware-name = "mba";
|
||||
qcom,pil-self-auth = <1>;
|
||||
};
|
||||
|
||||
qcom,mba@fc820000 {
|
||||
compatible = "qcom,pil-mba";
|
||||
reg = <0xfc820000 0x0020>,
|
||||
<0x0d1fc000 0x4000>;
|
||||
|
||||
qcom,firmware-name = "modem";
|
||||
qcom,depends-on = "mba";
|
||||
};
|
||||
|
||||
qcom,pronto@fb21b000 {
|
||||
compatible = "qcom,pil-pronto";
|
||||
reg = <0xfb21b000 0x3000>,
|
||||
<0xfc401700 0x4>,
|
||||
<0xfd485300 0xc>;
|
||||
vdd_pronto_pll-supply = <&pm8941_l12>;
|
||||
|
||||
qcom,firmware-name = "wcnss";
|
||||
};
|
||||
|
||||
qcom,ocmem@fdd00000 {
|
||||
compatible = "qcom,msm_ocmem";
|
||||
};
|
||||
|
||||
qcom,rpm-smd {
|
||||
compatible = "qcom,rpm-smd";
|
||||
rpm-channel-name = "rpm_requests";
|
||||
rpm-channel-type = <15>; /* SMD_APPS_RPM */
|
||||
};
|
||||
|
||||
qcom,msm-rng@f9bff000 {
|
||||
compatible = "qcom,msm-rng";
|
||||
reg = <0xf9bff000 0x200>;
|
||||
};
|
||||
};
|
||||
280
arch/arm/boot/dts/msmcopper_pm.dtsi
Normal file
280
arch/arm/boot/dts/msmcopper_pm.dtsi
Normal file
@@ -0,0 +1,280 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
qcom,spm@f9089000 {
|
||||
compatible = "qcom,spm-v2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xf9089000 0x1000>;
|
||||
qcom,core-id = <0>;
|
||||
qcom,saw2-ver-reg = <0xfd0>;
|
||||
qcom,saw2-cfg = <0x1b>;
|
||||
qcom,saw2-avs-ctl = <0>;
|
||||
qcom,saw2-avs-hysteresis = <0>;
|
||||
qcom,saw2-avs-limit = <0>;
|
||||
qcom,saw2-avs-dly= <0>;
|
||||
qcom,saw2-spm-dly= <0x20000400>;
|
||||
qcom,saw2-spm-ctl = <0x1>;
|
||||
qcom,spm-cmd-wfi = [03 0b 0f];
|
||||
qcom,spm-cmd-spc = [00 20 50 80 60 70 10 92
|
||||
a0 b0 03 68 70 3b 92 a0 b0
|
||||
82 2b 50 10 30 02 22 30 0f];
|
||||
qcom,spm-cmd-pc = [00 20 10 92 a0 b0 07 3b 92
|
||||
a0 b0 82 10 30 02 22 30 0f];
|
||||
};
|
||||
|
||||
qcom,spm@f9099000 {
|
||||
compatible = "qcom,spm-v2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xf9099000 0x1000>;
|
||||
qcom,core-id = <1>;
|
||||
qcom,saw2-ver-reg = <0xfd0>;
|
||||
qcom,saw2-cfg = <0x1b>;
|
||||
qcom,saw2-avs-ctl = <0>;
|
||||
qcom,saw2-avs-hysteresis = <0>;
|
||||
qcom,saw2-avs-limit = <0>;
|
||||
qcom,saw2-avs-dly= <0>;
|
||||
qcom,saw2-spm-dly= <0x20000400>;
|
||||
qcom,saw2-spm-ctl = <0x1>;
|
||||
qcom,spm-cmd-wfi = [03 0b 0f];
|
||||
qcom,spm-cmd-spc = [00 20 50 80 60 70 10 92
|
||||
a0 b0 03 68 70 3b 92 a0 b0
|
||||
82 2b 50 10 30 02 22 30 0f];
|
||||
qcom,spm-cmd-pc = [00 20 10 92 a0 b0 07 3b 92
|
||||
a0 b0 82 10 30 02 22 30 0f];
|
||||
};
|
||||
|
||||
qcom,spm@f90a9000 {
|
||||
compatible = "qcom,spm-v2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xf90a9000 0x1000>;
|
||||
qcom,core-id = <2>;
|
||||
qcom,saw2-ver-reg = <0xfd0>;
|
||||
qcom,saw2-cfg = <0x1b>;
|
||||
qcom,saw2-avs-ctl = <0>;
|
||||
qcom,saw2-avs-hysteresis = <0>;
|
||||
qcom,saw2-avs-limit = <0>;
|
||||
qcom,saw2-avs-dly= <0>;
|
||||
qcom,saw2-spm-dly= <0x20000400>;
|
||||
qcom,saw2-spm-ctl = <0x1>;
|
||||
qcom,spm-cmd-wfi = [03 0b 0f];
|
||||
qcom,spm-cmd-spc = [00 20 50 80 60 70 10 92
|
||||
a0 b0 03 68 70 3b 92 a0 b0
|
||||
82 2b 50 10 30 02 22 30 0f];
|
||||
qcom,spm-cmd-pc = [00 20 10 92 a0 b0 07 3b 92
|
||||
a0 b0 82 10 30 02 22 30 0f];
|
||||
};
|
||||
|
||||
qcom,spm@f90b9000 {
|
||||
compatible = "qcom,spm-v2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xf90b9000 0x1000>;
|
||||
qcom,core-id = <3>;
|
||||
qcom,saw2-ver-reg = <0xfd0>;
|
||||
qcom,saw2-cfg = <0x1b>;
|
||||
qcom,saw2-avs-ctl = <0>;
|
||||
qcom,saw2-avs-hysteresis = <0>;
|
||||
qcom,saw2-avs-limit = <0>;
|
||||
qcom,saw2-avs-dly= <0>;
|
||||
qcom,saw2-spm-dly= <0x20000400>;
|
||||
qcom,saw2-spm-ctl = <0x1>;
|
||||
qcom,spm-cmd-wfi = [03 0b 0f];
|
||||
qcom,spm-cmd-spc = [00 20 50 80 60 70 10 92
|
||||
a0 b0 03 68 70 3b 92 a0 b0
|
||||
82 2b 50 10 30 02 22 30 0f];
|
||||
qcom,spm-cmd-pc = [00 20 10 92 a0 b0 07 3b 92
|
||||
a0 b0 82 10 30 02 22 30 0f];
|
||||
};
|
||||
|
||||
qcom,spm@f9012000 {
|
||||
compatible = "qcom,spm-v2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xf9012000 0x1000>;
|
||||
qcom,core-id = <0xffff>; /* L2/APCS SAW */
|
||||
qcom,saw2-ver-reg = <0xfd0>;
|
||||
qcom,saw2-cfg = <0x1a>;
|
||||
qcom,saw2-avs-ctl = <0>;
|
||||
qcom,saw2-avs-hysteresis = <0>;
|
||||
qcom,saw2-avs-limit = <0>;
|
||||
qcom,saw2-avs-dly= <0>;
|
||||
qcom,saw2-spm-dly= <0x20000400>;
|
||||
qcom,saw2-spm-ctl = <0x0>; /* TODO: Enable L2 SPM */
|
||||
qcom,saw2-pmic-dly = <0x02020204>;
|
||||
qcom,saw2-pmic-data0 = <0x0400009c>;
|
||||
qcom,saw2-pmic-data1 = <0x00000060>;
|
||||
qcom,saw2-pmic-data2 = <0x0000001c>;
|
||||
qcom,saw2-pmic-data3 = <0x04000000>;
|
||||
qcom,vctl-timeout-us = <50>;
|
||||
qcom,vctl-port = <0x0>; /* TODO: */
|
||||
qcom,phase-port = <0x1>; /* TODO: */
|
||||
qcom,spm-cmd-ret = [0b 00 20 03 22 00 0f];
|
||||
qcom,spm-cmd-spc = [00 20 32 60 70 80 42 03
|
||||
78 80 44 22 50 3b 60 02 32
|
||||
50 0f];
|
||||
qcom,spm-cmd-pc = [00 10 32 60 70 80 b0 11 42
|
||||
07 01 b0 78 80 12 44 a0 50
|
||||
3b 60 02 32 a0 50 0f];
|
||||
};
|
||||
|
||||
qcom,lpm-levels {
|
||||
compatible = "qcom,lpm-levels";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,lpm-level@0 {
|
||||
reg = <0x0>;
|
||||
qcom,mode = <0>; /* MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT */
|
||||
qcom,xo = <1>; /* ON */
|
||||
qcom,l2 = <3>; /* ACTIVE */
|
||||
qcom,vdd-mem-upper-bound = <1150000>; /* MAX */
|
||||
qcom,vdd-mem-lower-bound = <1050000>; /* ACTIVE */
|
||||
qcom,vdd-dig-upper-bound = <1150000>; /* MAX */
|
||||
qcom,vdd-dig-lower-bound = <950000>; /* ACTIVE */
|
||||
qcom,latency-us = <100>;
|
||||
qcom,ss-power = <650>;
|
||||
qcom,energy-overhead = <801>;
|
||||
qcom,time-overhead = <200>;
|
||||
};
|
||||
|
||||
qcom,lpm-level@1 {
|
||||
reg = <0x1>;
|
||||
qcom,mode = <2>; /* MSM_PM_SLEEP_MODE_STANDALONE_POWER_COLLAPSE */
|
||||
qcom,xo = <1>; /* ON */
|
||||
qcom,l2 = <3>; /* ACTIVE */
|
||||
qcom,vdd-mem-upper-bound = <1150000>; /* MAX */
|
||||
qcom,vdd-mem-lower-bound = <1050000>; /* ACTIVE */
|
||||
qcom,vdd-dig-upper-bound = <1150000>; /* MAX */
|
||||
qcom,vdd-dig-lower-bound = <950000>; /* ACTIVE */
|
||||
qcom,latency-us = <2000>;
|
||||
qcom,ss-power = <200>;
|
||||
qcom,energy-overhead = <576000>;
|
||||
qcom,time-overhead = <2000>;
|
||||
};
|
||||
|
||||
qcom,lpm-level@2 {
|
||||
reg = <0x2>;
|
||||
qcom,mode = <3>; /* MSM_PM_SLEEP_MODE_POWER_COLLAPSE */
|
||||
qcom,xo = <1>; /* ON */
|
||||
qcom,l2 = <1>; /* GDHS */
|
||||
qcom,vdd-mem-upper-bound = <1150000>; /* MAX */
|
||||
qcom,vdd-mem-lower-bound = <1050000>; /* ACTIVE */
|
||||
qcom,vdd-dig-upper-bound = <1150000>; /* MAX */
|
||||
qcom,vdd-dig-lower-bound = <950000>; /* ACTIVE */
|
||||
qcom,latency-us = <8500>;
|
||||
qcom,ss-power = <51>;
|
||||
qcom,energy-overhead = <1122000>;
|
||||
qcom,time-overhead = <8500>;
|
||||
};
|
||||
|
||||
qcom,lpm-level@3 {
|
||||
reg = <0x3>;
|
||||
qcom,mode = <3>; /* MSM_PM_SLEEP_MODE_POWER_COLLAPSE */
|
||||
qcom,xo = <1>; /* ON */
|
||||
qcom,l2 = <0>; /* OFF */
|
||||
qcom,vdd-mem-upper-bound = <1150000>; /* MAX */
|
||||
qcom,vdd-mem-lower-bound = <1050000>; /* ACTIVE */
|
||||
qcom,vdd-dig-upper-bound = <1150000>; /* MAX */
|
||||
qcom,vdd-dig-lower-bound = <950000>; /* ACTIVE */
|
||||
qcom,latency-us = <9000>;
|
||||
qcom,ss-power = <51>;
|
||||
qcom,energy-overhead = <1130300>;
|
||||
qcom,time-overhead = <9000>;
|
||||
};
|
||||
|
||||
qcom,lpm-level@4 {
|
||||
reg = <0x4>;
|
||||
qcom,mode = <3>; /* MSM_PM_SLEEP_MODE_POWER_COLLAPSE */
|
||||
qcom,xo = <1>; /* ON */
|
||||
qcom,l2 = <0>; /* OFF */
|
||||
qcom,vdd-mem-upper-bound = <1050000>; /* ACTIVE */
|
||||
qcom,vdd-mem-lower-bound = <750000>; /* RETENTION HIGH */
|
||||
qcom,vdd-dig-upper-bound = <950000>; /* ACTIVE */
|
||||
qcom,vdd-dig-lower-bound = <750000>; /* RETENTION HIGH */
|
||||
qcom,latency-us = <10000>;
|
||||
qcom,ss-power = <51>;
|
||||
qcom,energy-overhead = <1130300>;
|
||||
qcom,time-overhead = <10000>;
|
||||
};
|
||||
|
||||
qcom,lpm-level@5 {
|
||||
reg = <0x5>;
|
||||
qcom,mode = <3>; /* MSM_PM_SLEEP_MODE_POWER_COLLAPSE */
|
||||
qcom,xo = <0>; /* OFF */
|
||||
qcom,l2 = <1>; /* GDHS */
|
||||
qcom,vdd-mem-upper-bound = <1150000>; /* MAX */
|
||||
qcom,vdd-mem-lower-bound = <1050000>; /* ACTIVE */
|
||||
qcom,vdd-dig-upper-bound = <1150000>; /* MAX */
|
||||
qcom,vdd-dig-lower-bound = <950000>; /* ACTIVE */
|
||||
qcom,latency-us = <12000>;
|
||||
qcom,ss-power = <14>;
|
||||
qcom,energy-overhead = <2205900>;
|
||||
qcom,time-overhead = <12000>;
|
||||
};
|
||||
|
||||
qcom,lpm-level@6 {
|
||||
reg = <0x6>;
|
||||
qcom,mode = <3>; /* MSM_PM_SLEEP_MODE_POWER_COLLAPSE */
|
||||
qcom,xo = <0>; /* OFF */
|
||||
qcom,l2 = <0>; /* OFF */
|
||||
qcom,vdd-mem-upper-bound = <1150000>; /* MAX */
|
||||
qcom,vdd-mem-lower-bound = <1050000>; /* ACTIVE */
|
||||
qcom,vdd-dig-upper-bound = <1150000>; /* MAX */
|
||||
qcom,vdd-dig-lower-bound = <950000>; /* ACTIVE */
|
||||
qcom,latency-us = <18000>;
|
||||
qcom,ss-power = <12>;
|
||||
qcom,energy-overhead = <2364250>;
|
||||
qcom,time-overhead = <18000>;
|
||||
};
|
||||
|
||||
qcom,lpm-level@7 {
|
||||
reg = <0x7>;
|
||||
qcom,mode= <3>; /* MSM_PM_SLEEP_MODE_POWER_COLLAPSE */
|
||||
qcom,xo = <0>; /* OFF */
|
||||
qcom,l2 = <0>; /* OFF */
|
||||
qcom,vdd-mem-upper-bound = <1050000>; /* ACTIVE */
|
||||
qcom,vdd-mem-lower-bound = <750000>; /* RETENTION HIGH */
|
||||
qcom,vdd-dig-upper-bound = <950000>; /* ACTIVE */
|
||||
qcom,vdd-dig-lower-bound = <750000>; /* RETIONTION HIGH */
|
||||
qcom,latency-us = <23500>;
|
||||
qcom,ss-power = <10>;
|
||||
qcom,energy-overhead = <2667000>;
|
||||
qcom,time-overhead = <23500>;
|
||||
};
|
||||
|
||||
qcom,lpm-level@8 {
|
||||
reg = <0x8>;
|
||||
qcom,mode= <3>; /* MSM_PM_SLEEP_MODE_POWER_COLLAPSE */
|
||||
qcom,xo = <0>; /* OFF */
|
||||
qcom,l2 = <0>; /* OFF */
|
||||
qcom,vdd-mem-upper-bound = <750000>; /* RETENTION HIGH */
|
||||
qcom,vdd-mem-lower-bound = <750000>; /* RETENTION LOW */
|
||||
qcom,vdd-dig-upper-bound = <750000>; /* RETENTION HIGH */
|
||||
qcom,vdd-dig-lower-bound = <500000>; /* RETENTION LOW */
|
||||
qcom,latency-us = <29700>;
|
||||
qcom,ss-power = <5>;
|
||||
qcom,energy-overhead = <2867000>;
|
||||
qcom,time-overhead = <30000>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,pm-boot {
|
||||
compatible = "qcom,pm-boot";
|
||||
qcom,mode = <0>; /* MSM_PM_BOOT_CONFIG_TZ */
|
||||
};
|
||||
};
|
||||
184
arch/arm/configs/fsm9xxx-perf_defconfig
Normal file
184
arch/arm/configs/fsm9xxx-perf_defconfig
Normal file
@@ -0,0 +1,184 @@
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_LOCALVERSION="$(KERNEL_LOCAL_VERSION)"
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_PANIC_TIMEOUT=5
|
||||
CONFIG_ASHMEM=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_PERF_EVENTS is not set
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=m
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARCH_MSM=y
|
||||
CONFIG_ARCH_FSM9XXX=y
|
||||
# CONFIG_MSM_STACKED_MEMORY is not set
|
||||
CONFIG_MSM7X00A_USE_DG_TIMER=y
|
||||
CONFIG_MSM7X00A_SLEEP_WAIT_FOR_INTERRUPT=y
|
||||
CONFIG_MSM7X00A_IDLE_SLEEP_WAIT_FOR_INTERRUPT=y
|
||||
CONFIG_MSM_SMD=y
|
||||
CONFIG_MSM_SMD_PKG3=y
|
||||
# CONFIG_MSM_SMD_DEBUG is not set
|
||||
CONFIG_MSM_ONCRPCROUTER=y
|
||||
# CONFIG_MSM_ONCRPCROUTER_DEBUG is not set
|
||||
# CONFIG_MSM_HW3D is not set
|
||||
# CONFIG_QSD_AUDIO is not set
|
||||
# CONFIG_SURF_FFA_GPIO_KEYPAD is not set
|
||||
CONFIG_MSM_WATCHDOG=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_VMSPLIT_2G=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="init=/sbin/init root=/dev/ram rw initrd=0x11000000,16M console=ttyDCC0 mem=88M ip=dhcp"
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_NET_KEY=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_INET_AH=y
|
||||
CONFIG_INET_ESP=y
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_IPV6_OPTIMISTIC_DAD=y
|
||||
CONFIG_INET6_AH=y
|
||||
CONFIG_INET6_ESP=y
|
||||
CONFIG_INET6_IPCOMP=y
|
||||
CONFIG_IPV6_MIP6=y
|
||||
CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y
|
||||
CONFIG_IPV6_TUNNEL=y
|
||||
CONFIG_IPV6_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6_SUBTREES=y
|
||||
CONFIG_IPV6_MROUTE=y
|
||||
CONFIG_IPV6_PIMSM_V2=y
|
||||
# CONFIG_NET_ACTIVITY_STATS is not set
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_TESTS=m
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_COUNT=8
|
||||
CONFIG_BLK_DEV_RAM_SIZE=16384
|
||||
CONFIG_PMIC8058_XOADC=y
|
||||
CONFIG_QFP_FUSE=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_TGT=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_SCH=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
# CONFIG_MSM_RMNET is not set
|
||||
CONFIG_QFEC=y
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_SLIP=y
|
||||
CONFIG_SLIP_COMPRESSED=y
|
||||
CONFIG_SLIP_MODE_SLIP6=y
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_EVBUG=m
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
CONFIG_INPUT_GPIO=y
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_MSM=y
|
||||
CONFIG_SERIAL_MSM_CONSOLE=y
|
||||
# CONFIG_DIAG_OVER_USB is not set
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_DCC_TTY=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_SSBI=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_SENSORS_MSM_ADC=y
|
||||
CONFIG_PMIC8058=y
|
||||
# CONFIG_MFD_PM8XXX_PWM is not set
|
||||
# CONFIG_MFD_PM8XXX_MISC is not set
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_PM8058_XO=y
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_SWITCH=y
|
||||
CONFIG_SWITCH_GPIO=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DEBUG=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_ANDROID_BINDER_IPC=y
|
||||
CONFIG_ANDROID_LOGGER=y
|
||||
CONFIG_ANDROID_RAM_CONSOLE=y
|
||||
CONFIG_ANDROID_TIMED_GPIO=y
|
||||
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
|
||||
CONFIG_MSM_SSBI=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_YAFFS_FS=y
|
||||
CONFIG_YAFFS_DISABLE_TAGS_ECC=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_STACKTRACE is not set
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
|
||||
CONFIG_CRYPTO_NULL=y
|
||||
CONFIG_CRYPTO_CRYPTD=y
|
||||
CONFIG_CRYPTO_TEST=m
|
||||
CONFIG_CRYPTO_CTR=y
|
||||
CONFIG_CRYPTO_CTS=y
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
CONFIG_CRYPTO_DEV_QCRYPTO=y
|
||||
CONFIG_CRYPTO_DEV_QCE=y
|
||||
CONFIG_CRYPTO_DEV_OTA_CRYPTO=y
|
||||
CONFIG_CRC_CCITT=y
|
||||
186
arch/arm/configs/fsm9xxx_defconfig
Normal file
186
arch/arm/configs/fsm9xxx_defconfig
Normal file
@@ -0,0 +1,186 @@
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_LOCALVERSION="$(KERNEL_LOCAL_VERSION)"
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_PANIC_TIMEOUT=5
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_ASHMEM=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_PERF_EVENTS is not set
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=m
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARCH_MSM=y
|
||||
CONFIG_ARCH_FSM9XXX=y
|
||||
# CONFIG_MSM_STACKED_MEMORY is not set
|
||||
CONFIG_MSM7X00A_USE_DG_TIMER=y
|
||||
CONFIG_MSM7X00A_SLEEP_WAIT_FOR_INTERRUPT=y
|
||||
CONFIG_MSM7X00A_IDLE_SLEEP_WAIT_FOR_INTERRUPT=y
|
||||
CONFIG_MSM_SMD=y
|
||||
CONFIG_MSM_SMD_PKG3=y
|
||||
CONFIG_MSM_ONCRPCROUTER=y
|
||||
# CONFIG_MSM_HW3D is not set
|
||||
# CONFIG_QSD_AUDIO is not set
|
||||
# CONFIG_SURF_FFA_GPIO_KEYPAD is not set
|
||||
CONFIG_MSM_WATCHDOG=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_VMSPLIT_2G=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="init=/sbin/init root=/dev/ram rw initrd=0x11000000,16M console=ttyDCC0 mem=88M ip=dhcp"
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_NET_KEY=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_INET_AH=y
|
||||
CONFIG_INET_ESP=y
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_IPV6_OPTIMISTIC_DAD=y
|
||||
CONFIG_INET6_AH=y
|
||||
CONFIG_INET6_ESP=y
|
||||
CONFIG_INET6_IPCOMP=y
|
||||
CONFIG_IPV6_MIP6=y
|
||||
CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y
|
||||
CONFIG_IPV6_TUNNEL=y
|
||||
CONFIG_IPV6_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6_SUBTREES=y
|
||||
CONFIG_IPV6_MROUTE=y
|
||||
CONFIG_IPV6_PIMSM_V2=y
|
||||
# CONFIG_NET_ACTIVITY_STATS is not set
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_TESTS=m
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_COUNT=8
|
||||
CONFIG_BLK_DEV_RAM_SIZE=16384
|
||||
CONFIG_PMIC8058_XOADC=y
|
||||
CONFIG_QFP_FUSE=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_TGT=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_SCH=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
# CONFIG_MSM_RMNET is not set
|
||||
CONFIG_QFEC=y
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_SLIP=y
|
||||
CONFIG_SLIP_COMPRESSED=y
|
||||
CONFIG_SLIP_MODE_SLIP6=y
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_EVBUG=m
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
CONFIG_INPUT_GPIO=y
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_MSM=y
|
||||
CONFIG_SERIAL_MSM_CONSOLE=y
|
||||
# CONFIG_DIAG_OVER_USB is not set
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_DCC_TTY=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_SSBI=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_SENSORS_MSM_ADC=y
|
||||
CONFIG_PMIC8058=y
|
||||
# CONFIG_MFD_PM8XXX_PWM is not set
|
||||
# CONFIG_MFD_PM8XXX_MISC is not set
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_PM8058_XO=y
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_SWITCH=y
|
||||
CONFIG_SWITCH_GPIO=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DEBUG=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_ANDROID_BINDER_IPC=y
|
||||
CONFIG_ANDROID_LOGGER=y
|
||||
CONFIG_ANDROID_RAM_CONSOLE=y
|
||||
CONFIG_ANDROID_TIMED_GPIO=y
|
||||
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
|
||||
CONFIG_MSM_SSBI=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_YAFFS_FS=y
|
||||
CONFIG_YAFFS_DISABLE_TAGS_ECC=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_SCHEDSTATS=y
|
||||
# CONFIG_STACKTRACE is not set
|
||||
CONFIG_DEBUG_STACK_USAGE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
|
||||
CONFIG_CRYPTO_NULL=y
|
||||
CONFIG_CRYPTO_CRYPTD=y
|
||||
CONFIG_CRYPTO_TEST=m
|
||||
CONFIG_CRYPTO_CTR=y
|
||||
CONFIG_CRYPTO_CTS=y
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
CONFIG_CRYPTO_DEV_QCRYPTO=y
|
||||
CONFIG_CRYPTO_DEV_QCE=y
|
||||
CONFIG_CRYPTO_DEV_OTA_CRYPTO=y
|
||||
CONFIG_CRC_CCITT=y
|
||||
206
arch/arm/configs/msm-copper_defconfig
Normal file
206
arch/arm/configs/msm-copper_defconfig
Normal file
@@ -0,0 +1,206 @@
|
||||
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_DEBUG=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_RESOURCE_COUNTERS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
# CONFIG_FAIR_GROUP_SCHED is not set
|
||||
CONFIG_RT_GROUP_SCHED=y
|
||||
CONFIG_NAMESPACES=y
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_USER_NS is not set
|
||||
# CONFIG_PID_NS is not set
|
||||
CONFIG_RELAY=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_ASHMEM=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=m
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
CONFIG_ARCH_MSM=y
|
||||
CONFIG_ARCH_MSMCOPPER=y
|
||||
CONFIG_MSM_KRAIT_TBB_ABORT_HANDLER=y
|
||||
# CONFIG_MSM_STACKED_MEMORY is not set
|
||||
CONFIG_KERNEL_PMEM_EBI_REGION=y
|
||||
CONFIG_CPU_HAS_L2_PMU=y
|
||||
# CONFIG_MSM_FIQ_SUPPORT is not set
|
||||
# CONFIG_MSM_PROC_COMM is not set
|
||||
CONFIG_MSM_SMD=y
|
||||
CONFIG_MSM_SMD_PKG4=y
|
||||
CONFIG_MSM_IPC_ROUTER=y
|
||||
CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
|
||||
# CONFIG_MSM_HW3D is not set
|
||||
CONFIG_MSM_PIL_LPASS_QDSP6V5=y
|
||||
CONFIG_MSM_PIL_MSS_QDSP6V5=y
|
||||
CONFIG_MSM_PIL_MBA=y
|
||||
CONFIG_MSM_PIL_PRONTO=y
|
||||
CONFIG_MSM_TZ_LOG=y
|
||||
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
|
||||
CONFIG_MSM_OCMEM=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_SMP=y
|
||||
# CONFIG_SMP_ON_UP is not set
|
||||
CONFIG_ARM_ARCH_TIMER=y
|
||||
CONFIG_HOTPLUG_CPU=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_VMALLOC_RESERVE=0x19000000
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_IPV6_OPTIMISTIC_DAD=y
|
||||
CONFIG_IPV6_MIP6=y
|
||||
CONFIG_IPV6_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6_SUBTREES=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_TGT=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_SCH=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_KS8851=m
|
||||
# CONFIG_MSM_RMNET is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_EVBUG=m
|
||||
CONFIG_INPUT_JOYSTICK=y
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
CONFIG_SERIAL_MSM_HSL=y
|
||||
CONFIG_SERIAL_MSM_HSL_CONSOLE=y
|
||||
CONFIG_DIAG_CHAR=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_MSM=y
|
||||
CONFIG_DCC_TTY=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_QUP=y
|
||||
CONFIG_SPI_SPIDEV=m
|
||||
CONFIG_SPMI=y
|
||||
CONFIG_SPMI_MSM_PMIC_ARB=y
|
||||
CONFIG_MSM_QPNP=y
|
||||
CONFIG_SLIMBUS=y
|
||||
CONFIG_SLIMBUS_MSM_CTRL=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
# CONFIG_BATTERY_MSM is not set
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_REGULATOR_STUB=y
|
||||
CONFIG_REGULATOR_QPNP=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_VIDEO_DEV=y
|
||||
# CONFIG_RC_CORE is not set
|
||||
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
|
||||
CONFIG_VIDEOBUF2_MSM_MEM=y
|
||||
# CONFIG_VIDEO_CAPTURE_DRIVERS is not set
|
||||
# CONFIG_RADIO_ADAPTERS is not set
|
||||
CONFIG_ION=y
|
||||
CONFIG_ION_MSM=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_VIRTUAL=y
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_CI13XXX_MSM=y
|
||||
CONFIG_USB_G_ANDROID=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_PERF_PROFILING=y
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
CONFIG_MMC_PARANOID_SD_INIT=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
CONFIG_MMC_TEST=m
|
||||
CONFIG_MMC_MSM=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_SWITCH=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_ANDROID_BINDER_IPC=y
|
||||
CONFIG_ANDROID_LOGGER=y
|
||||
CONFIG_ANDROID_RAM_CONSOLE=y
|
||||
CONFIG_ANDROID_TIMED_GPIO=y
|
||||
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
|
||||
CONFIG_MSM_SSBI=y
|
||||
CONFIG_SPS=y
|
||||
CONFIG_SPS_SUPPORT_BAMDMA=y
|
||||
CONFIG_SPS_SUPPORT_NDP_BAM=y
|
||||
CONFIG_MSM_IOMMU=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_TIMER_STATS=y
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_MEMORY_INIT=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_DEBUG_LL=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
CONFIG_KEYS=y
|
||||
CONFIG_CRYPTO_AUTHENC=y
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_MD4=y
|
||||
CONFIG_CRYPTO_MD5=y
|
||||
CONFIG_CRYPTO_SHA1=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
CONFIG_CRYPTO_ARC4=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
CONFIG_CRC_CCITT=y
|
||||
CONFIG_LIBCRC32C=y
|
||||
344
arch/arm/configs/msm7627a-perf_defconfig
Normal file
344
arch/arm/configs/msm7627a-perf_defconfig
Normal file
@@ -0,0 +1,344 @@
|
||||
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_LOCALVERSION="$(KERNEL_LOCAL_VERSION)-perf"
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_DEVICE=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_RESOURCE_COUNTERS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_RT_GROUP_SCHED=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_ASHMEM=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=y
|
||||
CONFIG_KPROBES=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
CONFIG_ARCH_MSM=y
|
||||
CONFIG_ARCH_MSM7X27=y
|
||||
CONFIG_ARCH_MSM8625=y
|
||||
CONFIG_MSM_SOC_REV_A=y
|
||||
# CONFIG_MACH_MSM7X27_SURF is not set
|
||||
# CONFIG_MACH_MSM7X27_FFA is not set
|
||||
# CONFIG_MSM_STACKED_MEMORY is not set
|
||||
CONFIG_MSM7X00A_USE_DG_TIMER=y
|
||||
# CONFIG_MSM_FIQ_SUPPORT is not set
|
||||
CONFIG_MSM_SMD=y
|
||||
CONFIG_MSM_SMD_PKG4=y
|
||||
# CONFIG_MSM_SMD_DEBUG is not set
|
||||
# CONFIG_MSM_RESET_MODEM is not set
|
||||
# CONFIG_MSM_SMD_NMEA is not set
|
||||
# CONFIG_MSM_SMD_QMI is not set
|
||||
CONFIG_MSM_ONCRPCROUTER=y
|
||||
# CONFIG_MSM_RPCSERVER_TIME_REMOTE is not set
|
||||
CONFIG_MSM_RMT_STORAGE_CLIENT=y
|
||||
# CONFIG_MSM_HW3D is not set
|
||||
CONFIG_MSM7X27A_AUDIO=y
|
||||
CONFIG_MSM_DMA_TEST=y
|
||||
CONFIG_MSM_SLEEP_STATS_DEVICE=y
|
||||
CONFIG_BT_MSM_PINTEST=y
|
||||
CONFIG_MSM_RPC_VIBRATOR=y
|
||||
CONFIG_PM8XXX_RPC_VIBRATOR=y
|
||||
CONFIG_MSM_SPM_V2=y
|
||||
CONFIG_ARM_THUMBEE=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_VMALLOC_RESERVE=0xC800000
|
||||
CONFIG_CP_ACCESS=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="init=/sbin/init root=/dev/ram rw initrd=0x11000000,16M console=ttyDCC0 mem=88M"
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_STAT_DETAILS=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
|
||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_WAKELOCK=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_IPV6_OPTIMISTIC_DAD=y
|
||||
CONFIG_INET6_AH=y
|
||||
CONFIG_INET6_ESP=y
|
||||
CONFIG_INET6_IPCOMP=y
|
||||
CONFIG_IPV6_MIP6=y
|
||||
CONFIG_IPV6_TUNNEL=y
|
||||
CONFIG_IPV6_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6_SUBTREES=y
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_NETFILTER_NETLINK_LOG=y
|
||||
CONFIG_NF_CONNTRACK=y
|
||||
CONFIG_NF_CONNTRACK_EVENTS=y
|
||||
CONFIG_NF_CT_PROTO_DCCP=y
|
||||
CONFIG_NF_CT_PROTO_SCTP=y
|
||||
CONFIG_NF_CT_PROTO_UDPLITE=y
|
||||
CONFIG_NF_CONNTRACK_AMANDA=y
|
||||
CONFIG_NF_CONNTRACK_FTP=y
|
||||
CONFIG_NF_CONNTRACK_H323=y
|
||||
CONFIG_NF_CONNTRACK_IRC=y
|
||||
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
|
||||
CONFIG_NF_CONNTRACK_PPTP=y
|
||||
CONFIG_NF_CONNTRACK_SANE=y
|
||||
CONFIG_NF_CONNTRACK_SIP=y
|
||||
CONFIG_NF_CONNTRACK_TFTP=y
|
||||
CONFIG_NF_CT_NETLINK=y
|
||||
CONFIG_NETFILTER_TPROXY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_LOG=y
|
||||
CONFIG_NETFILTER_XT_TARGET_MARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_HELPER=y
|
||||
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MAC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_POLICY=y
|
||||
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
|
||||
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STRING=y
|
||||
CONFIG_NETFILTER_XT_MATCH_TIME=y
|
||||
CONFIG_NETFILTER_XT_MATCH_U32=y
|
||||
CONFIG_NF_CONNTRACK_IPV4=y
|
||||
CONFIG_IP_NF_IPTABLES=y
|
||||
CONFIG_IP_NF_MATCH_AH=y
|
||||
CONFIG_IP_NF_MATCH_ECN=y
|
||||
CONFIG_IP_NF_MATCH_TTL=y
|
||||
CONFIG_IP_NF_FILTER=y
|
||||
CONFIG_IP_NF_TARGET_REJECT=y
|
||||
CONFIG_NF_NAT=y
|
||||
CONFIG_IP_NF_TARGET_MASQUERADE=y
|
||||
CONFIG_IP_NF_TARGET_NETMAP=y
|
||||
CONFIG_IP_NF_TARGET_REDIRECT=y
|
||||
CONFIG_IP_NF_MANGLE=y
|
||||
CONFIG_IP_NF_ARPTABLES=y
|
||||
CONFIG_IP_NF_ARPFILTER=y
|
||||
CONFIG_IP_NF_ARP_MANGLE=y
|
||||
CONFIG_IP6_NF_IPTABLES=y
|
||||
CONFIG_BT=y
|
||||
CONFIG_BT_RFCOMM=y
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_BNEP=y
|
||||
CONFIG_BT_BNEP_MC_FILTER=y
|
||||
CONFIG_BT_BNEP_PROTO_FILTER=y
|
||||
CONFIG_BT_HIDP=y
|
||||
CONFIG_BT_HCIUART=y
|
||||
CONFIG_BT_HCIUART_H4=y
|
||||
CONFIG_BT_HCIUART_IBS=y
|
||||
CONFIG_MSM_BT_POWER=y
|
||||
CONFIG_CFG80211=m
|
||||
# CONFIG_CFG80211_WEXT is not set
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_GENLOCK=y
|
||||
CONFIG_GENLOCK_MISCDEVICE=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_TESTS=m
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_TGT=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_SCH=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_MD=y
|
||||
CONFIG_BLK_DEV_DM=y
|
||||
CONFIG_DM_CRYPT=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_LIBRA_SDIOIF=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_EVBUG=m
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_TOUCHSCREEN_ATMEL_MAXTOUCH=y
|
||||
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
|
||||
CONFIG_TOUCHSCREEN_SYNAPTICS_RMI4_I2C=y
|
||||
CONFIG_TOUCHSCREEN_FT5X06=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
CONFIG_INPUT_GPIO=y
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_MSM=y
|
||||
CONFIG_SERIAL_MSM_CONSOLE=y
|
||||
CONFIG_SERIAL_MSM_HS=y
|
||||
# CONFIG_SERIAL_MSM_CLOCK_CONTROL is not set
|
||||
CONFIG_DIAG_CHAR=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_I2C_MSM is not set
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_SX150X=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_BATTERY_MSM=y
|
||||
CONFIG_SENSORS_MSM_ADC=y
|
||||
CONFIG_MARIMBA_CORE=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_MEDIA_CONTROLLER=y
|
||||
CONFIG_VIDEO_DEV=y
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
# CONFIG_RC_CORE is not set
|
||||
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
|
||||
CONFIG_VIDEOBUF2_MSM_MEM=y
|
||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
||||
CONFIG_MSM_CAMERA_V4L2=y
|
||||
CONFIG_OV5647=y
|
||||
CONFIG_OV8825=y
|
||||
CONFIG_AD5046_ACT=y
|
||||
CONFIG_WEBCAM_OV9726=y
|
||||
CONFIG_MT9E013=y
|
||||
CONFIG_S5K4E1=y
|
||||
CONFIG_DW9712_ACT=y
|
||||
CONFIG_MSM_CAMERA_FLASH_SC628A=y
|
||||
CONFIG_MSM_CAMERA_SENSOR=y
|
||||
CONFIG_MSM_ACTUATOR=y
|
||||
CONFIG_OV7692=y
|
||||
CONFIG_RADIO_TAVARUA=y
|
||||
CONFIG_MSM_KGSL=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_MSM=y
|
||||
# CONFIG_FB_MSM_BACKLIGHT is not set
|
||||
CONFIG_FB_MSM_TRIPLE_BUFFER=y
|
||||
CONFIG_FB_MSM_MDP30=y
|
||||
CONFIG_FB_MSM_MDP303=y
|
||||
CONFIG_FB_MSM_LCDC_TRULY_HVGA_IPS3P2335_PT_PANEL=y
|
||||
CONFIG_FB_MSM_MIPI_PANEL_DETECT=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_MSM_SOC=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_MAGICMOUSE=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_SUSPEND=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_EHSET=y
|
||||
CONFIG_USB_EHCI_ROOT_HUB_TT=y
|
||||
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
|
||||
CONFIG_USB_EHCI_MSM_72K=y
|
||||
CONFIG_USB_ACM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_STORAGE_DATAFAB=y
|
||||
CONFIG_USB_STORAGE_FREECOM=y
|
||||
CONFIG_USB_STORAGE_ISD200=y
|
||||
CONFIG_USB_STORAGE_USBAT=y
|
||||
CONFIG_USB_STORAGE_SDDR09=y
|
||||
CONFIG_USB_STORAGE_SDDR55=y
|
||||
CONFIG_USB_STORAGE_JUMPSHOT=y
|
||||
CONFIG_USB_STORAGE_ALAUDA=y
|
||||
CONFIG_USB_STORAGE_ONETOUCH=y
|
||||
CONFIG_USB_STORAGE_KARMA=y
|
||||
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
|
||||
CONFIG_USB_EHSET_TEST_FIXTURE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_MSM_72K=y
|
||||
CONFIG_USB_G_ANDROID=y
|
||||
CONFIG_RMNET_SMD_CTL_CHANNEL="DATA40_CNTL"
|
||||
CONFIG_RMNET_SMD_DATA_CHANNEL="DATA40"
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_PERF_PROFILING=y
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
CONFIG_MMC_CLKGATE=y
|
||||
CONFIG_MMC_PARANOID_SD_INIT=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
CONFIG_MMC_TEST=m
|
||||
CONFIG_MMC_MSM=y
|
||||
CONFIG_MMC_MSM_CARD_HW_DETECTION=y
|
||||
CONFIG_MMC_MSM_SDC3_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC3_8_BIT_SUPPORT=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_MSM_PDM=y
|
||||
CONFIG_LEDS_PMIC_MPP=y
|
||||
CONFIG_SWITCH=y
|
||||
CONFIG_SWITCH_GPIO=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_ANDROID_BINDER_IPC=y
|
||||
CONFIG_ANDROID_LOGGER=y
|
||||
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_YAFFS_FS=y
|
||||
CONFIG_YAFFS_DISABLE_TAGS_ECC=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_SHIRQ=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_TIMER_STATS=y
|
||||
CONFIG_DEBUG_STACK_USAGE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_ENABLE_DEFAULT_TRACERS=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRC_CCITT=y
|
||||
352
arch/arm/configs/msm7627a_defconfig
Normal file
352
arch/arm/configs/msm7627a_defconfig
Normal file
@@ -0,0 +1,352 @@
|
||||
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_LOCALVERSION="$(KERNEL_LOCAL_VERSION)"
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_DEVICE=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_RESOURCE_COUNTERS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_RT_GROUP_SCHED=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_ASHMEM=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=y
|
||||
CONFIG_KPROBES=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
CONFIG_ARCH_MSM=y
|
||||
CONFIG_ARCH_MSM7X27=y
|
||||
CONFIG_ARCH_MSM8625=y
|
||||
CONFIG_MSM_SOC_REV_A=y
|
||||
# CONFIG_MACH_MSM7X27_SURF is not set
|
||||
# CONFIG_MACH_MSM7X27_FFA is not set
|
||||
# CONFIG_MSM_STACKED_MEMORY is not set
|
||||
CONFIG_MSM7X00A_USE_DG_TIMER=y
|
||||
# CONFIG_MSM_FIQ_SUPPORT is not set
|
||||
CONFIG_MSM_SMD=y
|
||||
CONFIG_MSM_SMD_PKG4=y
|
||||
# CONFIG_MSM_SMD_DEBUG is not set
|
||||
# CONFIG_MSM_RESET_MODEM is not set
|
||||
# CONFIG_MSM_SMD_NMEA is not set
|
||||
# CONFIG_MSM_SMD_QMI is not set
|
||||
CONFIG_MSM_ONCRPCROUTER=y
|
||||
# CONFIG_MSM_RPCSERVER_TIME_REMOTE is not set
|
||||
CONFIG_MSM_RMT_STORAGE_CLIENT=y
|
||||
# CONFIG_MSM_HW3D is not set
|
||||
CONFIG_MSM7X27A_AUDIO=y
|
||||
CONFIG_MSM_DMA_TEST=y
|
||||
CONFIG_MSM_SLEEP_STATS_DEVICE=y
|
||||
CONFIG_BT_MSM_PINTEST=y
|
||||
CONFIG_MSM_RPC_VIBRATOR=y
|
||||
CONFIG_PM8XXX_RPC_VIBRATOR=y
|
||||
CONFIG_MSM_SPM_V2=y
|
||||
CONFIG_ARM_THUMBEE=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_VMALLOC_RESERVE=0xC800000
|
||||
CONFIG_CP_ACCESS=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="init=/sbin/init root=/dev/ram rw initrd=0x11000000,16M console=ttyDCC0 mem=88M"
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_STAT_DETAILS=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
|
||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_WAKELOCK=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_IPV6_OPTIMISTIC_DAD=y
|
||||
CONFIG_INET6_AH=y
|
||||
CONFIG_INET6_ESP=y
|
||||
CONFIG_INET6_IPCOMP=y
|
||||
CONFIG_IPV6_MIP6=y
|
||||
CONFIG_IPV6_TUNNEL=y
|
||||
CONFIG_IPV6_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6_SUBTREES=y
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_NETFILTER_NETLINK_LOG=y
|
||||
CONFIG_NF_CONNTRACK=y
|
||||
CONFIG_NF_CONNTRACK_EVENTS=y
|
||||
CONFIG_NF_CT_PROTO_DCCP=y
|
||||
CONFIG_NF_CT_PROTO_SCTP=y
|
||||
CONFIG_NF_CT_PROTO_UDPLITE=y
|
||||
CONFIG_NF_CONNTRACK_AMANDA=y
|
||||
CONFIG_NF_CONNTRACK_FTP=y
|
||||
CONFIG_NF_CONNTRACK_H323=y
|
||||
CONFIG_NF_CONNTRACK_IRC=y
|
||||
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
|
||||
CONFIG_NF_CONNTRACK_PPTP=y
|
||||
CONFIG_NF_CONNTRACK_SANE=y
|
||||
CONFIG_NF_CONNTRACK_SIP=y
|
||||
CONFIG_NF_CONNTRACK_TFTP=y
|
||||
CONFIG_NF_CT_NETLINK=y
|
||||
CONFIG_NETFILTER_TPROXY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_LOG=y
|
||||
CONFIG_NETFILTER_XT_TARGET_MARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_HELPER=y
|
||||
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MAC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_POLICY=y
|
||||
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
|
||||
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STRING=y
|
||||
CONFIG_NETFILTER_XT_MATCH_TIME=y
|
||||
CONFIG_NETFILTER_XT_MATCH_U32=y
|
||||
CONFIG_NF_CONNTRACK_IPV4=y
|
||||
CONFIG_IP_NF_IPTABLES=y
|
||||
CONFIG_IP_NF_MATCH_AH=y
|
||||
CONFIG_IP_NF_MATCH_ECN=y
|
||||
CONFIG_IP_NF_MATCH_TTL=y
|
||||
CONFIG_IP_NF_FILTER=y
|
||||
CONFIG_IP_NF_TARGET_REJECT=y
|
||||
CONFIG_NF_NAT=y
|
||||
CONFIG_IP_NF_TARGET_MASQUERADE=y
|
||||
CONFIG_IP_NF_TARGET_NETMAP=y
|
||||
CONFIG_IP_NF_TARGET_REDIRECT=y
|
||||
CONFIG_IP_NF_MANGLE=y
|
||||
CONFIG_IP_NF_ARPTABLES=y
|
||||
CONFIG_IP_NF_ARPFILTER=y
|
||||
CONFIG_IP_NF_ARP_MANGLE=y
|
||||
CONFIG_IP6_NF_IPTABLES=y
|
||||
CONFIG_BT=y
|
||||
CONFIG_BT_RFCOMM=y
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_BNEP=y
|
||||
CONFIG_BT_BNEP_MC_FILTER=y
|
||||
CONFIG_BT_BNEP_PROTO_FILTER=y
|
||||
CONFIG_BT_HIDP=y
|
||||
CONFIG_BT_HCIUART=y
|
||||
CONFIG_BT_HCIUART_H4=y
|
||||
CONFIG_BT_HCIUART_IBS=y
|
||||
CONFIG_MSM_BT_POWER=y
|
||||
CONFIG_CFG80211=m
|
||||
# CONFIG_CFG80211_WEXT is not set
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_GENLOCK=y
|
||||
CONFIG_GENLOCK_MISCDEVICE=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_TESTS=m
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_TGT=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_SCH=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_MD=y
|
||||
CONFIG_BLK_DEV_DM=y
|
||||
CONFIG_DM_CRYPT=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_LIBRA_SDIOIF=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_EVBUG=m
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_TOUCHSCREEN_ATMEL_MAXTOUCH=y
|
||||
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
|
||||
CONFIG_TOUCHSCREEN_SYNAPTICS_RMI4_I2C=y
|
||||
CONFIG_TOUCHSCREEN_FT5X06=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
CONFIG_INPUT_GPIO=y
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_MSM=y
|
||||
CONFIG_SERIAL_MSM_CONSOLE=y
|
||||
CONFIG_SERIAL_MSM_HS=y
|
||||
# CONFIG_SERIAL_MSM_CLOCK_CONTROL is not set
|
||||
CONFIG_DIAG_CHAR=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_DCC_TTY=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_I2C_MSM is not set
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_SX150X=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_BATTERY_MSM=y
|
||||
CONFIG_SENSORS_MSM_ADC=y
|
||||
CONFIG_MARIMBA_CORE=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_MEDIA_CONTROLLER=y
|
||||
CONFIG_VIDEO_DEV=y
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
# CONFIG_RC_CORE is not set
|
||||
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
|
||||
CONFIG_VIDEOBUF2_MSM_MEM=y
|
||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
||||
CONFIG_MSM_CAMERA_V4L2=y
|
||||
CONFIG_OV5647=y
|
||||
CONFIG_OV8825=y
|
||||
CONFIG_AD5046_ACT=y
|
||||
CONFIG_WEBCAM_OV9726=y
|
||||
CONFIG_MT9E013=y
|
||||
CONFIG_S5K4E1=y
|
||||
CONFIG_DW9712_ACT=y
|
||||
CONFIG_MSM_CAMERA_FLASH_SC628A=y
|
||||
CONFIG_MSM_CAMERA_SENSOR=y
|
||||
CONFIG_MSM_ACTUATOR=y
|
||||
CONFIG_OV7692=y
|
||||
CONFIG_RADIO_TAVARUA=y
|
||||
CONFIG_MSM_KGSL=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_MSM=y
|
||||
# CONFIG_FB_MSM_BACKLIGHT is not set
|
||||
CONFIG_FB_MSM_TRIPLE_BUFFER=y
|
||||
CONFIG_FB_MSM_MDP30=y
|
||||
CONFIG_FB_MSM_MDP303=y
|
||||
CONFIG_FB_MSM_LCDC_TRULY_HVGA_IPS3P2335_PT_PANEL=y
|
||||
CONFIG_FB_MSM_MIPI_PANEL_DETECT=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_MSM_SOC=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_MAGICMOUSE=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_SUSPEND=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_EHSET=y
|
||||
CONFIG_USB_EHCI_ROOT_HUB_TT=y
|
||||
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
|
||||
CONFIG_USB_EHCI_MSM_72K=y
|
||||
CONFIG_USB_ACM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_STORAGE_DATAFAB=y
|
||||
CONFIG_USB_STORAGE_FREECOM=y
|
||||
CONFIG_USB_STORAGE_ISD200=y
|
||||
CONFIG_USB_STORAGE_USBAT=y
|
||||
CONFIG_USB_STORAGE_SDDR09=y
|
||||
CONFIG_USB_STORAGE_SDDR55=y
|
||||
CONFIG_USB_STORAGE_JUMPSHOT=y
|
||||
CONFIG_USB_STORAGE_ALAUDA=y
|
||||
CONFIG_USB_STORAGE_ONETOUCH=y
|
||||
CONFIG_USB_STORAGE_KARMA=y
|
||||
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
|
||||
CONFIG_USB_EHSET_TEST_FIXTURE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_MSM_72K=y
|
||||
CONFIG_USB_G_ANDROID=y
|
||||
CONFIG_RMNET_SMD_CTL_CHANNEL="DATA40_CNTL"
|
||||
CONFIG_RMNET_SMD_DATA_CHANNEL="DATA40"
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_PERF_PROFILING=y
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
CONFIG_MMC_CLKGATE=y
|
||||
CONFIG_MMC_PARANOID_SD_INIT=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
CONFIG_MMC_TEST=m
|
||||
CONFIG_MMC_MSM=y
|
||||
CONFIG_MMC_MSM_CARD_HW_DETECTION=y
|
||||
CONFIG_MMC_MSM_SDC3_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC3_8_BIT_SUPPORT=y
|
||||
CONFIG_LEDS_MSM_PDM=y
|
||||
CONFIG_LEDS_PMIC_MPP=y
|
||||
CONFIG_SWITCH=y
|
||||
CONFIG_SWITCH_GPIO=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_ANDROID_BINDER_IPC=y
|
||||
CONFIG_ANDROID_LOGGER=y
|
||||
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_YAFFS_FS=y
|
||||
CONFIG_YAFFS_DISABLE_TAGS_ECC=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_SHIRQ=y
|
||||
CONFIG_LOCKUP_DETECTOR=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_TIMER_STATS=y
|
||||
CONFIG_DEBUG_SLAB=y
|
||||
CONFIG_DEBUG_SLAB_LEAK=y
|
||||
CONFIG_DEBUG_SPINLOCK=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
CONFIG_DEBUG_ATOMIC_SLEEP=y
|
||||
CONFIG_DEBUG_STACK_USAGE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_LIST=y
|
||||
CONFIG_DEBUG_PAGEALLOC=y
|
||||
CONFIG_ENABLE_DEFAULT_TRACERS=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRC_CCITT=y
|
||||
378
arch/arm/configs/msm7630-perf_defconfig
Normal file
378
arch/arm/configs/msm7630-perf_defconfig
Normal file
@@ -0,0 +1,378 @@
|
||||
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_LOCALVERSION="-perf"
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_RESOURCE_COUNTERS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_RT_GROUP_SCHED=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_ASHMEM=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=m
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
CONFIG_ARCH_MSM=y
|
||||
CONFIG_ARCH_MSM7X30=y
|
||||
# CONFIG_MSM_STACKED_MEMORY is not set
|
||||
CONFIG_MSM_SMD=y
|
||||
CONFIG_MSM_SMD_PKG3=y
|
||||
CONFIG_MSM_SDIO_DMUX=y
|
||||
CONFIG_MSM_SDIO_CMUX=y
|
||||
CONFIG_MSM_SDIO_CTL=y
|
||||
CONFIG_MSM_ONCRPCROUTER=y
|
||||
CONFIG_MSM_RPC_WATCHDOG=y
|
||||
CONFIG_MSM_RMT_STORAGE_CLIENT=y
|
||||
# CONFIG_MSM_HW3D is not set
|
||||
# CONFIG_QSD_AUDIO is not set
|
||||
CONFIG_MSM_MEMORY_LOW_POWER_MODE=y
|
||||
CONFIG_MSM_MEMORY_LOW_POWER_MODE_IDLE_RETENTION=y
|
||||
CONFIG_MSM_MEMORY_LOW_POWER_MODE_SUSPEND_DEEP_POWER_DOWN=y
|
||||
CONFIG_MSM_IDLE_WAIT_ON_MODEM=2000
|
||||
CONFIG_MSM_STANDALONE_POWER_COLLAPSE=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_VMALLOC_RESERVE=0x1A000000
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="init=/sbin/init root=/dev/ram rw initrd=0x11000000,16M console=ttyDCC0 mem=88M ip=dhcp"
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_WAKELOCK=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_IPV6_OPTIMISTIC_DAD=y
|
||||
CONFIG_INET6_AH=y
|
||||
CONFIG_INET6_ESP=y
|
||||
CONFIG_INET6_IPCOMP=y
|
||||
CONFIG_IPV6_MIP6=y
|
||||
CONFIG_IPV6_TUNNEL=y
|
||||
CONFIG_IPV6_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6_SUBTREES=y
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_NF_CONNTRACK=y
|
||||
CONFIG_NF_CONNTRACK_EVENTS=y
|
||||
CONFIG_NF_CT_PROTO_DCCP=y
|
||||
CONFIG_NF_CT_PROTO_SCTP=y
|
||||
CONFIG_NF_CT_PROTO_UDPLITE=y
|
||||
CONFIG_NF_CONNTRACK_AMANDA=y
|
||||
CONFIG_NF_CONNTRACK_FTP=y
|
||||
CONFIG_NF_CONNTRACK_H323=y
|
||||
CONFIG_NF_CONNTRACK_IRC=y
|
||||
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
|
||||
CONFIG_NF_CONNTRACK_PPTP=y
|
||||
CONFIG_NF_CONNTRACK_SANE=y
|
||||
CONFIG_NF_CONNTRACK_SIP=y
|
||||
CONFIG_NF_CONNTRACK_TFTP=y
|
||||
CONFIG_NF_CT_NETLINK=y
|
||||
CONFIG_NETFILTER_TPROXY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_LOG=y
|
||||
CONFIG_NETFILTER_XT_TARGET_MARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
|
||||
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_HELPER=y
|
||||
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MAC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_POLICY=y
|
||||
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
|
||||
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STRING=y
|
||||
CONFIG_NETFILTER_XT_MATCH_TIME=y
|
||||
CONFIG_NETFILTER_XT_MATCH_U32=y
|
||||
CONFIG_NF_CONNTRACK_IPV4=y
|
||||
CONFIG_IP_NF_IPTABLES=y
|
||||
CONFIG_IP_NF_MATCH_AH=y
|
||||
CONFIG_IP_NF_MATCH_ECN=y
|
||||
CONFIG_IP_NF_MATCH_TTL=y
|
||||
CONFIG_IP_NF_FILTER=y
|
||||
CONFIG_IP_NF_TARGET_REJECT=y
|
||||
CONFIG_NF_NAT=y
|
||||
CONFIG_IP_NF_TARGET_MASQUERADE=y
|
||||
CONFIG_IP_NF_TARGET_NETMAP=y
|
||||
CONFIG_IP_NF_TARGET_REDIRECT=y
|
||||
CONFIG_IP_NF_MANGLE=y
|
||||
CONFIG_IP_NF_ARPTABLES=y
|
||||
CONFIG_IP_NF_ARPFILTER=y
|
||||
CONFIG_IP_NF_ARP_MANGLE=y
|
||||
CONFIG_IP6_NF_IPTABLES=y
|
||||
CONFIG_IP6_NF_FILTER=y
|
||||
CONFIG_IP6_NF_MANGLE=y
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_SCH_HTB=y
|
||||
CONFIG_NET_SCH_PRIO=y
|
||||
CONFIG_NET_SCH_SFQ=y
|
||||
CONFIG_NET_SCH_TBF=y
|
||||
CONFIG_NET_SCH_DSMARK=m
|
||||
CONFIG_NET_SCH_INGRESS=y
|
||||
CONFIG_NET_CLS_BASIC=y
|
||||
CONFIG_NET_CLS_TCINDEX=y
|
||||
CONFIG_NET_CLS_FW=y
|
||||
CONFIG_NET_CLS_U32=y
|
||||
CONFIG_CLS_U32_MARK=y
|
||||
CONFIG_NET_CLS_FLOW=m
|
||||
CONFIG_NET_EMATCH=y
|
||||
CONFIG_NET_CLS_ACT=y
|
||||
CONFIG_NET_ACT_MIRRED=y
|
||||
CONFIG_BT=y
|
||||
CONFIG_BT_RFCOMM=y
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_BNEP=y
|
||||
CONFIG_BT_BNEP_MC_FILTER=y
|
||||
CONFIG_BT_BNEP_PROTO_FILTER=y
|
||||
CONFIG_BT_HIDP=y
|
||||
CONFIG_BT_HCIUART=y
|
||||
CONFIG_BT_HCIUART_H4=y
|
||||
CONFIG_BT_HCIUART_IBS=y
|
||||
CONFIG_MSM_BT_POWER=y
|
||||
CONFIG_CFG80211=y
|
||||
# CONFIG_CFG80211_WEXT is not set
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_GENLOCK=y
|
||||
CONFIG_GENLOCK_MISCDEVICE=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_TESTS=m
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_COUNT=8
|
||||
CONFIG_BLK_DEV_RAM_SIZE=16384
|
||||
CONFIG_HAPTIC_ISA1200=y
|
||||
CONFIG_PMIC8XXX_UPL=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_TGT=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_SCH=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_MD=y
|
||||
CONFIG_BLK_DEV_DM=y
|
||||
CONFIG_DM_CRYPT=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_MSM_RMNET_SDIO=y
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_SLIP=y
|
||||
CONFIG_SLIP_COMPRESSED=y
|
||||
CONFIG_SLIP_MODE_SLIP6=y
|
||||
CONFIG_LIBRA_SDIOIF=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_EVBUG=m
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
CONFIG_KEYBOARD_PMIC8XXX=y
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_TOUCHSCREEN_MSM=y
|
||||
CONFIG_TOUCHSCREEN_TSC2007=y
|
||||
CONFIG_TOUCHSCREEN_CY8C_TS=y
|
||||
CONFIG_TOUCHSCREEN_CYTTSP_I2C_QC=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
CONFIG_INPUT_GPIO=y
|
||||
CONFIG_BOSCH_BMA150=y
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_MSM=y
|
||||
CONFIG_SERIAL_MSM_HS=y
|
||||
CONFIG_DIAG_CHAR=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_I2C_SSBI=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_QSD=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_BATTERY_MSM=y
|
||||
CONFIG_SENSORS_MSM_ADC=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_MSM_POPMEM=y
|
||||
CONFIG_PMIC8058=y
|
||||
CONFIG_MARIMBA_CORE=y
|
||||
CONFIG_MARIMBA_CODEC=y
|
||||
CONFIG_TIMPANI_CODEC=y
|
||||
# CONFIG_MFD_PM8XXX_DEBUG is not set
|
||||
# CONFIG_MFD_PM8XXX_PWM is not set
|
||||
# CONFIG_MFD_PM8XXX_MISC is not set
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_VIDEO_DEV=y
|
||||
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
|
||||
CONFIG_VIDEOBUF2_MSM_MEM=y
|
||||
CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
|
||||
CONFIG_RADIO_TAVARUA=y
|
||||
CONFIG_MSM_KGSL=y
|
||||
CONFIG_VIDEO_OUTPUT_CONTROL=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
CONFIG_FB_TILEBLITTING=y
|
||||
CONFIG_FB_MSM=y
|
||||
# CONFIG_FB_MSM_BACKLIGHT is not set
|
||||
CONFIG_FB_MSM_LOGO=y
|
||||
CONFIG_FB_MSM_TRIPLE_BUFFER=y
|
||||
CONFIG_FB_MSM_MDP40=y
|
||||
CONFIG_FB_MSM_OVERLAY=y
|
||||
CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y
|
||||
CONFIG_FB_MSM_TRY_MDDI_CATCH_LCDC_PRISM=y
|
||||
CONFIG_FB_MSM_HDMI_ADV7520_PANEL=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_LCD_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
# CONFIG_BACKLIGHT_GENERIC is not set
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
# CONFIG_SND_DRIVERS is not set
|
||||
# CONFIG_SND_ARM is not set
|
||||
# CONFIG_SND_SPI is not set
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_MSM7KV2_SOC=y
|
||||
CONFIG_SND_MVS_SOC=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_MAGICMOUSE=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_SUSPEND=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_EHSET=y
|
||||
CONFIG_USB_EHCI_ROOT_HUB_TT=y
|
||||
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
|
||||
CONFIG_USB_EHCI_MSM_72K=y
|
||||
CONFIG_USB_ACM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_STORAGE_DATAFAB=y
|
||||
CONFIG_USB_STORAGE_FREECOM=y
|
||||
CONFIG_USB_STORAGE_ISD200=y
|
||||
CONFIG_USB_STORAGE_USBAT=y
|
||||
CONFIG_USB_STORAGE_SDDR09=y
|
||||
CONFIG_USB_STORAGE_SDDR55=y
|
||||
CONFIG_USB_STORAGE_JUMPSHOT=y
|
||||
CONFIG_USB_STORAGE_ALAUDA=y
|
||||
CONFIG_USB_STORAGE_ONETOUCH=y
|
||||
CONFIG_USB_STORAGE_KARMA=y
|
||||
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
|
||||
CONFIG_USB_EHSET_TEST_FIXTURE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_MSM_72K=y
|
||||
CONFIG_USB_G_ANDROID=y
|
||||
CONFIG_RMNET_SMD_CTL_CHANNEL="DATA40_CNTL"
|
||||
CONFIG_RMNET_SMD_DATA_CHANNEL="DATA40"
|
||||
CONFIG_RMNET_SDIO_SMD_DATA_CHANNEL=""
|
||||
CONFIG_USB_MSM_ACA=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_PERF_PROFILING=y
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
CONFIG_MMC_CLKGATE=y
|
||||
CONFIG_MMC_PARANOID_SD_INIT=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
CONFIG_MMC_TEST=m
|
||||
CONFIG_MMC_MSM=y
|
||||
CONFIG_MMC_MSM_CARD_HW_DETECTION=y
|
||||
# CONFIG_MMC_MSM_SDC1_SUPPORT is not set
|
||||
CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC3_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC4_SUPPORT=y
|
||||
CONFIG_LEDS_PMIC8058=y
|
||||
CONFIG_SWITCH=y
|
||||
CONFIG_SWITCH_GPIO=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DEBUG=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_ANDROID_BINDER_IPC=y
|
||||
CONFIG_ANDROID_LOGGER=y
|
||||
CONFIG_ANDROID_RAM_CONSOLE=y
|
||||
CONFIG_ANDROID_TIMED_GPIO=y
|
||||
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
|
||||
CONFIG_MSM_SSBI=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_YAFFS_FS=y
|
||||
CONFIG_YAFFS_DISABLE_TAGS_ECC=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_TIMER_STATS=y
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRYPTO_DEV_QCRYPTO=m
|
||||
CONFIG_CRYPTO_DEV_QCE=m
|
||||
CONFIG_CRYPTO_DEV_QCEDEV=m
|
||||
CONFIG_CRC_CCITT=y
|
||||
386
arch/arm/configs/msm7630_defconfig
Normal file
386
arch/arm/configs/msm7630_defconfig
Normal file
@@ -0,0 +1,386 @@
|
||||
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_DEBUG=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_RESOURCE_COUNTERS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_RT_GROUP_SCHED=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_ASHMEM=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=m
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
CONFIG_ARCH_MSM=y
|
||||
CONFIG_ARCH_MSM7X30=y
|
||||
# CONFIG_MSM_STACKED_MEMORY is not set
|
||||
CONFIG_MSM_SMD=y
|
||||
CONFIG_MSM_SMD_PKG3=y
|
||||
CONFIG_MSM_SDIO_DMUX=y
|
||||
CONFIG_MSM_SDIO_CMUX=y
|
||||
CONFIG_MSM_SDIO_CTL=y
|
||||
CONFIG_MSM_ONCRPCROUTER=y
|
||||
CONFIG_MSM_RPC_WATCHDOG=y
|
||||
CONFIG_MSM_RMT_STORAGE_CLIENT=y
|
||||
# CONFIG_MSM_HW3D is not set
|
||||
# CONFIG_QSD_AUDIO is not set
|
||||
CONFIG_MSM_MEMORY_LOW_POWER_MODE=y
|
||||
CONFIG_MSM_MEMORY_LOW_POWER_MODE_IDLE_RETENTION=y
|
||||
CONFIG_MSM_MEMORY_LOW_POWER_MODE_SUSPEND_DEEP_POWER_DOWN=y
|
||||
CONFIG_MSM_IDLE_WAIT_ON_MODEM=2000
|
||||
CONFIG_MSM_STANDALONE_POWER_COLLAPSE=y
|
||||
CONFIG_STRICT_MEMORY_RWX=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_VMALLOC_RESERVE=0x1A000000
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="init=/sbin/init root=/dev/ram rw initrd=0x11000000,16M console=ttyDCC0 mem=88M ip=dhcp"
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_WAKELOCK=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_IPV6_OPTIMISTIC_DAD=y
|
||||
CONFIG_INET6_AH=y
|
||||
CONFIG_INET6_ESP=y
|
||||
CONFIG_INET6_IPCOMP=y
|
||||
CONFIG_IPV6_MIP6=y
|
||||
CONFIG_IPV6_TUNNEL=y
|
||||
CONFIG_IPV6_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6_SUBTREES=y
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_NF_CONNTRACK=y
|
||||
CONFIG_NF_CONNTRACK_EVENTS=y
|
||||
CONFIG_NF_CT_PROTO_DCCP=y
|
||||
CONFIG_NF_CT_PROTO_SCTP=y
|
||||
CONFIG_NF_CT_PROTO_UDPLITE=y
|
||||
CONFIG_NF_CONNTRACK_AMANDA=y
|
||||
CONFIG_NF_CONNTRACK_FTP=y
|
||||
CONFIG_NF_CONNTRACK_H323=y
|
||||
CONFIG_NF_CONNTRACK_IRC=y
|
||||
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
|
||||
CONFIG_NF_CONNTRACK_PPTP=y
|
||||
CONFIG_NF_CONNTRACK_SANE=y
|
||||
CONFIG_NF_CONNTRACK_SIP=y
|
||||
CONFIG_NF_CONNTRACK_TFTP=y
|
||||
CONFIG_NF_CT_NETLINK=y
|
||||
CONFIG_NETFILTER_TPROXY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_LOG=y
|
||||
CONFIG_NETFILTER_XT_TARGET_MARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
|
||||
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_HELPER=y
|
||||
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MAC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_POLICY=y
|
||||
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
|
||||
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STRING=y
|
||||
CONFIG_NETFILTER_XT_MATCH_TIME=y
|
||||
CONFIG_NETFILTER_XT_MATCH_U32=y
|
||||
CONFIG_NF_CONNTRACK_IPV4=y
|
||||
CONFIG_IP_NF_IPTABLES=y
|
||||
CONFIG_IP_NF_MATCH_AH=y
|
||||
CONFIG_IP_NF_MATCH_ECN=y
|
||||
CONFIG_IP_NF_MATCH_TTL=y
|
||||
CONFIG_IP_NF_FILTER=y
|
||||
CONFIG_IP_NF_TARGET_REJECT=y
|
||||
CONFIG_NF_NAT=y
|
||||
CONFIG_IP_NF_TARGET_MASQUERADE=y
|
||||
CONFIG_IP_NF_TARGET_NETMAP=y
|
||||
CONFIG_IP_NF_TARGET_REDIRECT=y
|
||||
CONFIG_IP_NF_MANGLE=y
|
||||
CONFIG_IP_NF_ARPTABLES=y
|
||||
CONFIG_IP_NF_ARPFILTER=y
|
||||
CONFIG_IP_NF_ARP_MANGLE=y
|
||||
CONFIG_IP6_NF_IPTABLES=y
|
||||
CONFIG_IP6_NF_FILTER=y
|
||||
CONFIG_IP6_NF_MANGLE=y
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_SCH_HTB=y
|
||||
CONFIG_NET_SCH_PRIO=y
|
||||
CONFIG_NET_SCH_SFQ=y
|
||||
CONFIG_NET_SCH_TBF=y
|
||||
CONFIG_NET_SCH_DSMARK=m
|
||||
CONFIG_NET_SCH_INGRESS=y
|
||||
CONFIG_NET_CLS_BASIC=y
|
||||
CONFIG_NET_CLS_TCINDEX=y
|
||||
CONFIG_NET_CLS_FW=y
|
||||
CONFIG_NET_CLS_U32=y
|
||||
CONFIG_CLS_U32_MARK=y
|
||||
CONFIG_NET_CLS_FLOW=m
|
||||
CONFIG_NET_EMATCH=y
|
||||
CONFIG_NET_CLS_ACT=y
|
||||
CONFIG_NET_ACT_MIRRED=y
|
||||
CONFIG_BT=y
|
||||
CONFIG_BT_RFCOMM=y
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_BNEP=y
|
||||
CONFIG_BT_BNEP_MC_FILTER=y
|
||||
CONFIG_BT_BNEP_PROTO_FILTER=y
|
||||
CONFIG_BT_HIDP=y
|
||||
CONFIG_BT_HCIUART=y
|
||||
CONFIG_BT_HCIUART_H4=y
|
||||
CONFIG_BT_HCIUART_IBS=y
|
||||
CONFIG_MSM_BT_POWER=y
|
||||
CONFIG_CFG80211=y
|
||||
# CONFIG_CFG80211_WEXT is not set
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_GENLOCK=y
|
||||
CONFIG_GENLOCK_MISCDEVICE=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_TESTS=m
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_COUNT=8
|
||||
CONFIG_BLK_DEV_RAM_SIZE=16384
|
||||
CONFIG_HAPTIC_ISA1200=y
|
||||
CONFIG_PMIC8XXX_UPL=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_TGT=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_SCH=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_MD=y
|
||||
CONFIG_BLK_DEV_DM=y
|
||||
CONFIG_DM_CRYPT=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_MSM_RMNET_SDIO=y
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_SLIP=y
|
||||
CONFIG_SLIP_COMPRESSED=y
|
||||
CONFIG_SLIP_MODE_SLIP6=y
|
||||
CONFIG_LIBRA_SDIOIF=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_EVBUG=m
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
CONFIG_KEYBOARD_PMIC8XXX=y
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_TOUCHSCREEN_MSM=y
|
||||
CONFIG_TOUCHSCREEN_TSC2007=y
|
||||
CONFIG_TOUCHSCREEN_CY8C_TS=y
|
||||
CONFIG_TOUCHSCREEN_CYTTSP_I2C_QC=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
CONFIG_INPUT_GPIO=y
|
||||
CONFIG_BOSCH_BMA150=y
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_MSM=y
|
||||
CONFIG_SERIAL_MSM_HS=y
|
||||
CONFIG_DIAG_CHAR=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_DCC_TTY=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_I2C_SSBI=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_QSD=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_BATTERY_MSM=y
|
||||
CONFIG_SENSORS_MSM_ADC=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_MSM_POPMEM=y
|
||||
CONFIG_PMIC8058=y
|
||||
CONFIG_MARIMBA_CORE=y
|
||||
CONFIG_MARIMBA_CODEC=y
|
||||
CONFIG_TIMPANI_CODEC=y
|
||||
# CONFIG_MFD_PM8XXX_DEBUG is not set
|
||||
# CONFIG_MFD_PM8XXX_PWM is not set
|
||||
# CONFIG_MFD_PM8XXX_MISC is not set
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_VIDEO_DEV=y
|
||||
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
|
||||
CONFIG_VIDEOBUF2_MSM_MEM=y
|
||||
CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
|
||||
CONFIG_RADIO_TAVARUA=y
|
||||
CONFIG_MSM_KGSL=y
|
||||
CONFIG_VIDEO_OUTPUT_CONTROL=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
CONFIG_FB_TILEBLITTING=y
|
||||
CONFIG_FB_MSM=y
|
||||
# CONFIG_FB_MSM_BACKLIGHT is not set
|
||||
CONFIG_FB_MSM_LOGO=y
|
||||
CONFIG_FB_MSM_TRIPLE_BUFFER=y
|
||||
CONFIG_FB_MSM_MDP40=y
|
||||
CONFIG_FB_MSM_OVERLAY=y
|
||||
CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y
|
||||
CONFIG_FB_MSM_TRY_MDDI_CATCH_LCDC_PRISM=y
|
||||
CONFIG_FB_MSM_HDMI_ADV7520_PANEL=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_LCD_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
# CONFIG_BACKLIGHT_GENERIC is not set
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
# CONFIG_SND_DRIVERS is not set
|
||||
# CONFIG_SND_ARM is not set
|
||||
# CONFIG_SND_SPI is not set
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_MSM7KV2_SOC=y
|
||||
CONFIG_SND_MVS_SOC=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_SUSPEND=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_EHSET=y
|
||||
CONFIG_USB_EHCI_ROOT_HUB_TT=y
|
||||
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
|
||||
CONFIG_USB_EHCI_MSM_72K=y
|
||||
CONFIG_USB_ACM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_STORAGE_DATAFAB=y
|
||||
CONFIG_USB_STORAGE_FREECOM=y
|
||||
CONFIG_USB_STORAGE_ISD200=y
|
||||
CONFIG_USB_STORAGE_USBAT=y
|
||||
CONFIG_USB_STORAGE_SDDR09=y
|
||||
CONFIG_USB_STORAGE_SDDR55=y
|
||||
CONFIG_USB_STORAGE_JUMPSHOT=y
|
||||
CONFIG_USB_STORAGE_ALAUDA=y
|
||||
CONFIG_USB_STORAGE_ONETOUCH=y
|
||||
CONFIG_USB_STORAGE_KARMA=y
|
||||
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
|
||||
CONFIG_USB_EHSET_TEST_FIXTURE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_MSM_72K=y
|
||||
CONFIG_USB_G_ANDROID=y
|
||||
CONFIG_RMNET_SMD_CTL_CHANNEL="DATA40_CNTL"
|
||||
CONFIG_RMNET_SMD_DATA_CHANNEL="DATA40"
|
||||
CONFIG_RMNET_SDIO_SMD_DATA_CHANNEL=""
|
||||
CONFIG_USB_MSM_ACA=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_PERF_PROFILING=y
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
CONFIG_MMC_CLKGATE=y
|
||||
CONFIG_MMC_PARANOID_SD_INIT=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
CONFIG_MMC_TEST=m
|
||||
CONFIG_MMC_MSM=y
|
||||
CONFIG_MMC_MSM_CARD_HW_DETECTION=y
|
||||
# CONFIG_MMC_MSM_SDC1_SUPPORT is not set
|
||||
CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC3_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC4_SUPPORT=y
|
||||
CONFIG_LEDS_PMIC8058=y
|
||||
CONFIG_SWITCH=y
|
||||
CONFIG_SWITCH_GPIO=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DEBUG=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_ANDROID_BINDER_IPC=y
|
||||
CONFIG_ANDROID_LOGGER=y
|
||||
CONFIG_ANDROID_RAM_CONSOLE=y
|
||||
CONFIG_ANDROID_TIMED_GPIO=y
|
||||
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
|
||||
CONFIG_MSM_SSBI=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_YAFFS_FS=y
|
||||
CONFIG_YAFFS_DISABLE_TAGS_ECC=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_LOCKUP_DETECTOR=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_SCHEDSTATS=y
|
||||
CONFIG_TIMER_STATS=y
|
||||
CONFIG_DEBUG_SLAB=y
|
||||
CONFIG_DEBUG_SLAB_LEAK=y
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
CONFIG_PROVE_LOCKING=y
|
||||
CONFIG_DEBUG_ATOMIC_SLEEP=y
|
||||
CONFIG_DEBUG_STACK_USAGE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_LIST=y
|
||||
CONFIG_DEBUG_PAGEALLOC=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRYPTO_DEV_QCRYPTO=m
|
||||
CONFIG_CRYPTO_DEV_QCE=m
|
||||
CONFIG_CRYPTO_DEV_QCEDEV=m
|
||||
CONFIG_CRC_CCITT=y
|
||||
450
arch/arm/configs/msm8660-perf_defconfig
Normal file
450
arch/arm/configs/msm8660-perf_defconfig
Normal file
@@ -0,0 +1,450 @@
|
||||
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_LOCALVERSION="-perf"
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_RESOURCE_COUNTERS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_RT_GROUP_SCHED=y
|
||||
CONFIG_NAMESPACES=y
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_USER_NS is not set
|
||||
# CONFIG_PID_NS is not set
|
||||
# CONFIG_NET_NS is not set
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_PANIC_TIMEOUT=5
|
||||
CONFIG_ASHMEM=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_SLUB_DEBUG is not set
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=y
|
||||
CONFIG_KPROBES=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_DEFAULT_DEADLINE=y
|
||||
CONFIG_ARCH_MSM=y
|
||||
CONFIG_ARCH_MSM8X60=y
|
||||
CONFIG_MACH_MSM8X60_RUMI3=y
|
||||
CONFIG_MACH_MSM8X60_SIM=y
|
||||
CONFIG_MACH_MSM8X60_SURF=y
|
||||
CONFIG_MACH_MSM8X60_FFA=y
|
||||
CONFIG_MACH_MSM8X60_FLUID=y
|
||||
CONFIG_MACH_MSM8X60_FUSION=y
|
||||
CONFIG_MACH_MSM8X60_FUSN_FFA=y
|
||||
CONFIG_MACH_MSM8X60_DRAGON=y
|
||||
CONFIG_MSM7X00A_USE_DG_TIMER=y
|
||||
CONFIG_MSM7X00A_SLEEP_MODE_POWER_COLLAPSE=y
|
||||
CONFIG_MSM7X00A_IDLE_SLEEP_WAIT_FOR_INTERRUPT=y
|
||||
# CONFIG_MSM_FIQ_SUPPORT is not set
|
||||
# CONFIG_MSM_PROC_COMM is not set
|
||||
CONFIG_MSM_SMD=y
|
||||
CONFIG_MSM_SDIO_DMUX=y
|
||||
# CONFIG_MSM_RESET_MODEM is not set
|
||||
# CONFIG_MSM_SMD_NMEA is not set
|
||||
CONFIG_MSM_SDIO_TTY=y
|
||||
# CONFIG_MSM_SMD_QMI is not set
|
||||
CONFIG_MSM_SDIO_CMUX=y
|
||||
CONFIG_MSM_DSPS=y
|
||||
CONFIG_MSM_SDIO_CTL=y
|
||||
CONFIG_MSM_ONCRPCROUTER=y
|
||||
# CONFIG_MSM_RPCSERVER_TIME_REMOTE is not set
|
||||
# CONFIG_MSM_RPCSERVER_WATCHDOG is not set
|
||||
# CONFIG_MSM_RPCSERVER_HANDSET is not set
|
||||
CONFIG_MSM_RMT_STORAGE_CLIENT=y
|
||||
CONFIG_MSM_SDIO_SMEM=y
|
||||
# CONFIG_MSM_HW3D is not set
|
||||
CONFIG_MSM_PIL_MODEM=y
|
||||
CONFIG_MSM_PIL_QDSP6V3=y
|
||||
CONFIG_MSM_PIL_TZAPPS=y
|
||||
CONFIG_MSM_PIL_DSPS=y
|
||||
CONFIG_MSM_SUBSYSTEM_RESTART=y
|
||||
CONFIG_MSM_TZ_LOG=y
|
||||
CONFIG_MSM_RPM_LOG=y
|
||||
CONFIG_MSM_RPM_STATS_LOG=y
|
||||
CONFIG_MSM_WATCHDOG=y
|
||||
CONFIG_MSM_DLOAD_MODE=y
|
||||
CONFIG_MSM_ETM=y
|
||||
CONFIG_MSM_GSBI9_UART=y
|
||||
CONFIG_STRICT_MEMORY_RWX=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_VMALLOC_RESERVE=0x19000000
|
||||
CONFIG_CP_ACCESS=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_WAKELOCK=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_IPV6_OPTIMISTIC_DAD=y
|
||||
CONFIG_INET6_AH=y
|
||||
CONFIG_INET6_ESP=y
|
||||
CONFIG_INET6_IPCOMP=y
|
||||
CONFIG_IPV6_MIP6=y
|
||||
CONFIG_IPV6_TUNNEL=y
|
||||
CONFIG_IPV6_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6_SUBTREES=y
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_NF_CONNTRACK=y
|
||||
CONFIG_NF_CONNTRACK_EVENTS=y
|
||||
CONFIG_NF_CT_PROTO_DCCP=y
|
||||
CONFIG_NF_CT_PROTO_SCTP=y
|
||||
CONFIG_NF_CT_PROTO_UDPLITE=y
|
||||
CONFIG_NF_CONNTRACK_AMANDA=y
|
||||
CONFIG_NF_CONNTRACK_FTP=y
|
||||
CONFIG_NF_CONNTRACK_H323=y
|
||||
CONFIG_NF_CONNTRACK_IRC=y
|
||||
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
|
||||
CONFIG_NF_CONNTRACK_PPTP=y
|
||||
CONFIG_NF_CONNTRACK_SANE=y
|
||||
CONFIG_NF_CONNTRACK_SIP=y
|
||||
CONFIG_NF_CONNTRACK_TFTP=y
|
||||
CONFIG_NF_CT_NETLINK=y
|
||||
CONFIG_NETFILTER_TPROXY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_LOG=y
|
||||
CONFIG_NETFILTER_XT_TARGET_MARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
|
||||
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_HELPER=y
|
||||
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MAC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_POLICY=y
|
||||
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
|
||||
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STRING=y
|
||||
CONFIG_NETFILTER_XT_MATCH_TIME=y
|
||||
CONFIG_NETFILTER_XT_MATCH_U32=y
|
||||
CONFIG_NF_CONNTRACK_IPV4=y
|
||||
CONFIG_IP_NF_IPTABLES=y
|
||||
CONFIG_IP_NF_MATCH_AH=y
|
||||
CONFIG_IP_NF_MATCH_ECN=y
|
||||
CONFIG_IP_NF_MATCH_TTL=y
|
||||
CONFIG_IP_NF_FILTER=y
|
||||
CONFIG_IP_NF_TARGET_REJECT=y
|
||||
CONFIG_NF_NAT=y
|
||||
CONFIG_IP_NF_TARGET_MASQUERADE=y
|
||||
CONFIG_IP_NF_TARGET_NETMAP=y
|
||||
CONFIG_IP_NF_TARGET_REDIRECT=y
|
||||
CONFIG_IP_NF_MANGLE=y
|
||||
CONFIG_IP_NF_ARPTABLES=y
|
||||
CONFIG_IP_NF_ARPFILTER=y
|
||||
CONFIG_IP_NF_ARP_MANGLE=y
|
||||
CONFIG_IP6_NF_IPTABLES=y
|
||||
CONFIG_IP6_NF_FILTER=y
|
||||
CONFIG_IP6_NF_MANGLE=y
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_SCH_HTB=y
|
||||
CONFIG_NET_SCH_PRIO=y
|
||||
CONFIG_NET_SCH_SFQ=y
|
||||
CONFIG_NET_SCH_TBF=y
|
||||
CONFIG_NET_SCH_DSMARK=m
|
||||
CONFIG_NET_SCH_INGRESS=y
|
||||
CONFIG_NET_CLS_BASIC=y
|
||||
CONFIG_NET_CLS_TCINDEX=y
|
||||
CONFIG_NET_CLS_FW=y
|
||||
CONFIG_NET_CLS_U32=y
|
||||
CONFIG_CLS_U32_MARK=y
|
||||
CONFIG_NET_CLS_FLOW=m
|
||||
CONFIG_NET_EMATCH=y
|
||||
CONFIG_NET_EMATCH_CMP=y
|
||||
CONFIG_NET_EMATCH_NBYTE=y
|
||||
CONFIG_NET_EMATCH_U32=y
|
||||
CONFIG_NET_EMATCH_META=y
|
||||
CONFIG_NET_EMATCH_TEXT=y
|
||||
CONFIG_NET_CLS_ACT=y
|
||||
CONFIG_NET_ACT_MIRRED=y
|
||||
CONFIG_BT=y
|
||||
CONFIG_BT_RFCOMM=y
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_BNEP=y
|
||||
CONFIG_BT_BNEP_MC_FILTER=y
|
||||
CONFIG_BT_BNEP_PROTO_FILTER=y
|
||||
CONFIG_BT_HIDP=y
|
||||
CONFIG_BT_HCIUART=y
|
||||
CONFIG_BT_HCIUART_H4=y
|
||||
CONFIG_BT_HCIUART_IBS=y
|
||||
CONFIG_MSM_BT_POWER=y
|
||||
CONFIG_CFG80211=y
|
||||
# CONFIG_CFG80211_WEXT is not set
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_GENLOCK=y
|
||||
CONFIG_GENLOCK_MISCDEVICE=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_UID_STAT=y
|
||||
CONFIG_TSIF=m
|
||||
CONFIG_TSIF_CHRDEV=m
|
||||
CONFIG_HAPTIC_ISA1200=y
|
||||
CONFIG_PMIC8XXX_VIBRATOR=y
|
||||
CONFIG_PMIC8XXX_UPL=y
|
||||
CONFIG_PMIC8058_XOADC=y
|
||||
CONFIG_QSEECOM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_TGT=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_SCH=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_MD=y
|
||||
CONFIG_BLK_DEV_DM=y
|
||||
CONFIG_DM_CRYPT=y
|
||||
CONFIG_DM_UEVENT=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_MSM_RMNET_SDIO=y
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMC911X=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_PPP=y
|
||||
CONFIG_PPP_BSDCOMP=y
|
||||
CONFIG_PPP_DEFLATE=y
|
||||
CONFIG_PPP_ASYNC=y
|
||||
CONFIG_SLIP=y
|
||||
CONFIG_SLIP_COMPRESSED=y
|
||||
CONFIG_SLIP_MODE_SLIP6=y
|
||||
CONFIG_LIBRA_SDIOIF=m
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_EVBUG=m
|
||||
CONFIG_INPUT_KEYRESET=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_KEYBOARD_MATRIX=y
|
||||
CONFIG_KEYBOARD_PMIC8XXX=y
|
||||
CONFIG_INPUT_JOYSTICK=y
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_TOUCHSCREEN_CY8C_TS=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_PMIC8XXX_PWRKEY=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
CONFIG_PMIC8058_OTHC=y
|
||||
CONFIG_SERIAL_MSM_HS=y
|
||||
CONFIG_SERIAL_MSM_HSL=y
|
||||
CONFIG_SERIAL_MSM_HSL_CONSOLE=y
|
||||
CONFIG_DIAG_CHAR=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_MSM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_I2C_MSM is not set
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_I2C_SSBI=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_QUP=y
|
||||
CONFIG_SPI_SPIDEV=m
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_SX150X=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
# CONFIG_BATTERY_MSM is not set
|
||||
CONFIG_BATTERY_MSM8X60=y
|
||||
CONFIG_PM8058_CHARGER=y
|
||||
CONFIG_ISL9519_CHARGER=y
|
||||
CONFIG_SMB137B_CHARGER=y
|
||||
CONFIG_BATTERY_BQ27520=y
|
||||
CONFIG_BATTERY_BQ27541=y
|
||||
CONFIG_SENSORS_MSM_ADC=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_TSENS=y
|
||||
CONFIG_THERMAL_PM8XXX=y
|
||||
CONFIG_PMIC8058=y
|
||||
CONFIG_PMIC8901=y
|
||||
CONFIG_MARIMBA_CORE=y
|
||||
CONFIG_TIMPANI_CODEC=y
|
||||
# CONFIG_MFD_PM8XXX_PWM is not set
|
||||
CONFIG_MFD_PM8XXX_BATT_ALARM=y
|
||||
CONFIG_REGULATOR_MSM_GPIO=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_MEDIA_CONTROLLER=y
|
||||
CONFIG_VIDEO_DEV=y
|
||||
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
|
||||
CONFIG_VIDEOBUF2_MSM_MEM=y
|
||||
CONFIG_USB_VIDEO_CLASS=y
|
||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
||||
CONFIG_MSM_CAMERA_V4L2=y
|
||||
CONFIG_IMX074=y
|
||||
CONFIG_WEBCAM_OV9726=y
|
||||
CONFIG_MT9E013=y
|
||||
CONFIG_IMX074_ACT=y
|
||||
CONFIG_MSM_CAMERA_SENSOR=y
|
||||
CONFIG_MSM_ACTUATOR=y
|
||||
CONFIG_MSM_GEMINI=y
|
||||
CONFIG_OV7692=y
|
||||
CONFIG_RADIO_TAVARUA=y
|
||||
CONFIG_ION=y
|
||||
CONFIG_ION_MSM=y
|
||||
CONFIG_MSM_KGSL=y
|
||||
CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y
|
||||
CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=24
|
||||
CONFIG_VIDEO_OUTPUT_CONTROL=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_MSM=y
|
||||
# CONFIG_FB_MSM_BACKLIGHT is not set
|
||||
CONFIG_FB_MSM_TRIPLE_BUFFER=y
|
||||
CONFIG_FB_MSM_MDP40=y
|
||||
CONFIG_FB_MSM_OVERLAY=y
|
||||
CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y
|
||||
CONFIG_FB_MSM_OVERLAY1_WRITEBACK=y
|
||||
CONFIG_FB_MSM_WRITEBACK_MSM_PANEL=y
|
||||
CONFIG_FB_MSM_LCDC_MIPI_PANEL_AUTO_DETECT=y
|
||||
CONFIG_FB_MSM_HDMI_MSM_PANEL=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_USB_AUDIO=y
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_MAGICMOUSE=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_SUSPEND=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_EHSET=y
|
||||
CONFIG_USB_EHCI_ROOT_HUB_TT=y
|
||||
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
|
||||
CONFIG_USB_EHCI_MSM_72K=y
|
||||
CONFIG_USB_ACM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_STORAGE_DATAFAB=y
|
||||
CONFIG_USB_STORAGE_FREECOM=y
|
||||
CONFIG_USB_STORAGE_ISD200=y
|
||||
CONFIG_USB_STORAGE_USBAT=y
|
||||
CONFIG_USB_STORAGE_SDDR09=y
|
||||
CONFIG_USB_STORAGE_SDDR55=y
|
||||
CONFIG_USB_STORAGE_JUMPSHOT=y
|
||||
CONFIG_USB_STORAGE_ALAUDA=y
|
||||
CONFIG_USB_STORAGE_ONETOUCH=y
|
||||
CONFIG_USB_STORAGE_KARMA=y
|
||||
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
|
||||
CONFIG_USB_EHSET_TEST_FIXTURE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_MSM_72K=y
|
||||
CONFIG_USB_G_ANDROID=y
|
||||
CONFIG_RMNET_SMD_CTL_CHANNEL="DATA40_CNTL"
|
||||
CONFIG_RMNET_SMD_DATA_CHANNEL="DATA40"
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_PERF_PROFILING=y
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
CONFIG_MMC_CLKGATE=y
|
||||
CONFIG_MMC_EMBEDDED_SDIO=y
|
||||
CONFIG_MMC_PARANOID_SD_INIT=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
CONFIG_MMC_TEST=m
|
||||
CONFIG_MMC_MSM=y
|
||||
CONFIG_MMC_MSM_CARD_HW_DETECTION=y
|
||||
CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC3_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC3_8_BIT_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC4_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC5_SUPPORT=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_PMIC8058=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_TIMER=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_LEDS_TRIGGER_SLEEP=y
|
||||
CONFIG_SWITCH=y
|
||||
CONFIG_SWITCH_GPIO=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_DRV_MSM is not set
|
||||
CONFIG_RTC_DRV_PM8XXX=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_ANDROID_BINDER_IPC=y
|
||||
CONFIG_ANDROID_LOGGER=y
|
||||
CONFIG_ANDROID_RAM_CONSOLE=y
|
||||
CONFIG_ANDROID_TIMED_GPIO=y
|
||||
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
|
||||
CONFIG_MSM_SSBI=y
|
||||
CONFIG_MSM_IOMMU=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_CIFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_TIMER_STATS=y
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_ENABLE_DEFAULT_TRACERS=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRYPTO_DEV_QCRYPTO=m
|
||||
CONFIG_CRYPTO_DEV_QCE=m
|
||||
CONFIG_CRYPTO_DEV_QCEDEV=m
|
||||
462
arch/arm/configs/msm8660_defconfig
Normal file
462
arch/arm/configs/msm8660_defconfig
Normal file
@@ -0,0 +1,462 @@
|
||||
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_DEBUG=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_RESOURCE_COUNTERS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_RT_GROUP_SCHED=y
|
||||
CONFIG_NAMESPACES=y
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_USER_NS is not set
|
||||
# CONFIG_PID_NS is not set
|
||||
# CONFIG_NET_NS is not set
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_PANIC_TIMEOUT=5
|
||||
CONFIG_ASHMEM=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=y
|
||||
CONFIG_KPROBES=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_DEFAULT_DEADLINE=y
|
||||
CONFIG_ARCH_MSM=y
|
||||
CONFIG_ARCH_MSM8X60=y
|
||||
CONFIG_MACH_MSM8X60_RUMI3=y
|
||||
CONFIG_MACH_MSM8X60_SIM=y
|
||||
CONFIG_MACH_MSM8X60_SURF=y
|
||||
CONFIG_MACH_MSM8X60_FFA=y
|
||||
CONFIG_MACH_MSM8X60_FLUID=y
|
||||
CONFIG_MACH_MSM8X60_FUSION=y
|
||||
CONFIG_MACH_MSM8X60_FUSN_FFA=y
|
||||
CONFIG_MACH_MSM8X60_DRAGON=y
|
||||
CONFIG_MSM7X00A_USE_DG_TIMER=y
|
||||
CONFIG_MSM7X00A_SLEEP_MODE_POWER_COLLAPSE=y
|
||||
CONFIG_MSM7X00A_IDLE_SLEEP_WAIT_FOR_INTERRUPT=y
|
||||
# CONFIG_MSM_FIQ_SUPPORT is not set
|
||||
# CONFIG_MSM_PROC_COMM is not set
|
||||
CONFIG_MSM_SMD=y
|
||||
CONFIG_MSM_SDIO_DMUX=y
|
||||
# CONFIG_MSM_RESET_MODEM is not set
|
||||
# CONFIG_MSM_SMD_NMEA is not set
|
||||
CONFIG_MSM_SDIO_TTY=y
|
||||
# CONFIG_MSM_SMD_QMI is not set
|
||||
CONFIG_MSM_SDIO_CMUX=y
|
||||
CONFIG_MSM_DSPS=y
|
||||
CONFIG_MSM_SDIO_CTL=y
|
||||
CONFIG_MSM_ONCRPCROUTER=y
|
||||
# CONFIG_MSM_RPCSERVER_TIME_REMOTE is not set
|
||||
# CONFIG_MSM_RPCSERVER_WATCHDOG is not set
|
||||
# CONFIG_MSM_RPCSERVER_HANDSET is not set
|
||||
CONFIG_MSM_RMT_STORAGE_CLIENT=y
|
||||
CONFIG_MSM_SDIO_SMEM=y
|
||||
# CONFIG_MSM_HW3D is not set
|
||||
CONFIG_MSM_PIL_MODEM=y
|
||||
CONFIG_MSM_PIL_QDSP6V3=y
|
||||
CONFIG_MSM_PIL_TZAPPS=y
|
||||
CONFIG_MSM_PIL_DSPS=y
|
||||
CONFIG_MSM_SUBSYSTEM_RESTART=y
|
||||
CONFIG_MSM_TZ_LOG=y
|
||||
CONFIG_MSM_RPM_LOG=y
|
||||
CONFIG_MSM_RPM_STATS_LOG=y
|
||||
CONFIG_MSM_WATCHDOG=y
|
||||
CONFIG_MSM_DLOAD_MODE=y
|
||||
CONFIG_MSM_ETM=y
|
||||
CONFIG_MSM_SLEEP_STATS=y
|
||||
CONFIG_MSM_GSBI9_UART=y
|
||||
CONFIG_STRICT_MEMORY_RWX=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_VMALLOC_RESERVE=0x19000000
|
||||
CONFIG_CP_ACCESS=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_WAKELOCK=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_IPV6_OPTIMISTIC_DAD=y
|
||||
CONFIG_INET6_AH=y
|
||||
CONFIG_INET6_ESP=y
|
||||
CONFIG_INET6_IPCOMP=y
|
||||
CONFIG_IPV6_MIP6=y
|
||||
CONFIG_IPV6_TUNNEL=y
|
||||
CONFIG_IPV6_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6_SUBTREES=y
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_NF_CONNTRACK=y
|
||||
CONFIG_NF_CONNTRACK_EVENTS=y
|
||||
CONFIG_NF_CT_PROTO_DCCP=y
|
||||
CONFIG_NF_CT_PROTO_SCTP=y
|
||||
CONFIG_NF_CT_PROTO_UDPLITE=y
|
||||
CONFIG_NF_CONNTRACK_AMANDA=y
|
||||
CONFIG_NF_CONNTRACK_FTP=y
|
||||
CONFIG_NF_CONNTRACK_H323=y
|
||||
CONFIG_NF_CONNTRACK_IRC=y
|
||||
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
|
||||
CONFIG_NF_CONNTRACK_PPTP=y
|
||||
CONFIG_NF_CONNTRACK_SANE=y
|
||||
CONFIG_NF_CONNTRACK_SIP=y
|
||||
CONFIG_NF_CONNTRACK_TFTP=y
|
||||
CONFIG_NF_CT_NETLINK=y
|
||||
CONFIG_NETFILTER_TPROXY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_LOG=y
|
||||
CONFIG_NETFILTER_XT_TARGET_MARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
|
||||
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_HELPER=y
|
||||
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MAC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_POLICY=y
|
||||
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
|
||||
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STRING=y
|
||||
CONFIG_NETFILTER_XT_MATCH_TIME=y
|
||||
CONFIG_NETFILTER_XT_MATCH_U32=y
|
||||
CONFIG_NF_CONNTRACK_IPV4=y
|
||||
CONFIG_IP_NF_IPTABLES=y
|
||||
CONFIG_IP_NF_MATCH_AH=y
|
||||
CONFIG_IP_NF_MATCH_ECN=y
|
||||
CONFIG_IP_NF_MATCH_TTL=y
|
||||
CONFIG_IP_NF_FILTER=y
|
||||
CONFIG_IP_NF_TARGET_REJECT=y
|
||||
CONFIG_NF_NAT=y
|
||||
CONFIG_IP_NF_TARGET_MASQUERADE=y
|
||||
CONFIG_IP_NF_TARGET_NETMAP=y
|
||||
CONFIG_IP_NF_TARGET_REDIRECT=y
|
||||
CONFIG_IP_NF_MANGLE=y
|
||||
CONFIG_IP_NF_ARPTABLES=y
|
||||
CONFIG_IP_NF_ARPFILTER=y
|
||||
CONFIG_IP_NF_ARP_MANGLE=y
|
||||
CONFIG_IP6_NF_IPTABLES=y
|
||||
CONFIG_IP6_NF_FILTER=y
|
||||
CONFIG_IP6_NF_MANGLE=y
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_SCH_HTB=y
|
||||
CONFIG_NET_SCH_PRIO=y
|
||||
CONFIG_NET_SCH_SFQ=y
|
||||
CONFIG_NET_SCH_TBF=y
|
||||
CONFIG_NET_SCH_DSMARK=m
|
||||
CONFIG_NET_SCH_INGRESS=y
|
||||
CONFIG_NET_CLS_BASIC=y
|
||||
CONFIG_NET_CLS_TCINDEX=y
|
||||
CONFIG_NET_CLS_FW=y
|
||||
CONFIG_NET_CLS_U32=y
|
||||
CONFIG_CLS_U32_MARK=y
|
||||
CONFIG_NET_CLS_FLOW=m
|
||||
CONFIG_NET_EMATCH=y
|
||||
CONFIG_NET_EMATCH_CMP=y
|
||||
CONFIG_NET_EMATCH_NBYTE=y
|
||||
CONFIG_NET_EMATCH_U32=y
|
||||
CONFIG_NET_EMATCH_META=y
|
||||
CONFIG_NET_EMATCH_TEXT=y
|
||||
CONFIG_NET_CLS_ACT=y
|
||||
CONFIG_NET_ACT_MIRRED=y
|
||||
CONFIG_BT=y
|
||||
CONFIG_BT_RFCOMM=y
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_BNEP=y
|
||||
CONFIG_BT_BNEP_MC_FILTER=y
|
||||
CONFIG_BT_BNEP_PROTO_FILTER=y
|
||||
CONFIG_BT_HIDP=y
|
||||
CONFIG_BT_HCIUART=y
|
||||
CONFIG_BT_HCIUART_H4=y
|
||||
CONFIG_BT_HCIUART_IBS=y
|
||||
CONFIG_MSM_BT_POWER=y
|
||||
CONFIG_CFG80211=y
|
||||
# CONFIG_CFG80211_WEXT is not set
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_GENLOCK=y
|
||||
CONFIG_GENLOCK_MISCDEVICE=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_UID_STAT=y
|
||||
CONFIG_TSIF=m
|
||||
CONFIG_TSIF_CHRDEV=m
|
||||
CONFIG_HAPTIC_ISA1200=y
|
||||
CONFIG_PMIC8XXX_VIBRATOR=y
|
||||
CONFIG_PMIC8XXX_UPL=y
|
||||
CONFIG_PMIC8058_XOADC=y
|
||||
CONFIG_QSEECOM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_TGT=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_SCH=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_MD=y
|
||||
CONFIG_BLK_DEV_DM=y
|
||||
CONFIG_DM_DEBUG=y
|
||||
CONFIG_DM_CRYPT=y
|
||||
CONFIG_DM_UEVENT=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_MSM_RMNET_SDIO=y
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMC911X=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_PPP=y
|
||||
CONFIG_PPP_BSDCOMP=y
|
||||
CONFIG_PPP_DEFLATE=y
|
||||
CONFIG_PPP_ASYNC=y
|
||||
CONFIG_SLIP=y
|
||||
CONFIG_SLIP_COMPRESSED=y
|
||||
CONFIG_SLIP_MODE_SLIP6=y
|
||||
CONFIG_LIBRA_SDIOIF=m
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_EVBUG=m
|
||||
CONFIG_INPUT_KEYRESET=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_KEYBOARD_MATRIX=y
|
||||
CONFIG_KEYBOARD_PMIC8XXX=y
|
||||
CONFIG_INPUT_JOYSTICK=y
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_TOUCHSCREEN_CY8C_TS=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_PMIC8XXX_PWRKEY=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
CONFIG_PMIC8058_OTHC=y
|
||||
CONFIG_SERIAL_MSM_HS=y
|
||||
CONFIG_SERIAL_MSM_HSL=y
|
||||
CONFIG_SERIAL_MSM_HSL_CONSOLE=y
|
||||
CONFIG_DIAG_CHAR=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_MSM=y
|
||||
CONFIG_DCC_TTY=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_I2C_MSM is not set
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_I2C_SSBI=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_QUP=y
|
||||
CONFIG_SPI_SPIDEV=m
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_SX150X=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
# CONFIG_BATTERY_MSM is not set
|
||||
CONFIG_BATTERY_MSM8X60=y
|
||||
CONFIG_PM8058_CHARGER=y
|
||||
CONFIG_ISL9519_CHARGER=y
|
||||
CONFIG_SMB137B_CHARGER=y
|
||||
CONFIG_BATTERY_BQ27520=y
|
||||
CONFIG_BATTERY_BQ27541=y
|
||||
CONFIG_SENSORS_MSM_ADC=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_TSENS=y
|
||||
CONFIG_THERMAL_PM8XXX=y
|
||||
CONFIG_PMIC8058=y
|
||||
CONFIG_PMIC8901=y
|
||||
CONFIG_MARIMBA_CORE=y
|
||||
CONFIG_TIMPANI_CODEC=y
|
||||
# CONFIG_MFD_PM8XXX_PWM is not set
|
||||
CONFIG_MFD_PM8XXX_BATT_ALARM=y
|
||||
CONFIG_REGULATOR_MSM_GPIO=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_MEDIA_CONTROLLER=y
|
||||
CONFIG_VIDEO_DEV=y
|
||||
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
|
||||
CONFIG_VIDEOBUF2_MSM_MEM=y
|
||||
CONFIG_USB_VIDEO_CLASS=y
|
||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
||||
CONFIG_MSM_CAMERA_V4L2=y
|
||||
CONFIG_IMX074=y
|
||||
CONFIG_WEBCAM_OV9726=y
|
||||
CONFIG_MT9E013=y
|
||||
CONFIG_IMX074_ACT=y
|
||||
CONFIG_MSM_CAMERA_SENSOR=y
|
||||
CONFIG_MSM_ACTUATOR=y
|
||||
CONFIG_MSM_GEMINI=y
|
||||
CONFIG_OV7692=y
|
||||
CONFIG_RADIO_TAVARUA=y
|
||||
CONFIG_ION=y
|
||||
CONFIG_ION_MSM=y
|
||||
CONFIG_MSM_KGSL=y
|
||||
CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y
|
||||
CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=24
|
||||
CONFIG_VIDEO_OUTPUT_CONTROL=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_MSM=y
|
||||
# CONFIG_FB_MSM_BACKLIGHT is not set
|
||||
CONFIG_FB_MSM_TRIPLE_BUFFER=y
|
||||
CONFIG_FB_MSM_MDP40=y
|
||||
CONFIG_FB_MSM_OVERLAY=y
|
||||
CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y
|
||||
CONFIG_FB_MSM_OVERLAY1_WRITEBACK=y
|
||||
CONFIG_FB_MSM_WRITEBACK_MSM_PANEL=y
|
||||
CONFIG_FB_MSM_LCDC_MIPI_PANEL_AUTO_DETECT=y
|
||||
CONFIG_FB_MSM_HDMI_MSM_PANEL=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_USB_AUDIO=y
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_MAGICMOUSE=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_SUSPEND=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_EHSET=y
|
||||
CONFIG_USB_EHCI_ROOT_HUB_TT=y
|
||||
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
|
||||
CONFIG_USB_EHCI_MSM_72K=y
|
||||
CONFIG_USB_ACM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_STORAGE_DATAFAB=y
|
||||
CONFIG_USB_STORAGE_FREECOM=y
|
||||
CONFIG_USB_STORAGE_ISD200=y
|
||||
CONFIG_USB_STORAGE_USBAT=y
|
||||
CONFIG_USB_STORAGE_SDDR09=y
|
||||
CONFIG_USB_STORAGE_SDDR55=y
|
||||
CONFIG_USB_STORAGE_JUMPSHOT=y
|
||||
CONFIG_USB_STORAGE_ALAUDA=y
|
||||
CONFIG_USB_STORAGE_ONETOUCH=y
|
||||
CONFIG_USB_STORAGE_KARMA=y
|
||||
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
|
||||
CONFIG_USB_EHSET_TEST_FIXTURE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_MSM_72K=y
|
||||
CONFIG_USB_G_ANDROID=y
|
||||
CONFIG_RMNET_SMD_CTL_CHANNEL="DATA40_CNTL"
|
||||
CONFIG_RMNET_SMD_DATA_CHANNEL="DATA40"
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_PERF_PROFILING=y
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
CONFIG_MMC_CLKGATE=y
|
||||
CONFIG_MMC_EMBEDDED_SDIO=y
|
||||
CONFIG_MMC_PARANOID_SD_INIT=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
CONFIG_MMC_TEST=m
|
||||
CONFIG_MMC_MSM=y
|
||||
CONFIG_MMC_MSM_CARD_HW_DETECTION=y
|
||||
CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC3_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC3_8_BIT_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC4_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC5_SUPPORT=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_PMIC8058=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_TIMER=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_LEDS_TRIGGER_SLEEP=y
|
||||
CONFIG_SWITCH=y
|
||||
CONFIG_SWITCH_GPIO=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_DRV_MSM is not set
|
||||
CONFIG_RTC_DRV_PM8XXX=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_ANDROID_BINDER_IPC=y
|
||||
CONFIG_ANDROID_LOGGER=y
|
||||
CONFIG_ANDROID_RAM_CONSOLE=y
|
||||
CONFIG_ANDROID_TIMED_GPIO=y
|
||||
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
|
||||
CONFIG_MSM_SSBI=y
|
||||
CONFIG_MSM_IOMMU=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_CIFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_LOCKUP_DETECTOR=y
|
||||
CONFIG_SCHEDSTATS=y
|
||||
CONFIG_TIMER_STATS=y
|
||||
CONFIG_SLUB_DEBUG_ON=y
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
CONFIG_DEBUG_ATOMIC_SLEEP=y
|
||||
CONFIG_DEBUG_STACK_USAGE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_VM=y
|
||||
CONFIG_DEBUG_MEMORY_INIT=y
|
||||
CONFIG_DEBUG_LIST=y
|
||||
CONFIG_DEBUG_SG=y
|
||||
CONFIG_DEBUG_PAGEALLOC=y
|
||||
CONFIG_ENABLE_DEFAULT_TRACERS=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_DEBUG_LL=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRYPTO_DEV_QCRYPTO=m
|
||||
CONFIG_CRYPTO_DEV_QCE=m
|
||||
CONFIG_CRYPTO_DEV_QCEDEV=m
|
||||
483
arch/arm/configs/msm8960-perf_defconfig
Normal file
483
arch/arm/configs/msm8960-perf_defconfig
Normal file
@@ -0,0 +1,483 @@
|
||||
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_LOCALVERSION="-perf"
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_DEBUG=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_RESOURCE_COUNTERS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_RT_GROUP_SCHED=y
|
||||
CONFIG_NAMESPACES=y
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_USER_NS is not set
|
||||
# CONFIG_PID_NS is not set
|
||||
# CONFIG_NET_NS is not set
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_PANIC_TIMEOUT=5
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_ASHMEM=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=y
|
||||
CONFIG_KPROBES=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
CONFIG_ARCH_MSM=y
|
||||
CONFIG_ARCH_MSM8960=y
|
||||
CONFIG_ARCH_MSM8930=y
|
||||
CONFIG_ARCH_APQ8064=y
|
||||
CONFIG_MSM_KRAIT_TBB_ABORT_HANDLER=y
|
||||
CONFIG_MACH_MSM8960_SIM=y
|
||||
CONFIG_MACH_MSM8960_RUMI3=y
|
||||
CONFIG_MACH_MSM8960_CDP=y
|
||||
CONFIG_MACH_MSM8960_MTP=y
|
||||
CONFIG_MACH_MSM8960_FLUID=y
|
||||
CONFIG_MACH_MSM8960_LIQUID=y
|
||||
CONFIG_MACH_MSM8930_CDP=y
|
||||
CONFIG_MACH_MSM8930_MTP=y
|
||||
CONFIG_MACH_MSM8930_FLUID=y
|
||||
CONFIG_MACH_MSM8627_CDP=y
|
||||
CONFIG_MACH_MSM8627_MTP=y
|
||||
CONFIG_MACH_APQ8064_SIM=y
|
||||
CONFIG_MACH_APQ8064_RUMI3=y
|
||||
CONFIG_MACH_APQ8064_CDP=y
|
||||
CONFIG_MACH_APQ8064_MTP=y
|
||||
CONFIG_MACH_APQ8064_LIQUID=y
|
||||
CONFIG_MACH_MPQ8064_CDP=y
|
||||
CONFIG_MACH_MPQ8064_HRD=y
|
||||
CONFIG_MACH_MPQ8064_DTV=y
|
||||
# CONFIG_MSM_STACKED_MEMORY is not set
|
||||
CONFIG_KERNEL_PMEM_EBI_REGION=y
|
||||
# CONFIG_MSM_FIQ_SUPPORT is not set
|
||||
# CONFIG_MSM_PROC_COMM is not set
|
||||
CONFIG_MSM_SMD=y
|
||||
CONFIG_MSM_SMD_PKG4=y
|
||||
CONFIG_MSM_PCIE=y
|
||||
CONFIG_MSM_BAM_DMUX=y
|
||||
CONFIG_MSM_RMNET_SMUX=y
|
||||
CONFIG_MSM_DSPS=y
|
||||
CONFIG_MSM_IPC_ROUTER=y
|
||||
CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
|
||||
# CONFIG_MSM_HW3D is not set
|
||||
CONFIG_MSM_PIL_QDSP6V4=y
|
||||
CONFIG_MSM_PIL_RIVA=y
|
||||
CONFIG_MSM_PIL_TZAPPS=y
|
||||
CONFIG_MSM_PIL_DSPS=y
|
||||
CONFIG_MSM_PIL_VIDC=y
|
||||
CONFIG_MSM_PIL_GSS=y
|
||||
CONFIG_MSM_SUBSYSTEM_RESTART=y
|
||||
CONFIG_MSM_MODEM_8960=y
|
||||
CONFIG_MSM_LPASS_8960=y
|
||||
CONFIG_MSM_WCNSS_SSR_8960=y
|
||||
CONFIG_MSM_GSS_SSR_8064=y
|
||||
CONFIG_MSM_TZ_LOG=y
|
||||
CONFIG_MSM_RPM_LOG=y
|
||||
CONFIG_MSM_RPM_STATS_LOG=y
|
||||
CONFIG_MSM_BUS_SCALING=y
|
||||
CONFIG_MSM_BUS_RPM_MULTI_TIER_ENABLED=y
|
||||
CONFIG_MSM_WATCHDOG=y
|
||||
CONFIG_MSM_DLOAD_MODE=y
|
||||
CONFIG_MSM_QDSS=y
|
||||
CONFIG_MSM_SLEEP_STATS=y
|
||||
CONFIG_MSM_CACHE_ERP=y
|
||||
CONFIG_MSM_L2_ERP_2BIT_PANIC=y
|
||||
CONFIG_MSM_DCVS=y
|
||||
CONFIG_MSM_HSIC_SYSMON=y
|
||||
CONFIG_STRICT_MEMORY_RWX=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_SMP=y
|
||||
# CONFIG_SMP_ON_UP is not set
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_VMALLOC_RESERVE=0x19000000
|
||||
CONFIG_CC_STACKPROTECTOR=y
|
||||
CONFIG_CP_ACCESS=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_WAKELOCK=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_IPV6_OPTIMISTIC_DAD=y
|
||||
CONFIG_INET6_AH=y
|
||||
CONFIG_INET6_ESP=y
|
||||
CONFIG_INET6_IPCOMP=y
|
||||
CONFIG_IPV6_MIP6=y
|
||||
CONFIG_IPV6_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6_SUBTREES=y
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_NETFILTER_NETLINK_LOG=y
|
||||
CONFIG_NF_CONNTRACK=y
|
||||
CONFIG_NF_CONNTRACK_EVENTS=y
|
||||
CONFIG_NF_CT_PROTO_DCCP=y
|
||||
CONFIG_NF_CT_PROTO_SCTP=y
|
||||
CONFIG_NF_CT_PROTO_UDPLITE=y
|
||||
CONFIG_NF_CONNTRACK_AMANDA=y
|
||||
CONFIG_NF_CONNTRACK_FTP=y
|
||||
CONFIG_NF_CONNTRACK_H323=y
|
||||
CONFIG_NF_CONNTRACK_IRC=y
|
||||
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
|
||||
CONFIG_NF_CONNTRACK_PPTP=y
|
||||
CONFIG_NF_CONNTRACK_SANE=y
|
||||
CONFIG_NF_CONNTRACK_SIP=y
|
||||
CONFIG_NF_CONNTRACK_TFTP=y
|
||||
CONFIG_NF_CT_NETLINK=y
|
||||
CONFIG_NETFILTER_TPROXY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_LOG=y
|
||||
CONFIG_NETFILTER_XT_TARGET_MARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_HELPER=y
|
||||
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MAC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_POLICY=y
|
||||
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
|
||||
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STRING=y
|
||||
CONFIG_NETFILTER_XT_MATCH_TIME=y
|
||||
CONFIG_NETFILTER_XT_MATCH_U32=y
|
||||
CONFIG_NF_CONNTRACK_IPV4=y
|
||||
CONFIG_IP_NF_IPTABLES=y
|
||||
CONFIG_IP_NF_MATCH_AH=y
|
||||
CONFIG_IP_NF_MATCH_ECN=y
|
||||
CONFIG_IP_NF_MATCH_TTL=y
|
||||
CONFIG_IP_NF_FILTER=y
|
||||
CONFIG_IP_NF_TARGET_REJECT=y
|
||||
CONFIG_NF_NAT=y
|
||||
CONFIG_IP_NF_TARGET_MASQUERADE=y
|
||||
CONFIG_IP_NF_TARGET_NETMAP=y
|
||||
CONFIG_IP_NF_TARGET_REDIRECT=y
|
||||
CONFIG_IP_NF_MANGLE=y
|
||||
CONFIG_IP_NF_ARPTABLES=y
|
||||
CONFIG_IP_NF_ARPFILTER=y
|
||||
CONFIG_IP_NF_ARP_MANGLE=y
|
||||
CONFIG_NF_CONNTRACK_IPV6=y
|
||||
CONFIG_IP6_NF_IPTABLES=y
|
||||
CONFIG_IP6_NF_FILTER=y
|
||||
CONFIG_IP6_NF_TARGET_REJECT=y
|
||||
CONFIG_IP6_NF_MANGLE=y
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_SCH_HTB=y
|
||||
CONFIG_NET_SCH_PRIO=y
|
||||
CONFIG_NET_CLS_FW=y
|
||||
CONFIG_NET_CLS_U32=y
|
||||
CONFIG_CLS_U32_MARK=y
|
||||
CONFIG_NET_CLS_FLOW=y
|
||||
CONFIG_NET_EMATCH=y
|
||||
CONFIG_NET_EMATCH_CMP=y
|
||||
CONFIG_NET_EMATCH_NBYTE=y
|
||||
CONFIG_NET_EMATCH_U32=y
|
||||
CONFIG_NET_EMATCH_META=y
|
||||
CONFIG_NET_EMATCH_TEXT=y
|
||||
CONFIG_NET_CLS_ACT=y
|
||||
CONFIG_BT=y
|
||||
CONFIG_BT_RFCOMM=y
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_BNEP=y
|
||||
CONFIG_BT_BNEP_MC_FILTER=y
|
||||
CONFIG_BT_BNEP_PROTO_FILTER=y
|
||||
CONFIG_BT_HIDP=y
|
||||
CONFIG_BT_HCISMD=y
|
||||
CONFIG_CFG80211=m
|
||||
# CONFIG_CFG80211_WEXT is not set
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_GENLOCK=y
|
||||
CONFIG_GENLOCK_MISCDEVICE=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_HAPTIC_ISA1200=y
|
||||
CONFIG_PMIC8XXX_VIBRATOR=y
|
||||
CONFIG_QSEECOM=y
|
||||
CONFIG_USB_HSIC_SMSC_HUB=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_TGT=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_SCH=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_MD=y
|
||||
CONFIG_BLK_DEV_DM=y
|
||||
CONFIG_DM_CRYPT=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_KS8851=m
|
||||
# CONFIG_MSM_RMNET is not set
|
||||
CONFIG_MSM_RMNET_BAM=y
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMC911X=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_SLIP=y
|
||||
CONFIG_SLIP_COMPRESSED=y
|
||||
CONFIG_SLIP_MODE_SLIP6=y
|
||||
CONFIG_USB_USBNET=y
|
||||
CONFIG_MSM_RMNET_USB=y
|
||||
CONFIG_WCNSS_CORE=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_EVBUG=m
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_KEYBOARD_MATRIX=y
|
||||
CONFIG_KEYBOARD_PMIC8XXX=y
|
||||
CONFIG_INPUT_JOYSTICK=y
|
||||
CONFIG_JOYSTICK_XPAD=y
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
|
||||
CONFIG_TOUCHSCREEN_CYTTSP_I2C_QC=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_PMIC8XXX_PWRKEY=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_N_SMUX=y
|
||||
CONFIG_N_SMUX_LOOPBACK=y
|
||||
CONFIG_SMUX_CTL=y
|
||||
CONFIG_SERIAL_MSM_HS=y
|
||||
CONFIG_SERIAL_MSM_HSL=y
|
||||
CONFIG_SERIAL_MSM_HSL_CONSOLE=y
|
||||
CONFIG_DIAG_CHAR=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_MSM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_I2C_MSM is not set
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_QUP=y
|
||||
CONFIG_SPI_SPIDEV=m
|
||||
CONFIG_SLIMBUS_MSM_CTRL=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_SX150X=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
# CONFIG_BATTERY_MSM is not set
|
||||
CONFIG_ISL9519_CHARGER=y
|
||||
CONFIG_SMB349_CHARGER=y
|
||||
CONFIG_PM8921_CHARGER=y
|
||||
CONFIG_PM8921_BMS=y
|
||||
CONFIG_PM8921_BCL=y
|
||||
CONFIG_SENSORS_PM8XXX_ADC=y
|
||||
CONFIG_SENSORS_EPM_ADC=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_TSENS8960=y
|
||||
CONFIG_THERMAL_PM8XXX=y
|
||||
CONFIG_THERMAL_MONITOR=y
|
||||
CONFIG_MFD_PM8921_CORE=y
|
||||
CONFIG_MFD_PM8821_CORE=y
|
||||
CONFIG_MFD_PM8038_CORE=y
|
||||
CONFIG_MFD_PM8XXX_SPK=y
|
||||
CONFIG_MFD_PM8XXX_BATT_ALARM=y
|
||||
CONFIG_WCD9304_CODEC=y
|
||||
CONFIG_WCD9310_CODEC=y
|
||||
CONFIG_REGULATOR_PM8XXX=y
|
||||
CONFIG_REGULATOR_MSM_GPIO=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_MEDIA_CONTROLLER=y
|
||||
CONFIG_VIDEO_DEV=y
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
CONFIG_USER_RC_INPUT=y
|
||||
CONFIG_IR_GPIO_CIR=y
|
||||
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
|
||||
CONFIG_VIDEOBUF2_MSM_MEM=y
|
||||
CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
|
||||
CONFIG_USB_VIDEO_CLASS=y
|
||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
||||
CONFIG_MSM_CAMERA_V4L2=y
|
||||
CONFIG_IMX074=y
|
||||
CONFIG_MT9M114=y
|
||||
CONFIG_IMX074_ACT=y
|
||||
CONFIG_MSM_CAMERA_FLASH_SC628A=y
|
||||
CONFIG_MSM_CAMERA_FLASH_TPS61310=y
|
||||
CONFIG_OV2720=y
|
||||
CONFIG_MSM_CAMERA_SENSOR=y
|
||||
CONFIG_MSM_ACTUATOR=y
|
||||
CONFIG_MSM_EEPROM=y
|
||||
CONFIG_IMX074_EEPROM=y
|
||||
CONFIG_IMX091_EEPROM=y
|
||||
CONFIG_MSM_GEMINI=y
|
||||
CONFIG_S5K3L1YX=y
|
||||
CONFIG_IMX091=y
|
||||
CONFIG_RADIO_IRIS=y
|
||||
CONFIG_RADIO_IRIS_TRANSPORT=m
|
||||
CONFIG_ION=y
|
||||
CONFIG_ION_MSM=y
|
||||
CONFIG_MSM_KGSL=y
|
||||
CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y
|
||||
CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=24
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_VIRTUAL=y
|
||||
CONFIG_FB_MSM=y
|
||||
# CONFIG_FB_MSM_BACKLIGHT is not set
|
||||
CONFIG_FB_MSM_TRIPLE_BUFFER=y
|
||||
CONFIG_FB_MSM_MDP40=y
|
||||
CONFIG_FB_MSM_OVERLAY=y
|
||||
CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y
|
||||
CONFIG_FB_MSM_OVERLAY1_WRITEBACK=y
|
||||
CONFIG_FB_MSM_WRITEBACK_MSM_PANEL=y
|
||||
CONFIG_FB_MSM_LVDS_MIPI_PANEL_DETECT=y
|
||||
CONFIG_FB_MSM_HDMI_MSM_PANEL=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_DYNAMIC_MINORS=y
|
||||
# CONFIG_SND_ARM is not set
|
||||
# CONFIG_SND_SPI is not set
|
||||
CONFIG_SND_USB_AUDIO=y
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_SOC_MSM8960=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_MAGICMOUSE=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_SUSPEND=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_EHSET=y
|
||||
CONFIG_USB_EHCI_MSM=y
|
||||
CONFIG_USB_EHCI_MSM_HSIC=y
|
||||
CONFIG_USB_ACM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_STORAGE_DEBUG=y
|
||||
CONFIG_USB_STORAGE_DATAFAB=y
|
||||
CONFIG_USB_STORAGE_FREECOM=y
|
||||
CONFIG_USB_STORAGE_ISD200=y
|
||||
CONFIG_USB_STORAGE_USBAT=y
|
||||
CONFIG_USB_STORAGE_SDDR09=y
|
||||
CONFIG_USB_STORAGE_SDDR55=y
|
||||
CONFIG_USB_STORAGE_JUMPSHOT=y
|
||||
CONFIG_USB_STORAGE_ALAUDA=y
|
||||
CONFIG_USB_STORAGE_ONETOUCH=y
|
||||
CONFIG_USB_STORAGE_KARMA=y
|
||||
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
|
||||
CONFIG_USB_SERIAL=y
|
||||
CONFIG_USB_SERIAL_QUALCOMM=y
|
||||
CONFIG_USB_SERIAL_CSVT=y
|
||||
CONFIG_USB_EHSET_TEST_FIXTURE=y
|
||||
CONFIG_USB_QCOM_DIAG_BRIDGE=y
|
||||
CONFIG_USB_QCOM_MDM_BRIDGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DEBUG_FILES=y
|
||||
CONFIG_USB_CI13XXX_MSM=y
|
||||
CONFIG_USB_G_ANDROID=y
|
||||
CONFIG_USB_ANDROID_RMNET_CTRL_SMD=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_PERF_PROFILING=y
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
CONFIG_MMC_CLKGATE=y
|
||||
CONFIG_MMC_PARANOID_SD_INIT=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
CONFIG_MMC_TEST=m
|
||||
CONFIG_MMC_MSM=y
|
||||
CONFIG_MMC_MSM_CARD_HW_DETECTION=y
|
||||
CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT=y
|
||||
# CONFIG_MMC_MSM_SDC2_SUPPORT is not set
|
||||
CONFIG_MMC_MSM_SDC3_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC3_WP_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SPS_SUPPORT=y
|
||||
CONFIG_LEDS_PM8XXX=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_SWITCH=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_DRV_MSM is not set
|
||||
CONFIG_RTC_DRV_PM8XXX=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_ANDROID_BINDER_IPC=y
|
||||
CONFIG_ANDROID_LOGGER=y
|
||||
CONFIG_ANDROID_RAM_CONSOLE=y
|
||||
CONFIG_ANDROID_TIMED_GPIO=y
|
||||
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
|
||||
CONFIG_MSM_SSBI=y
|
||||
CONFIG_SPS=y
|
||||
CONFIG_SPS_SUPPORT_BAMDMA=y
|
||||
CONFIG_MSM_IOMMU=y
|
||||
CONFIG_MOBICORE_SUPPORT=m
|
||||
CONFIG_MOBICORE_API=m
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_CIFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_TIMER_STATS=y
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_MEMORY_INIT=y
|
||||
CONFIG_ENABLE_DEFAULT_TRACERS=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_PID_IN_CONTEXTIDR=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRYPTO_DEV_QCRYPTO=m
|
||||
CONFIG_CRYPTO_DEV_QCE=m
|
||||
CONFIG_CRYPTO_DEV_QCEDEV=m
|
||||
CONFIG_CRC_CCITT=y
|
||||
500
arch/arm/configs/msm8960_defconfig
Normal file
500
arch/arm/configs/msm8960_defconfig
Normal file
@@ -0,0 +1,500 @@
|
||||
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_DEBUG=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_RESOURCE_COUNTERS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_RT_GROUP_SCHED=y
|
||||
CONFIG_NAMESPACES=y
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_USER_NS is not set
|
||||
# CONFIG_PID_NS is not set
|
||||
# CONFIG_NET_NS is not set
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_PANIC_TIMEOUT=5
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_ASHMEM=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=y
|
||||
CONFIG_KPROBES=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
CONFIG_ARCH_MSM=y
|
||||
CONFIG_ARCH_MSM8960=y
|
||||
CONFIG_ARCH_MSM8930=y
|
||||
CONFIG_ARCH_APQ8064=y
|
||||
CONFIG_MSM_KRAIT_TBB_ABORT_HANDLER=y
|
||||
CONFIG_MACH_MSM8960_SIM=y
|
||||
CONFIG_MACH_MSM8960_RUMI3=y
|
||||
CONFIG_MACH_MSM8960_CDP=y
|
||||
CONFIG_MACH_MSM8960_MTP=y
|
||||
CONFIG_MACH_MSM8960_FLUID=y
|
||||
CONFIG_MACH_MSM8960_LIQUID=y
|
||||
CONFIG_MACH_MSM8930_CDP=y
|
||||
CONFIG_MACH_MSM8930_MTP=y
|
||||
CONFIG_MACH_MSM8930_FLUID=y
|
||||
CONFIG_MACH_MSM8627_CDP=y
|
||||
CONFIG_MACH_MSM8627_MTP=y
|
||||
CONFIG_MACH_APQ8064_SIM=y
|
||||
CONFIG_MACH_APQ8064_RUMI3=y
|
||||
CONFIG_MACH_APQ8064_CDP=y
|
||||
CONFIG_MACH_APQ8064_MTP=y
|
||||
CONFIG_MACH_APQ8064_LIQUID=y
|
||||
CONFIG_MACH_MPQ8064_CDP=y
|
||||
CONFIG_MACH_MPQ8064_HRD=y
|
||||
CONFIG_MACH_MPQ8064_DTV=y
|
||||
# CONFIG_MSM_STACKED_MEMORY is not set
|
||||
CONFIG_KERNEL_PMEM_EBI_REGION=y
|
||||
# CONFIG_MSM_FIQ_SUPPORT is not set
|
||||
# CONFIG_MSM_PROC_COMM is not set
|
||||
CONFIG_MSM_SMD=y
|
||||
CONFIG_MSM_SMD_PKG4=y
|
||||
CONFIG_MSM_PCIE=y
|
||||
CONFIG_MSM_BAM_DMUX=y
|
||||
CONFIG_MSM_DSPS=y
|
||||
CONFIG_MSM_IPC_ROUTER=y
|
||||
CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
|
||||
# CONFIG_MSM_HW3D is not set
|
||||
CONFIG_MSM_PIL_QDSP6V4=y
|
||||
CONFIG_MSM_PIL_RIVA=y
|
||||
CONFIG_MSM_PIL_TZAPPS=y
|
||||
CONFIG_MSM_PIL_DSPS=y
|
||||
CONFIG_MSM_PIL_VIDC=y
|
||||
CONFIG_MSM_PIL_GSS=y
|
||||
CONFIG_MSM_SUBSYSTEM_RESTART=y
|
||||
CONFIG_MSM_MODEM_8960=y
|
||||
CONFIG_MSM_LPASS_8960=y
|
||||
CONFIG_MSM_WCNSS_SSR_8960=y
|
||||
CONFIG_MSM_GSS_SSR_8064=y
|
||||
CONFIG_MSM_TZ_LOG=y
|
||||
CONFIG_MSM_RPM_LOG=y
|
||||
CONFIG_MSM_RPM_STATS_LOG=y
|
||||
CONFIG_MSM_BUS_SCALING=y
|
||||
CONFIG_MSM_BUS_RPM_MULTI_TIER_ENABLED=y
|
||||
CONFIG_MSM_WATCHDOG=y
|
||||
CONFIG_MSM_DLOAD_MODE=y
|
||||
CONFIG_MSM_QDSS=y
|
||||
CONFIG_MSM_QDSS_ETM_DEFAULT_ENABLE=y
|
||||
CONFIG_MSM_RTB=y
|
||||
CONFIG_MSM_RTB_SEPARATE_CPUS=y
|
||||
CONFIG_MSM_CACHE_ERP=y
|
||||
CONFIG_MSM_L1_ERR_PANIC=y
|
||||
CONFIG_MSM_L2_ERP_PRINT_ACCESS_ERRORS=y
|
||||
CONFIG_MSM_L2_ERP_1BIT_PANIC=y
|
||||
CONFIG_MSM_L2_ERP_2BIT_PANIC=y
|
||||
CONFIG_MSM_DCVS=y
|
||||
CONFIG_MSM_CACHE_DUMP=y
|
||||
CONFIG_MSM_CACHE_DUMP_ON_PANIC=y
|
||||
CONFIG_MSM_HSIC_SYSMON=y
|
||||
CONFIG_STRICT_MEMORY_RWX=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_SMP=y
|
||||
# CONFIG_SMP_ON_UP is not set
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_VMALLOC_RESERVE=0x19000000
|
||||
CONFIG_CC_STACKPROTECTOR=y
|
||||
CONFIG_CP_ACCESS=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_WAKELOCK=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_IPV6_OPTIMISTIC_DAD=y
|
||||
CONFIG_INET6_AH=y
|
||||
CONFIG_INET6_ESP=y
|
||||
CONFIG_INET6_IPCOMP=y
|
||||
CONFIG_IPV6_MIP6=y
|
||||
CONFIG_IPV6_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6_SUBTREES=y
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_NETFILTER_NETLINK_LOG=y
|
||||
CONFIG_NF_CONNTRACK=y
|
||||
CONFIG_NF_CONNTRACK_EVENTS=y
|
||||
CONFIG_NF_CT_PROTO_DCCP=y
|
||||
CONFIG_NF_CT_PROTO_SCTP=y
|
||||
CONFIG_NF_CT_PROTO_UDPLITE=y
|
||||
CONFIG_NF_CONNTRACK_AMANDA=y
|
||||
CONFIG_NF_CONNTRACK_FTP=y
|
||||
CONFIG_NF_CONNTRACK_H323=y
|
||||
CONFIG_NF_CONNTRACK_IRC=y
|
||||
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
|
||||
CONFIG_NF_CONNTRACK_PPTP=y
|
||||
CONFIG_NF_CONNTRACK_SANE=y
|
||||
CONFIG_NF_CONNTRACK_SIP=y
|
||||
CONFIG_NF_CONNTRACK_TFTP=y
|
||||
CONFIG_NF_CT_NETLINK=y
|
||||
CONFIG_NETFILTER_TPROXY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_LOG=y
|
||||
CONFIG_NETFILTER_XT_TARGET_MARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_HELPER=y
|
||||
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
|
||||
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MAC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_POLICY=y
|
||||
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
|
||||
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STRING=y
|
||||
CONFIG_NETFILTER_XT_MATCH_TIME=y
|
||||
CONFIG_NETFILTER_XT_MATCH_U32=y
|
||||
CONFIG_NF_CONNTRACK_IPV4=y
|
||||
CONFIG_IP_NF_IPTABLES=y
|
||||
CONFIG_IP_NF_MATCH_AH=y
|
||||
CONFIG_IP_NF_MATCH_ECN=y
|
||||
CONFIG_IP_NF_MATCH_TTL=y
|
||||
CONFIG_IP_NF_FILTER=y
|
||||
CONFIG_IP_NF_TARGET_REJECT=y
|
||||
CONFIG_NF_NAT=y
|
||||
CONFIG_IP_NF_TARGET_MASQUERADE=y
|
||||
CONFIG_IP_NF_TARGET_NETMAP=y
|
||||
CONFIG_IP_NF_TARGET_REDIRECT=y
|
||||
CONFIG_IP_NF_MANGLE=y
|
||||
CONFIG_IP_NF_ARPTABLES=y
|
||||
CONFIG_IP_NF_ARPFILTER=y
|
||||
CONFIG_IP_NF_ARP_MANGLE=y
|
||||
CONFIG_NF_CONNTRACK_IPV6=y
|
||||
CONFIG_IP6_NF_IPTABLES=y
|
||||
CONFIG_IP6_NF_FILTER=y
|
||||
CONFIG_IP6_NF_TARGET_REJECT=y
|
||||
CONFIG_IP6_NF_MANGLE=y
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_SCH_HTB=y
|
||||
CONFIG_NET_SCH_PRIO=y
|
||||
CONFIG_NET_CLS_FW=y
|
||||
CONFIG_NET_CLS_U32=y
|
||||
CONFIG_CLS_U32_MARK=y
|
||||
CONFIG_NET_CLS_FLOW=y
|
||||
CONFIG_NET_EMATCH=y
|
||||
CONFIG_NET_EMATCH_CMP=y
|
||||
CONFIG_NET_EMATCH_NBYTE=y
|
||||
CONFIG_NET_EMATCH_U32=y
|
||||
CONFIG_NET_EMATCH_META=y
|
||||
CONFIG_NET_EMATCH_TEXT=y
|
||||
CONFIG_NET_CLS_ACT=y
|
||||
CONFIG_BT=y
|
||||
CONFIG_BT_RFCOMM=y
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_BNEP=y
|
||||
CONFIG_BT_BNEP_MC_FILTER=y
|
||||
CONFIG_BT_BNEP_PROTO_FILTER=y
|
||||
CONFIG_BT_HIDP=y
|
||||
CONFIG_BT_HCISMD=y
|
||||
CONFIG_CFG80211=m
|
||||
# CONFIG_CFG80211_WEXT is not set
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_GENLOCK=y
|
||||
CONFIG_GENLOCK_MISCDEVICE=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_HAPTIC_ISA1200=y
|
||||
CONFIG_PMIC8XXX_VIBRATOR=y
|
||||
CONFIG_QSEECOM=y
|
||||
CONFIG_USB_HSIC_SMSC_HUB=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_TGT=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_SCH=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_MD=y
|
||||
CONFIG_BLK_DEV_DM=y
|
||||
CONFIG_DM_CRYPT=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_KS8851=m
|
||||
# CONFIG_MSM_RMNET is not set
|
||||
CONFIG_MSM_RMNET_BAM=y
|
||||
CONFIG_MSM_RMNET_SMUX=y
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMC911X=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_SLIP=y
|
||||
CONFIG_SLIP_COMPRESSED=y
|
||||
CONFIG_SLIP_MODE_SLIP6=y
|
||||
CONFIG_USB_USBNET=y
|
||||
CONFIG_MSM_RMNET_USB=y
|
||||
CONFIG_WCNSS_CORE=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_EVBUG=m
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_KEYBOARD_MATRIX=y
|
||||
CONFIG_KEYBOARD_PMIC8XXX=y
|
||||
CONFIG_INPUT_JOYSTICK=y
|
||||
CONFIG_JOYSTICK_XPAD=y
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
|
||||
CONFIG_TOUCHSCREEN_CYTTSP_I2C_QC=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_PMIC8XXX_PWRKEY=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_N_SMUX=y
|
||||
CONFIG_N_SMUX_LOOPBACK=y
|
||||
CONFIG_SMUX_CTL=y
|
||||
CONFIG_SERIAL_MSM_HS=y
|
||||
CONFIG_SERIAL_MSM_HSL=y
|
||||
CONFIG_SERIAL_MSM_HSL_CONSOLE=y
|
||||
CONFIG_DIAG_CHAR=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_MSM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_I2C_MSM is not set
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_QUP=y
|
||||
CONFIG_SPI_SPIDEV=m
|
||||
CONFIG_SLIMBUS_MSM_CTRL=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_SX150X=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
# CONFIG_BATTERY_MSM is not set
|
||||
CONFIG_ISL9519_CHARGER=y
|
||||
CONFIG_SMB349_CHARGER=y
|
||||
CONFIG_PM8921_CHARGER=y
|
||||
CONFIG_PM8921_BMS=y
|
||||
CONFIG_SENSORS_PM8XXX_ADC=y
|
||||
CONFIG_SENSORS_EPM_ADC=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_TSENS8960=y
|
||||
CONFIG_THERMAL_PM8XXX=y
|
||||
CONFIG_THERMAL_MONITOR=y
|
||||
CONFIG_MFD_PM8921_CORE=y
|
||||
CONFIG_MFD_PM8821_CORE=y
|
||||
CONFIG_MFD_PM8038_CORE=y
|
||||
CONFIG_MFD_PM8XXX_SPK=y
|
||||
CONFIG_MFD_PM8XXX_BATT_ALARM=y
|
||||
CONFIG_WCD9304_CODEC=y
|
||||
CONFIG_WCD9310_CODEC=y
|
||||
CONFIG_REGULATOR_PM8XXX=y
|
||||
CONFIG_REGULATOR_MSM_GPIO=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_MEDIA_CONTROLLER=y
|
||||
CONFIG_VIDEO_DEV=y
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
CONFIG_USER_RC_INPUT=y
|
||||
CONFIG_IR_GPIO_CIR=y
|
||||
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
|
||||
CONFIG_VIDEOBUF2_MSM_MEM=y
|
||||
CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
|
||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
||||
CONFIG_MSM_CAMERA_V4L2=y
|
||||
CONFIG_IMX074=y
|
||||
CONFIG_MT9M114=y
|
||||
CONFIG_IMX074_ACT=y
|
||||
CONFIG_MSM_CAMERA_FLASH_SC628A=y
|
||||
CONFIG_OV2720=y
|
||||
CONFIG_MSM_CAMERA_SENSOR=y
|
||||
CONFIG_MSM_ACTUATOR=y
|
||||
CONFIG_MSM_EEPROM=y
|
||||
CONFIG_IMX074_EEPROM=y
|
||||
CONFIG_IMX091_EEPROM=y
|
||||
CONFIG_MSM_GEMINI=y
|
||||
CONFIG_S5K3L1YX=y
|
||||
CONFIG_IMX091=y
|
||||
CONFIG_RADIO_IRIS=y
|
||||
CONFIG_RADIO_IRIS_TRANSPORT=m
|
||||
CONFIG_ION=y
|
||||
CONFIG_ION_MSM=y
|
||||
CONFIG_MSM_KGSL=y
|
||||
CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y
|
||||
CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=24
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_VIRTUAL=y
|
||||
CONFIG_FB_MSM=y
|
||||
# CONFIG_FB_MSM_BACKLIGHT is not set
|
||||
CONFIG_FB_MSM_TRIPLE_BUFFER=y
|
||||
CONFIG_FB_MSM_MDP40=y
|
||||
CONFIG_FB_MSM_OVERLAY=y
|
||||
CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y
|
||||
CONFIG_FB_MSM_OVERLAY1_WRITEBACK=y
|
||||
CONFIG_FB_MSM_WRITEBACK_MSM_PANEL=y
|
||||
CONFIG_FB_MSM_LVDS_MIPI_PANEL_DETECT=y
|
||||
CONFIG_FB_MSM_HDMI_MSM_PANEL=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_DYNAMIC_MINORS=y
|
||||
CONFIG_SND_USB_AUDIO=y
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_SOC_MSM8960=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_MAGICMOUSE=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_SUSPEND=y
|
||||
CONFIG_USB_MON=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_EHSET=y
|
||||
CONFIG_USB_EHCI_MSM=y
|
||||
CONFIG_USB_EHCI_MSM_HSIC=y
|
||||
CONFIG_USB_ACM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_STORAGE_DEBUG=y
|
||||
CONFIG_USB_STORAGE_DATAFAB=y
|
||||
CONFIG_USB_STORAGE_FREECOM=y
|
||||
CONFIG_USB_STORAGE_ISD200=y
|
||||
CONFIG_USB_STORAGE_USBAT=y
|
||||
CONFIG_USB_STORAGE_SDDR09=y
|
||||
CONFIG_USB_STORAGE_SDDR55=y
|
||||
CONFIG_USB_STORAGE_JUMPSHOT=y
|
||||
CONFIG_USB_STORAGE_ALAUDA=y
|
||||
CONFIG_USB_STORAGE_ONETOUCH=y
|
||||
CONFIG_USB_STORAGE_KARMA=y
|
||||
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
|
||||
CONFIG_USB_SERIAL=y
|
||||
CONFIG_USB_SERIAL_QUALCOMM=y
|
||||
CONFIG_USB_SERIAL_CSVT=y
|
||||
CONFIG_USB_EHSET_TEST_FIXTURE=y
|
||||
CONFIG_USB_QCOM_DIAG_BRIDGE=y
|
||||
CONFIG_USB_QCOM_MDM_BRIDGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DEBUG_FILES=y
|
||||
CONFIG_USB_CI13XXX_MSM=y
|
||||
CONFIG_USB_G_ANDROID=y
|
||||
CONFIG_USB_ANDROID_RMNET_CTRL_SMD=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_PERF_PROFILING=y
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
CONFIG_MMC_CLKGATE=y
|
||||
CONFIG_MMC_PARANOID_SD_INIT=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
CONFIG_MMC_TEST=m
|
||||
CONFIG_MMC_MSM=y
|
||||
CONFIG_MMC_MSM_CARD_HW_DETECTION=y
|
||||
CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT=y
|
||||
# CONFIG_MMC_MSM_SDC2_SUPPORT is not set
|
||||
CONFIG_MMC_MSM_SDC3_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SDC3_WP_SUPPORT=y
|
||||
CONFIG_MMC_MSM_SPS_SUPPORT=y
|
||||
CONFIG_LEDS_PM8XXX=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_SWITCH=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_DRV_MSM is not set
|
||||
CONFIG_RTC_DRV_PM8XXX=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_ANDROID_BINDER_IPC=y
|
||||
CONFIG_ANDROID_LOGGER=y
|
||||
CONFIG_ANDROID_RAM_CONSOLE=y
|
||||
CONFIG_ANDROID_TIMED_GPIO=y
|
||||
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
|
||||
CONFIG_MSM_SSBI=y
|
||||
CONFIG_SPS=y
|
||||
CONFIG_SPS_SUPPORT_BAMDMA=y
|
||||
CONFIG_MSM_IOMMU=y
|
||||
CONFIG_MOBICORE_SUPPORT=m
|
||||
CONFIG_MOBICORE_API=m
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_CIFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_SECTION_MISMATCH=y
|
||||
CONFIG_LOCKUP_DETECTOR=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_TIMER_STATS=y
|
||||
CONFIG_DEBUG_KMEMLEAK=y
|
||||
CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
CONFIG_DEBUG_SPINLOCK=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
CONFIG_DEBUG_ATOMIC_SLEEP=y
|
||||
CONFIG_DEBUG_STACK_USAGE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_MEMORY_INIT=y
|
||||
CONFIG_DEBUG_LIST=y
|
||||
CONFIG_FAULT_INJECTION=y
|
||||
CONFIG_FAILSLAB=y
|
||||
CONFIG_FAIL_PAGE_ALLOC=y
|
||||
CONFIG_FAULT_INJECTION_DEBUG_FS=y
|
||||
CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
|
||||
CONFIG_DEBUG_PAGEALLOC=y
|
||||
CONFIG_ENABLE_DEFAULT_TRACERS=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_PID_IN_CONTEXTIDR=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRYPTO_DEV_QCRYPTO=m
|
||||
CONFIG_CRYPTO_DEV_QCE=m
|
||||
CONFIG_CRYPTO_DEV_QCEDEV=m
|
||||
CONFIG_CRC_CCITT=y
|
||||
297
arch/arm/configs/msm9615_defconfig
Normal file
297
arch/arm/configs/msm9615_defconfig
Normal file
@@ -0,0 +1,297 @@
|
||||
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_DEBUG=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_RESOURCE_COUNTERS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
# CONFIG_FAIR_GROUP_SCHED is not set
|
||||
CONFIG_RT_GROUP_SCHED=y
|
||||
CONFIG_NAMESPACES=y
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_USER_NS is not set
|
||||
# CONFIG_PID_NS is not set
|
||||
CONFIG_RELAY=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_PANIC_TIMEOUT=5
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_PERF_EVENTS is not set
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
CONFIG_ARCH_MSM=y
|
||||
CONFIG_ARCH_MSM9615=y
|
||||
CONFIG_MACH_MSM9615_CDP=y
|
||||
CONFIG_MACH_MSM9615_MTP=y
|
||||
# CONFIG_MSM_STACKED_MEMORY is not set
|
||||
CONFIG_CPU_HAS_L2_PMU=y
|
||||
# CONFIG_MSM_FIQ_SUPPORT is not set
|
||||
# CONFIG_MSM_PROC_COMM is not set
|
||||
CONFIG_MSM_SMD=y
|
||||
CONFIG_MSM_SMD_PKG4=y
|
||||
CONFIG_MSM_BAM_DMUX=y
|
||||
# CONFIG_MSM_RESET_MODEM is not set
|
||||
CONFIG_MSM_IPC_ROUTER=y
|
||||
CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
|
||||
CONFIG_MSM_SUBSYSTEM_RESTART=y
|
||||
# CONFIG_MSM_SYSMON_COMM is not set
|
||||
CONFIG_MSM_MODEM_8960=y
|
||||
CONFIG_MSM_LPASS_8960=y
|
||||
CONFIG_MSM_RPM_LOG=y
|
||||
CONFIG_MSM_RPM_STATS_LOG=y
|
||||
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
|
||||
CONFIG_MSM_BUS_SCALING=y
|
||||
CONFIG_MSM_BUS_RPM_MULTI_TIER_ENABLED=y
|
||||
CONFIG_MSM_WATCHDOG=y
|
||||
CONFIG_MSM_DLOAD_MODE=y
|
||||
CONFIG_SWP_EMULATE=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_VMALLOC_RESERVE=0x19000000
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_IPV6=y
|
||||
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET6_XFRM_MODE_BEET is not set
|
||||
# CONFIG_IPV6_SIT is not set
|
||||
CONFIG_IPV6_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6_SUBTREES=y
|
||||
# CONFIG_ANDROID_PARANOID_NETWORK is not set
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_NETFILTER_DEBUG=y
|
||||
CONFIG_NETFILTER_NETLINK_QUEUE=y
|
||||
CONFIG_NETFILTER_NETLINK_LOG=y
|
||||
CONFIG_NF_CONNTRACK=y
|
||||
CONFIG_NF_CONNTRACK_EVENTS=y
|
||||
CONFIG_NF_CONNTRACK_TIMESTAMP=y
|
||||
CONFIG_NF_CONNTRACK_FTP=y
|
||||
CONFIG_NF_CONNTRACK_PPTP=y
|
||||
CONFIG_NF_CONNTRACK_SIP=y
|
||||
CONFIG_NF_CONNTRACK_TFTP=y
|
||||
CONFIG_NETFILTER_XT_MARK=y
|
||||
CONFIG_NETFILTER_XT_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
|
||||
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
|
||||
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
|
||||
CONFIG_IP_SET=y
|
||||
CONFIG_NF_CONNTRACK_IPV4=y
|
||||
CONFIG_IP_NF_IPTABLES=y
|
||||
CONFIG_IP_NF_MATCH_AH=y
|
||||
CONFIG_IP_NF_MATCH_ECN=y
|
||||
CONFIG_IP_NF_MATCH_TTL=y
|
||||
CONFIG_IP_NF_FILTER=y
|
||||
CONFIG_IP_NF_TARGET_REJECT=y
|
||||
CONFIG_IP_NF_TARGET_REJECT_SKERR=y
|
||||
CONFIG_IP_NF_TARGET_ULOG=y
|
||||
CONFIG_NF_NAT=y
|
||||
CONFIG_IP_NF_TARGET_MASQUERADE=y
|
||||
CONFIG_IP_NF_TARGET_NETMAP=y
|
||||
CONFIG_IP_NF_TARGET_REDIRECT=y
|
||||
CONFIG_IP_NF_MANGLE=y
|
||||
CONFIG_IP_NF_TARGET_ECN=y
|
||||
CONFIG_IP_NF_TARGET_TTL=y
|
||||
CONFIG_IP_NF_RAW=y
|
||||
CONFIG_NF_CONNTRACK_IPV6=y
|
||||
CONFIG_IP6_NF_IPTABLES=y
|
||||
CONFIG_IP6_NF_MATCH_AH=y
|
||||
CONFIG_IP6_NF_MATCH_FRAG=y
|
||||
CONFIG_IP6_NF_MATCH_OPTS=y
|
||||
CONFIG_IP6_NF_MATCH_HL=y
|
||||
CONFIG_IP6_NF_MATCH_IPV6HEADER=y
|
||||
CONFIG_IP6_NF_MATCH_MH=y
|
||||
CONFIG_IP6_NF_MATCH_RT=y
|
||||
CONFIG_IP6_NF_FILTER=y
|
||||
CONFIG_IP6_NF_TARGET_REJECT=y
|
||||
CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
|
||||
CONFIG_IP6_NF_MANGLE=y
|
||||
CONFIG_IP6_NF_RAW=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_TESTS=m
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
# CONFIG_ANDROID_PMEM is not set
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_TGT=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_SCH=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_MSM_RMNET is not set
|
||||
CONFIG_MSM_RMNET_BAM=y
|
||||
CONFIG_ATH6K_LEGACY_EXT=y
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_EVBUG=m
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_PMIC8XXX_PWRKEY=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SERIAL_MSM=y
|
||||
CONFIG_SERIAL_MSM_CONSOLE=y
|
||||
# CONFIG_SERIAL_MSM_CLOCK_CONTROL is not set
|
||||
CONFIG_SERIAL_MSM_HSL=y
|
||||
CONFIG_SERIAL_MSM_HSL_CONSOLE=y
|
||||
CONFIG_DIAG_CHAR=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_MSM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_I2C_MSM is not set
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_QUP=y
|
||||
CONFIG_SPI_SPIDEV=m
|
||||
CONFIG_SLIMBUS_MSM_CTRL=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
# CONFIG_BATTERY_MSM is not set
|
||||
CONFIG_SENSORS_PM8XXX_ADC=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_TSENS8960=y
|
||||
CONFIG_THERMAL_PM8XXX=y
|
||||
CONFIG_MFD_PM8018_CORE=y
|
||||
CONFIG_WCD9310_CODEC=y
|
||||
CONFIG_REGULATOR_PM8XXX=y
|
||||
CONFIG_REGULATOR_MSM_GPIO=y
|
||||
CONFIG_ION=y
|
||||
CONFIG_ION_MSM=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_SOC_MDM9615=y
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_EHSET=y
|
||||
CONFIG_USB_EHCI_MSM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_STORAGE_DEBUG=y
|
||||
CONFIG_USB_STORAGE_DATAFAB=y
|
||||
CONFIG_USB_STORAGE_FREECOM=y
|
||||
CONFIG_USB_STORAGE_ISD200=y
|
||||
CONFIG_USB_STORAGE_USBAT=y
|
||||
CONFIG_USB_STORAGE_SDDR09=y
|
||||
CONFIG_USB_STORAGE_SDDR55=y
|
||||
CONFIG_USB_STORAGE_JUMPSHOT=y
|
||||
CONFIG_USB_STORAGE_ALAUDA=y
|
||||
CONFIG_USB_STORAGE_ONETOUCH=y
|
||||
CONFIG_USB_STORAGE_KARMA=y
|
||||
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
|
||||
CONFIG_USB_EHSET_TEST_FIXTURE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_CI13XXX_MSM=m
|
||||
CONFIG_USB_CI13XXX_MSM_HSIC=m
|
||||
CONFIG_USB_G_ANDROID=y
|
||||
CONFIG_RMNET_SMD_CTL_CHANNEL="DATA36_CNTL"
|
||||
CONFIG_RMNET_SMD_DATA_CHANNEL="DATA36"
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_PERF_PROFILING=y
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
CONFIG_MMC_CLKGATE=y
|
||||
CONFIG_MMC_EMBEDDED_SDIO=y
|
||||
CONFIG_MMC_PARANOID_SD_INIT=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
CONFIG_MMC_TEST=m
|
||||
CONFIG_MMC_MSM=y
|
||||
CONFIG_MMC_MSM_CARD_HW_DETECTION=y
|
||||
CONFIG_MMC_MSM_SPS_SUPPORT=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_PM8XXX=y
|
||||
CONFIG_SWITCH=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_INTF_ALARM is not set
|
||||
# CONFIG_RTC_DRV_MSM is not set
|
||||
CONFIG_RTC_DRV_PM8XXX=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_ANDROID_LOGGER=y
|
||||
CONFIG_MSM_SSBI=y
|
||||
CONFIG_SPS=y
|
||||
CONFIG_USB_BAM=y
|
||||
CONFIG_SPS_SUPPORT_BAMDMA=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_YAFFS_FS=y
|
||||
CONFIG_YAFFS_DISABLE_TAGS_ECC=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_TIMER_STATS=y
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_MEMORY_INIT=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_KEYS=y
|
||||
CONFIG_CRYPTO_AUTHENC=y
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_MD4=y
|
||||
CONFIG_CRYPTO_MD5=y
|
||||
CONFIG_CRYPTO_SHA1=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRYPTO_DEV_QCRYPTO=m
|
||||
CONFIG_CRYPTO_DEV_QCE=m
|
||||
CONFIG_CRYPTO_DEV_QCEDEV=m
|
||||
CONFIG_CRC_CCITT=y
|
||||
CONFIG_LIBCRC32C=y
|
||||
107
arch/arm/configs/msm9625_defconfig
Normal file
107
arch/arm/configs/msm9625_defconfig
Normal file
@@ -0,0 +1,107 @@
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_DEBUG=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_RESOURCE_COUNTERS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
# CONFIG_FAIR_GROUP_SCHED is not set
|
||||
CONFIG_RT_GROUP_SCHED=y
|
||||
CONFIG_NAMESPACES=y
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_USER_NS is not set
|
||||
# CONFIG_PID_NS is not set
|
||||
CONFIG_RELAY=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=m
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_ARCH_MSM=y
|
||||
CONFIG_ARCH_MSM9625=y
|
||||
# CONFIG_MSM_STACKED_MEMORY is not set
|
||||
CONFIG_CPU_HAS_L2_PMU=y
|
||||
# CONFIG_MSM_FIQ_SUPPORT is not set
|
||||
# CONFIG_MSM_PROC_COMM is not set
|
||||
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_ARM_ARCH_TIMER=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_VMALLOC_RESERVE=0x19000000
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_MISC_DEVICES=y
|
||||
# CONFIG_ANDROID_PMEM is not set
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
CONFIG_INPUT_GPIO=m
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_MSM_HSL=y
|
||||
CONFIG_SERIAL_MSM_HSL_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_MFD_SUPPORT is not set
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_TIMER_STATS=y
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_MEMORY_INIT=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_KEYS=y
|
||||
CONFIG_CRYPTO_AUTHENC=y
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_MD4=y
|
||||
CONFIG_CRYPTO_MD5=y
|
||||
CONFIG_CRYPTO_SHA1=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
CONFIG_CRYPTO_ARC4=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
CONFIG_CRC_CCITT=y
|
||||
CONFIG_CRC16=y
|
||||
CONFIG_LIBCRC32C=y
|
||||
@@ -14,6 +14,11 @@
|
||||
|
||||
struct clock_event_device;
|
||||
|
||||
/*
|
||||
* Setup a per-cpu timer, whether it be a local timer or dummy broadcast
|
||||
*/
|
||||
void percpu_timer_setup(void);
|
||||
|
||||
struct local_timer_ops {
|
||||
int (*setup)(struct clock_event_device *);
|
||||
void (*stop)(struct clock_event_device *);
|
||||
|
||||
@@ -7,6 +7,13 @@
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/mmc/card.h>
|
||||
#include <linux/mmc/sdio_func.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/msm_bus.h>
|
||||
|
||||
#define SDC_DAT1_DISABLE 0
|
||||
#define SDC_DAT1_ENABLE 1
|
||||
#define SDC_DAT1_ENWAKE 2
|
||||
#define SDC_DAT1_DISWAKE 3
|
||||
|
||||
struct embedded_sdio_data {
|
||||
struct sdio_cis cis;
|
||||
@@ -15,6 +22,102 @@ struct embedded_sdio_data {
|
||||
int num_funcs;
|
||||
};
|
||||
|
||||
/* This structure keeps information per regulator */
|
||||
struct msm_mmc_reg_data {
|
||||
/* voltage regulator handle */
|
||||
struct regulator *reg;
|
||||
/* regulator name */
|
||||
const char *name;
|
||||
/* voltage level to be set */
|
||||
unsigned int low_vol_level;
|
||||
unsigned int high_vol_level;
|
||||
/* Load values for low power and high power mode */
|
||||
unsigned int lpm_uA;
|
||||
unsigned int hpm_uA;
|
||||
/*
|
||||
* is set voltage supported for this regulator?
|
||||
* false => set voltage is not supported
|
||||
* true => set voltage is supported
|
||||
*
|
||||
* Some regulators (like gpio-regulators, LVS (low voltage swtiches)
|
||||
* PMIC regulators) dont have the capability to call
|
||||
* regulator_set_voltage or regulator_set_optimum_mode
|
||||
* Use this variable to indicate if its a such regulator or not
|
||||
*/
|
||||
bool set_voltage_sup;
|
||||
/* is this regulator enabled? */
|
||||
bool is_enabled;
|
||||
/* is this regulator needs to be always on? */
|
||||
bool always_on;
|
||||
/* is low power mode setting required for this regulator? */
|
||||
bool lpm_sup;
|
||||
};
|
||||
|
||||
/*
|
||||
* This structure keeps information for all the
|
||||
* regulators required for a SDCC slot.
|
||||
*/
|
||||
struct msm_mmc_slot_reg_data {
|
||||
struct msm_mmc_reg_data *vdd_data; /* keeps VDD/VCC regulator info */
|
||||
struct msm_mmc_reg_data *vdd_io_data; /* keeps VDD IO regulator info */
|
||||
};
|
||||
|
||||
struct msm_mmc_gpio {
|
||||
u32 no;
|
||||
const char *name;
|
||||
bool is_always_on;
|
||||
bool is_enabled;
|
||||
};
|
||||
|
||||
struct msm_mmc_gpio_data {
|
||||
struct msm_mmc_gpio *gpio;
|
||||
u8 size;
|
||||
};
|
||||
|
||||
struct msm_mmc_pad_pull {
|
||||
enum msm_tlmm_pull_tgt no;
|
||||
u32 val;
|
||||
};
|
||||
|
||||
struct msm_mmc_pad_pull_data {
|
||||
struct msm_mmc_pad_pull *on;
|
||||
struct msm_mmc_pad_pull *off;
|
||||
u8 size;
|
||||
};
|
||||
|
||||
struct msm_mmc_pad_drv {
|
||||
enum msm_tlmm_hdrive_tgt no;
|
||||
u32 val;
|
||||
};
|
||||
|
||||
struct msm_mmc_pad_drv_data {
|
||||
struct msm_mmc_pad_drv *on;
|
||||
struct msm_mmc_pad_drv *off;
|
||||
u8 size;
|
||||
};
|
||||
|
||||
struct msm_mmc_pad_data {
|
||||
struct msm_mmc_pad_pull_data *pull;
|
||||
struct msm_mmc_pad_drv_data *drv;
|
||||
};
|
||||
|
||||
struct msm_mmc_pin_data {
|
||||
/*
|
||||
* = 1 if controller pins are using gpios
|
||||
* = 0 if controller has dedicated MSM pads
|
||||
*/
|
||||
u8 is_gpio;
|
||||
u8 cfg_sts;
|
||||
struct msm_mmc_gpio_data *gpio_data;
|
||||
struct msm_mmc_pad_data *pad_data;
|
||||
};
|
||||
|
||||
struct msm_mmc_bus_voting_data {
|
||||
struct msm_bus_scale_pdata *use_cases;
|
||||
unsigned int *bw_vecs;
|
||||
unsigned int bw_vecs_size;
|
||||
};
|
||||
|
||||
struct mmc_platform_data {
|
||||
unsigned int ocr_mask; /* available voltages */
|
||||
int built_in; /* built-in device flag */
|
||||
@@ -23,6 +126,40 @@ struct mmc_platform_data {
|
||||
unsigned int (*status)(struct device *);
|
||||
struct embedded_sdio_data *embedded_sdio;
|
||||
int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
|
||||
/*
|
||||
* XPC controls the maximum current in the
|
||||
* default speed mode of SDXC card.
|
||||
*/
|
||||
unsigned int xpc_cap;
|
||||
/* Supported UHS-I Modes */
|
||||
unsigned int uhs_caps;
|
||||
void (*sdio_lpm_gpio_setup)(struct device *, unsigned int);
|
||||
unsigned int status_irq;
|
||||
unsigned int status_gpio;
|
||||
/* Indicates the polarity of the GPIO line when card is inserted */
|
||||
bool is_status_gpio_active_low;
|
||||
unsigned int sdiowakeup_irq;
|
||||
unsigned long irq_flags;
|
||||
unsigned long mmc_bus_width;
|
||||
int (*wpswitch) (struct device *);
|
||||
unsigned int msmsdcc_fmin;
|
||||
unsigned int msmsdcc_fmid;
|
||||
unsigned int msmsdcc_fmax;
|
||||
bool nonremovable;
|
||||
bool pclk_src_dfab;
|
||||
unsigned int mpm_sdiowakeup_int;
|
||||
unsigned int wpswitch_gpio;
|
||||
unsigned char wpswitch_polarity;
|
||||
struct msm_mmc_slot_reg_data *vreg_data;
|
||||
int is_sdio_al_client;
|
||||
unsigned int *sup_clk_table;
|
||||
unsigned char sup_clk_cnt;
|
||||
struct msm_mmc_pin_data *pin_data;
|
||||
bool disable_bam;
|
||||
bool disable_runtime_pm;
|
||||
bool disable_cmd23;
|
||||
u32 cpu_dma_latency;
|
||||
struct msm_mmc_bus_voting_data *msm_bus_voting_data;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@@ -82,3 +82,8 @@
|
||||
#define VFPOPDESC_UNUSED_BIT (24)
|
||||
#define VFPOPDESC_UNUSED_MASK (0xFF << VFPOPDESC_UNUSED_BIT)
|
||||
#define VFPOPDESC_OPDESC_MASK (~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK))
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
int vfp_pm_suspend(void);
|
||||
void vfp_pm_resume(void);
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,34 +1,372 @@
|
||||
obj-y += io.o idle.o timer.o
|
||||
obj-y += clock.o
|
||||
obj-y += subsystem_map.o
|
||||
obj-$(CONFIG_DEBUG_FS) += clock-debug.o
|
||||
|
||||
obj-$(CONFIG_MSM_VIC) += irq-vic.o
|
||||
obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o iommu_domains.o
|
||||
|
||||
obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
|
||||
obj-$(CONFIG_ARCH_MSM7X30) += dma.o
|
||||
obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
|
||||
|
||||
obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
|
||||
|
||||
obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
|
||||
obj-$(CONFIG_MSM_SMD) += last_radio_log.o
|
||||
obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
|
||||
|
||||
CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
|
||||
|
||||
obj-y += io.o dma.o memory.o
|
||||
ifndef CONFIG_ARM_ARCH_TIMER
|
||||
obj-y += timer.o
|
||||
endif
|
||||
obj-y += clock.o clock-voter.o clock-dummy.o
|
||||
obj-y += modem_notifier.o subsystem_map.o
|
||||
obj-$(CONFIG_CPU_FREQ_MSM) += cpufreq.o
|
||||
obj-$(CONFIG_DEBUG_FS) += nohlt.o clock-debug.o
|
||||
obj-$(CONFIG_KEXEC) += msm_kexec.o
|
||||
|
||||
obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o
|
||||
ifndef CONFIG_ARCH_MSM8X60
|
||||
obj-$(CONFIG_MSM_PROC_COMM) += clock-pcom.o
|
||||
obj-$(CONFIG_MSM_PROC_COMM) += vreg.o mpp.o
|
||||
ifdef CONFIG_MSM_PROC_COMM
|
||||
ifndef CONFIG_ARCH_FSM9XXX
|
||||
obj-$(CONFIG_REGULATOR) += footswitch-pcom.o
|
||||
endif
|
||||
obj-$(CONFIG_DEBUG_FS) += pmic_debugfs.o
|
||||
endif
|
||||
endif
|
||||
|
||||
obj-y += acpuclock.o
|
||||
obj-$(CONFIG_ARCH_MSM7X27) += acpuclock-7627.o clock-pll.o
|
||||
obj-$(CONFIG_ARCH_MSM_SCORPION) += pmu.o
|
||||
obj-$(CONFIG_ARCH_MSM_KRAIT) += msm-krait-l2-accessors.o pmu.o
|
||||
obj-$(CONFIG_ARCH_MSM7X27A) += pmu.o
|
||||
|
||||
ifndef CONFIG_MSM_SMP
|
||||
obj-$(CONFIG_ARCH_MSM_SCORPION) += msm_fault_handlers.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_MSM_VIC) += irq-vic.o
|
||||
|
||||
ifdef CONFIG_ARCH_QSD8X50
|
||||
obj-$(CONFIG_MSM_SOC_REV_NONE) += acpuclock-8x50.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_SMP) += headsmp.o
|
||||
ifdef CONFIG_ARCH_MSM8625
|
||||
obj-$(CONFIG_SMP) += platsmp-8625.o
|
||||
else
|
||||
obj-$(CONFIG_SMP) += platsmp.o
|
||||
endif
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
|
||||
|
||||
obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
|
||||
obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
|
||||
obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
|
||||
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
|
||||
obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
|
||||
obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
|
||||
obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o
|
||||
obj-$(CONFIG_MSM_CPU_AVS) += avs.o
|
||||
obj-$(CONFIG_MSM_AVS_HW) += avs_hw.o
|
||||
obj-$(CONFIG_CPU_V6) += idle-v6.o
|
||||
obj-$(CONFIG_CPU_V7) += idle-v7.o
|
||||
obj-$(CONFIG_MSM_JTAG) += jtag.o
|
||||
|
||||
obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o
|
||||
msm-etm-objs := etm.o
|
||||
obj-$(CONFIG_MSM_ETM) += msm-etm.o
|
||||
obj-$(CONFIG_MSM_QDSS) += qdss.o qdss-etb.o qdss-tpiu.o qdss-funnel.o qdss-etm.o
|
||||
|
||||
quiet_cmd_mkrpcsym = MKCAP $@
|
||||
cmd_mkrpcsym = $(PERL) $(srctree)/$(src)/mkrpcsym.pl $< $@
|
||||
|
||||
target += smd_rpc_sym.c
|
||||
$(obj)/smd_rpc_sym.c: $(src)/smd_rpc_sym $(src)/mkrpcsym.pl
|
||||
$(call if_changed,mkrpcsym)
|
||||
|
||||
obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
|
||||
obj-$(CONFIG_MSM_SECURE_IO) += scm-io.o
|
||||
obj-$(CONFIG_MSM_PIL) += peripheral-loader.o
|
||||
obj-$(CONFIG_MSM_PIL) += scm-pas.o
|
||||
obj-$(CONFIG_MSM_PIL_QDSP6V3) += pil-q6v3.o
|
||||
obj-$(CONFIG_MSM_PIL_QDSP6V4) += pil-q6v4.o
|
||||
obj-$(CONFIG_MSM_PIL_LPASS_QDSP6V5) += pil-q6v5.o pil-q6v5-lpass.o
|
||||
obj-$(CONFIG_MSM_PIL_MSS_QDSP6V5) += pil-q6v5.o pil-q6v5-mss.o
|
||||
obj-$(CONFIG_MSM_PIL_MBA) += pil-mba.o
|
||||
obj-$(CONFIG_MSM_PIL_RIVA) += pil-riva.o
|
||||
obj-$(CONFIG_MSM_PIL_TZAPPS) += pil-tzapps.o
|
||||
obj-$(CONFIG_MSM_PIL_VIDC) += pil-vidc.o
|
||||
obj-$(CONFIG_MSM_PIL_MODEM) += pil-modem.o
|
||||
obj-$(CONFIG_MSM_PIL_DSPS) += pil-dsps.o
|
||||
obj-$(CONFIG_MSM_PIL_GSS) += pil-gss.o
|
||||
obj-$(CONFIG_MSM_PIL_PRONTO) += pil-pronto.o
|
||||
obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
|
||||
obj-$(CONFIG_ARCH_FSM9XXX) += sirc-fsm9xxx.o
|
||||
obj-$(CONFIG_MSM_FIQ_SUPPORT) += fiq_glue.o
|
||||
obj-$(CONFIG_MACH_TROUT) += board-trout-rfkill.o
|
||||
obj-$(CONFIG_MSM_SDIO_AL) += sdio_al.o
|
||||
obj-$(CONFIG_MSM_SDIO_AL) += sdio_al_test.o
|
||||
obj-$(CONFIG_MSM_SDIO_AL) += sdio_al_dloader.o
|
||||
obj-$(CONFIG_MSM_SDIO_DMUX) += sdio_dmux.o
|
||||
obj-$(CONFIG_MSM_BAM_DMUX) += bam_dmux.o
|
||||
obj-$(CONFIG_MSM_SMD_LOGGING) += smem_log.o
|
||||
obj-$(CONFIG_MSM_IPC_LOGGING) += ipc_logging.o
|
||||
ifdef CONFIG_DEBUG_FS
|
||||
obj-$(CONFIG_MSM_IPC_LOGGING) += ipc_logging_debug.o
|
||||
endif
|
||||
obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o remote_spinlock.o smd_private.o
|
||||
obj-y += socinfo.o
|
||||
ifndef CONFIG_ARCH_MSM9615
|
||||
ifndef CONFIG_ARCH_APQ8064
|
||||
ifndef CONFIG_ARCH_MSM8960
|
||||
ifndef CONFIG_ARCH_MSM8X60
|
||||
ifndef CONFIG_ARCH_MSMCOPPER
|
||||
obj-$(CONFIG_MSM_SMD) += pmic.o
|
||||
obj-$(CONFIG_MSM_ONCRPCROUTER) += rpc_hsusb.o rpc_pmapp.o rpc_fsusb.o
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
ifndef CONFIG_ARCH_MSM8960
|
||||
ifndef CONFIG_ARCH_MSM8X60
|
||||
ifndef CONFIG_ARCH_APQ8064
|
||||
ifndef CONFIG_ARCH_MSMCOPPER
|
||||
ifndef CONFIG_ARCH_MSM9625
|
||||
obj-y += nand_partitions.o
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
obj-$(CONFIG_MSM_SDIO_TTY) += sdio_tty.o
|
||||
obj-$(CONFIG_MSM_SMD_TTY) += smd_tty.o
|
||||
obj-$(CONFIG_MSM_SMD_QMI) += smd_qmi.o
|
||||
obj-$(CONFIG_MSM_SMD_PKT) += smd_pkt.o
|
||||
obj-$(CONFIG_MSM_SDIO_CMUX) += sdio_cmux.o
|
||||
obj-$(CONFIG_MSM_DSPS) += msm_dsps.o
|
||||
obj-$(CONFIG_MSM_SDIO_CTL) += sdio_ctl.o
|
||||
obj-$(CONFIG_MSM_SMD_NMEA) += smd_nmea.o
|
||||
obj-$(CONFIG_MSM_RESET_MODEM) += reset_modem.o
|
||||
obj-$(CONFIG_MSM_IPC_ROUTER_SMD_XPRT) += ipc_router_smd_xprt.o
|
||||
obj-$(CONFIG_MSM_ONCRPCROUTER) += smd_rpcrouter.o
|
||||
obj-$(CONFIG_MSM_ONCRPCROUTER) += smd_rpcrouter_device.o
|
||||
obj-$(CONFIG_MSM_IPC_ROUTER) += ipc_router.o
|
||||
obj-$(CONFIG_MSM_IPC_ROUTER)+= ipc_socket.o
|
||||
obj-$(CONFIG_DEBUG_FS) += smd_rpc_sym.o
|
||||
obj-$(CONFIG_MSM_ONCRPCROUTER) += smd_rpcrouter_servers.o
|
||||
obj-$(CONFIG_MSM_ONCRPCROUTER) += smd_rpcrouter_clients.o
|
||||
obj-$(CONFIG_MSM_ONCRPCROUTER) += smd_rpcrouter_xdr.o
|
||||
obj-$(CONFIG_MSM_ONCRPCROUTER) += rpcrouter_smd_xprt.o
|
||||
obj-$(CONFIG_MSM_RPC_SDIO_XPRT) += rpcrouter_sdio_xprt.o
|
||||
obj-$(CONFIG_MSM_RPC_PING) += ping_mdm_rpc_client.o
|
||||
obj-$(CONFIG_MSM_RPC_PROC_COMM_TEST) += proc_comm_test.o
|
||||
obj-$(CONFIG_MSM_RPC_PING) += ping_mdm_rpc_client.o ping_apps_server.o
|
||||
obj-$(CONFIG_MSM_RPC_OEM_RAPI) += oem_rapi_client.o
|
||||
obj-$(CONFIG_MSM_RPC_WATCHDOG) += rpc_dog_keepalive.o
|
||||
obj-$(CONFIG_MSM_RPCSERVER_WATCHDOG) += rpc_server_dog_keepalive.o
|
||||
obj-$(CONFIG_MSM_RPCSERVER_TIME_REMOTE) += rpc_server_time_remote.o
|
||||
obj-$(CONFIG_MSM_DALRPC) += dal.o
|
||||
obj-$(CONFIG_MSM_DALRPC_TEST) += dal_remotetest.o
|
||||
obj-$(CONFIG_ARCH_MSM7X30) += dal_axi.o
|
||||
obj-$(CONFIG_ARCH_MSM7X27A) += dal_axi.o
|
||||
obj-$(CONFIG_MSM_ADSP) += qdsp5/
|
||||
obj-$(CONFIG_MSM7KV2_AUDIO) += qdsp5v2/
|
||||
obj-$(CONFIG_MSM_RPCSERVER_HANDSET) += rpc_server_handset.o
|
||||
obj-$(CONFIG_MSM_QDSP6) += qdsp6/
|
||||
obj-$(CONFIG_MSM8X60_AUDIO) += qdsp6v2/
|
||||
obj-$(CONFIG_MSM_AUDIO_QDSP6) += qdsp6v2/
|
||||
obj-$(CONFIG_MSM_HW3D) += hw3d.o
|
||||
obj-$(CONFIG_PM) += pm-boot.o
|
||||
obj-$(CONFIG_MSM_PM8X60) += pm-8x60.o pm-data.o
|
||||
obj-$(CONFIG_MSM_IDLE_STATS) += pm-stats.o
|
||||
obj-$(CONFIG_MSM_PM2) += pm2.o
|
||||
obj-$(CONFIG_MSM_NOPM) += no-pm.o
|
||||
|
||||
obj-$(CONFIG_MSM_PCIE) += pcie.o pcie_irq.o
|
||||
|
||||
obj-$(CONFIG_MSM_SPM_V1) += spm.o
|
||||
obj-$(CONFIG_MSM_SPM_V2) += spm-v2.o spm_devices.o
|
||||
|
||||
obj-$(CONFIG_MSM_DMA_TEST) += dma_test.o
|
||||
obj-$(CONFIG_SURF_FFA_GPIO_KEYPAD) += keypad-surf-ffa.o
|
||||
|
||||
obj-$(CONFIG_ARCH_MSM7X01A) += board-halibut.o devices-msm7x01a.o clock-pcom-lookup.o
|
||||
obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o
|
||||
obj-$(CONFIG_MACH_TROUT) += board-trout-keypad.o board-trout-panel.o
|
||||
obj-$(CONFIG_MACH_TROUT) += htc_akm_cal.o htc_wifi_nvs.o htc_acoustic.o
|
||||
obj-$(CONFIG_MACH_TROUT) += board-trout-mmc.o board-trout-wifi.o
|
||||
obj-$(CONFIG_ARCH_QSD8X50) += devices-qsd8x50.o clock-pcom-lookup.o
|
||||
obj-$(CONFIG_MACH_QSD8X50_SURF) += board-qsd8x50.o
|
||||
obj-$(CONFIG_MACH_QSD8X50_FFA) += board-qsd8x50.o
|
||||
obj-$(CONFIG_ARCH_MSM8X60) += devices-msm8x60.o clock-local.o clock-8x60.o acpuclock-8x60.o clock-pll.o
|
||||
obj-$(CONFIG_ARCH_MSM8X60) += clock-rpm.o
|
||||
obj-$(CONFIG_ARCH_MSM8X60) += saw-regulator.o
|
||||
obj-$(CONFIG_ARCH_MSM8X60) += footswitch-8x60.o
|
||||
|
||||
ifdef CONFIG_MSM_RPM_REGULATOR
|
||||
obj-y += rpm-regulator.o
|
||||
obj-$(CONFIG_ARCH_MSM8X60) += rpm-regulator-8660.o
|
||||
obj-$(CONFIG_ARCH_MSM8960) += rpm-regulator-8960.o
|
||||
obj-$(CONFIG_ARCH_MSM9615) += rpm-regulator-9615.o
|
||||
obj-$(CONFIG_ARCH_MSM8930) += rpm-regulator-8930.o
|
||||
obj-$(CONFIG_ARCH_APQ8064) += rpm-regulator-8960.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_MSM_RPM_REGULATOR_SMD) += rpm-regulator-smd.o
|
||||
|
||||
ifdef CONFIG_MSM_SUBSYSTEM_RESTART
|
||||
obj-y += subsystem_notif.o
|
||||
obj-y += subsystem_restart.o
|
||||
obj-y += ramdump.o
|
||||
obj-$(CONFIG_ARCH_MSM8X60) += modem-8660.o lpass-8660.o
|
||||
endif
|
||||
obj-$(CONFIG_MSM_SYSMON_COMM) += sysmon.o
|
||||
obj-$(CONFIG_MSM_MODEM_8960) += modem-8960.o
|
||||
obj-$(CONFIG_MSM_LPASS_8960) += lpass-8960.o
|
||||
obj-$(CONFIG_MSM_WCNSS_SSR_8960) += wcnss-ssr-8960.o
|
||||
obj-$(CONFIG_MSM_GSS_SSR_8064) += gss-8064.o
|
||||
|
||||
ifdef CONFIG_CPU_IDLE
|
||||
obj-$(CONFIG_ARCH_APQ8064) += cpuidle.o
|
||||
obj-$(CONFIG_ARCH_MSM8960) += cpuidle.o
|
||||
obj-$(CONFIG_ARCH_MSM8X60) += cpuidle.o
|
||||
obj-$(CONFIG_ARCH_MSM9615) += cpuidle.o
|
||||
obj-$(CONFIG_ARCH_MSMCOPPER) += cpuidle.o
|
||||
endif
|
||||
|
||||
ifdef CONFIG_MSM_CAMERA_V4L2
|
||||
obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60-camera.o
|
||||
endif
|
||||
obj-$(CONFIG_ARCH_FSM9XXX) += devices-fsm9xxx.o
|
||||
obj-$(CONFIG_ARCH_FSM9XXX) += clock-fsm9xxx.o clock-local.o acpuclock-fsm9xxx.o
|
||||
obj-$(CONFIG_ARCH_FSM9XXX) += dfe-fsm9xxx.o rfic-fsm9xxx.o
|
||||
obj-$(CONFIG_ARCH_FSM9XXX) += restart-fsm9xxx.o xo-fsm9xxx.o
|
||||
|
||||
obj-$(CONFIG_MSM_WATCHDOG) += msm_watchdog.o
|
||||
obj-$(CONFIG_MSM_WATCHDOG) += msm_watchdog_asm.o
|
||||
obj-$(CONFIG_MACH_MSM8X60_RUMI3) += board-msm8x60.o
|
||||
obj-$(CONFIG_MACH_MSM8X60_SIM) += board-msm8x60.o
|
||||
obj-$(CONFIG_MACH_MSM8X60_SURF) += board-msm8x60.o
|
||||
obj-$(CONFIG_MACH_MSM8X60_FFA) += board-msm8x60.o
|
||||
obj-$(CONFIG_MACH_MSM8X60_FLUID) += board-msm8x60.o
|
||||
obj-$(CONFIG_MACH_MSM8X60_DRAGON) += board-msm8x60.o
|
||||
obj-$(CONFIG_MACH_TYPE_MSM8X60_FUSION) += board-msm8x60.o mdm.o
|
||||
obj-$(CONFIG_MACH_MSM8X60_FUSN_FFA) += board-msm8x60.o mdm.o
|
||||
obj-$(CONFIG_TROUT_H2W) += board-trout-h2w.o
|
||||
obj-$(CONFIG_TROUT_BATTCHG) += htc_battery.o
|
||||
obj-$(CONFIG_TROUT_PWRSINK) += htc_pwrsink.o
|
||||
obj-$(CONFIG_ARCH_MSM7X27) += clock-pcom-lookup.o
|
||||
obj-$(CONFIG_MACH_MSM7X27_SURF) += board-msm7x27.o devices-msm7x27.o
|
||||
obj-$(CONFIG_MACH_MSM7X27_FFA) += board-msm7x27.o devices-msm7x27.o
|
||||
obj-$(CONFIG_ARCH_MSM7X27A) += clock-pcom-lookup.o devices-msm7x27a.o
|
||||
board-7627a-all-objs += board-msm7627a-storage.o board-msm7627a-bt.o board-msm7627a-camera.o
|
||||
board-7627a-all-objs += board-msm7627a-display.o board-msm7627a-wlan.o board-msm7627a-io.o
|
||||
obj-$(CONFIG_MACH_MSM7X27A_RUMI3) += board-msm7x27a.o board-7627a-all.o
|
||||
obj-$(CONFIG_MACH_MSM7X27A_SURF) += board-msm7x27a.o board-7627a-all.o
|
||||
obj-$(CONFIG_MACH_MSM7X27A_FFA) += board-msm7x27a.o board-7627a-all.o
|
||||
obj-$(CONFIG_MACH_MSM7627A_QRD1) += board-qrd7627a.o board-7627a-all.o
|
||||
obj-$(CONFIG_MACH_MSM7627A_QRD3) += board-qrd7627a.o board-7627a-all.o
|
||||
obj-$(CONFIG_MACH_MSM7627A_EVB) += board-qrd7627a.o board-7627a-all.o
|
||||
obj-$(CONFIG_ARCH_MSM8625) += devices-msm7x27a.o clock-pcom-lookup.o mpm-8625.o
|
||||
obj-$(CONFIG_MACH_MSM8625_RUMI3) += board-msm7x27a.o
|
||||
obj-$(CONFIG_MACH_MSM8625_SURF) += board-msm7x27a.o board-7627a-all.o
|
||||
obj-$(CONFIG_MACH_MSM8625_EVB) += board-qrd7627a.o board-7627a-all.o
|
||||
obj-$(CONFIG_MACH_MSM8625_QRD7) += board-qrd7627a.o board-7627a-all.o
|
||||
obj-$(CONFIG_MACH_MSM8625_FFA) += board-msm7x27a.o board-7627a-all.o
|
||||
obj-$(CONFIG_MACH_MSM8625_EVT) += board-msm7x27a.o board-7627a-all.o
|
||||
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o memory_topology.o
|
||||
obj-$(CONFIG_ARCH_MSM7X30) += clock-local.o clock-7x30.o acpuclock-7x30.o clock-pll.o
|
||||
obj-$(CONFIG_MACH_MSM7X25_SURF) += board-msm7x27.o devices-msm7x25.o
|
||||
obj-$(CONFIG_MACH_MSM7X25_FFA) += board-msm7x27.o devices-msm7x25.o
|
||||
obj-$(CONFIG_ARCH_MSM8960) += clock-local.o clock-dss-8960.o clock-8960.o clock-rpm.o clock-pll.o
|
||||
obj-$(CONFIG_ARCH_MSM8960) += footswitch-8x60.o
|
||||
obj-$(CONFIG_ARCH_MSM8960) += acpuclock-8960.o
|
||||
obj-$(CONFIG_ARCH_MSM8960) += memory_topology.o
|
||||
obj-$(CONFIG_ARCH_MSM8960) += saw-regulator.o
|
||||
obj-$(CONFIG_ARCH_MSM8960) += devices-8960.o
|
||||
obj-$(CONFIG_ARCH_APQ8064) += devices-8960.o devices-8064.o
|
||||
board-8960-all-objs += board-8960.o board-8960-camera.o board-8960-display.o board-8960-pmic.o board-8960-storage.o board-8960-gpiomux.o
|
||||
board-8930-all-objs += board-8930.o board-8930-camera.o board-8930-display.o board-8930-pmic.o board-8930-storage.o board-8930-gpiomux.o devices-8930.o board-8930-gpu.o
|
||||
board-8064-all-objs += board-8064.o board-8064-pmic.o board-8064-storage.o board-8064-gpiomux.o board-8064-camera.o board-8064-display.o board-8064-gpu.o
|
||||
obj-$(CONFIG_MACH_MSM8960_SIM) += board-8960-all.o board-8960-regulator.o
|
||||
obj-$(CONFIG_MACH_MSM8960_RUMI3) += board-8960-all.o board-8960-regulator.o
|
||||
obj-$(CONFIG_MACH_MSM8960_CDP) += board-8960-all.o board-8960-regulator.o
|
||||
obj-$(CONFIG_MACH_MSM8960_MTP) += board-8960-all.o board-8960-regulator.o
|
||||
obj-$(CONFIG_MACH_MSM8960_FLUID) += board-8960-all.o board-8960-regulator.o
|
||||
obj-$(CONFIG_MACH_MSM8930_CDP) += board-8930-all.o board-8930-regulator.o
|
||||
obj-$(CONFIG_MACH_MSM8930_MTP) += board-8930-all.o board-8930-regulator.o
|
||||
obj-$(CONFIG_MACH_MSM8930_FLUID) += board-8930-all.o board-8930-regulator.o
|
||||
obj-$(CONFIG_PM8921_BMS) += bms-batterydata.o bms-batterydata-desay.o
|
||||
obj-$(CONFIG_MACH_APQ8064_SIM) += board-8064-all.o board-8064-regulator.o
|
||||
obj-$(CONFIG_MACH_APQ8064_RUMI3) += board-8064-all.o board-8064-regulator.o
|
||||
obj-$(CONFIG_MACH_APQ8064_CDP) += board-8064-all.o board-8064-regulator.o
|
||||
obj-$(CONFIG_MACH_APQ8064_MTP) += board-8064-all.o board-8064-regulator.o
|
||||
obj-$(CONFIG_MACH_APQ8064_LIQUID) += board-8064-all.o board-8064-regulator.o
|
||||
obj-$(CONFIG_MACH_MPQ8064_HRD) += board-8064-all.o board-8064-regulator.o
|
||||
obj-$(CONFIG_MACH_MPQ8064_DTV) += board-8064-all.o board-8064-regulator.o
|
||||
obj-$(CONFIG_ARCH_MSM9615) += board-9615.o devices-9615.o board-9615-regulator.o board-9615-gpiomux.o board-9615-storage.o board-9615-display.o
|
||||
obj-$(CONFIG_ARCH_MSM9615) += clock-local.o clock-9615.o acpuclock-9615.o clock-rpm.o clock-pll.o
|
||||
obj-$(CONFIG_ARCH_MSMCOPPER) += board-copper.o board-dt.o board-copper-regulator.o board-copper-gpiomux.o
|
||||
obj-$(CONFIG_ARCH_MSMCOPPER) += acpuclock-krait.o acpuclock-copper.o
|
||||
obj-$(CONFIG_ARCH_MSMCOPPER) += clock-local2.o clock-pll.o clock-copper.o
|
||||
obj-$(CONFIG_ARCH_MSMCOPPER) += gdsc.o
|
||||
obj-$(CONFIG_ARCH_MSM9625) += board-9625.o board-9625-gpiomux.o
|
||||
|
||||
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire.o board-sapphire-gpio.o
|
||||
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire-keypad.o board-sapphire-panel.o
|
||||
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire-mmc.o board-sapphire-wifi.o
|
||||
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire-rfkill.o msm_vibrator.o
|
||||
|
||||
CFLAGS_msm_vibrator.o += -Idrivers/staging/android
|
||||
|
||||
obj-$(CONFIG_ARCH_FSM9XXX) += board-fsm9xxx.o
|
||||
|
||||
obj-$(CONFIG_TROUT_BATTCHG) += htc_battery.o
|
||||
|
||||
obj-$(CONFIG_HTC_PWRSINK) += htc_pwrsink.o
|
||||
obj-$(CONFIG_HTC_HEADSET) += htc_headset.o
|
||||
obj-$(CONFIG_MSM_RMT_STORAGE_CLIENT) += rmt_storage_client.o
|
||||
obj-$(CONFIG_MSM_SDIO_SMEM) += sdio_smem.o
|
||||
obj-$(CONFIG_MSM_RPM) += rpm.o
|
||||
ifdef CONFIG_MSM_RPM
|
||||
obj-$(CONFIG_ARCH_APQ8064) += rpm_resources.o
|
||||
obj-$(CONFIG_ARCH_MSM8960) += rpm_resources.o
|
||||
obj-$(CONFIG_ARCH_MSM8X60) += rpm_resources.o
|
||||
obj-$(CONFIG_ARCH_MSM9615) += rpm_resources.o
|
||||
endif
|
||||
ifdef CONFIG_MSM_RPM_SMD
|
||||
obj-$(CONFIG_ARCH_MSMCOPPER) += lpm_levels.o
|
||||
endif
|
||||
obj-$(CONFIG_MSM_MPM) += mpm.o
|
||||
obj-$(CONFIG_MSM_RPM_STATS_LOG) += rpm_stats.o
|
||||
obj-$(CONFIG_MSM_RPM_LOG) += rpm_log.o
|
||||
obj-$(CONFIG_MSM_TZ_LOG) += tz_log.o
|
||||
obj-$(CONFIG_MSM_XO) += msm_xo.o
|
||||
obj-$(CONFIG_MSM_BUS_SCALING) += msm_bus/
|
||||
obj-$(CONFIG_MSM_BUSPM_DEV) += msm-buspm-dev.o
|
||||
|
||||
obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o iommu_domains.o
|
||||
|
||||
ifdef CONFIG_VCM
|
||||
obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60-vcm.o
|
||||
endif
|
||||
obj-$(CONFIG_MSM_OCMEM) += ocmem.o ocmem_allocator.o ocmem_notifier.o
|
||||
|
||||
obj-$(CONFIG_ARCH_MSM7X27) += gpiomux-7x27.o gpiomux-v1.o gpiomux.o
|
||||
obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
|
||||
obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
|
||||
obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
|
||||
obj-$(CONFIG_ARCH_MSM8960) += gpiomux-v2.o gpiomux.o
|
||||
obj-$(CONFIG_ARCH_APQ8064) += gpiomux-v2.o gpiomux.o
|
||||
obj-$(CONFIG_ARCH_MSM9615) += gpiomux-v2.o gpiomux.o
|
||||
obj-$(CONFIG_ARCH_MSMCOPPER) += gpiomux-v2.o gpiomux.o
|
||||
obj-$(CONFIG_ARCH_MSM9625) += gpiomux-v2.o gpiomux.o
|
||||
|
||||
|
||||
obj-$(CONFIG_MSM_SLEEP_STATS) += idle_stats.o
|
||||
obj-$(CONFIG_MSM_SLEEP_STATS_DEVICE) += idle_stats_device.o
|
||||
obj-$(CONFIG_MSM_DCVS) += msm_dcvs_scm.o msm_dcvs.o msm_dcvs_idle.o
|
||||
obj-$(CONFIG_MSM_RUN_QUEUE_STATS) += msm_rq_stats.o
|
||||
obj-$(CONFIG_MSM_SHOW_RESUME_IRQ) += msm_show_resume_irq.o
|
||||
obj-$(CONFIG_BT_MSM_PINTEST) += btpintest.o
|
||||
obj-$(CONFIG_MSM_FAKE_BATTERY) += fish_battery.o
|
||||
obj-$(CONFIG_MSM_RPC_VIBRATOR) += msm_vibrator.o
|
||||
obj-$(CONFIG_MSM_NATIVE_RESTART) += restart.o
|
||||
|
||||
obj-$(CONFIG_MSM_PROC_COMM_REGULATOR) += proccomm-regulator.o
|
||||
ifdef CONFIG_MSM_PROC_COMM_REGULATOR
|
||||
obj-$(CONFIG_MACH_MSM7X27_SURF) += board-msm7627-regulator.o
|
||||
obj-$(CONFIG_MACH_MSM7X27_FFA) += board-msm7627-regulator.o
|
||||
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30-regulator.o
|
||||
obj-$(CONFIG_ARCH_MSM7X27A) += board-msm7x27a-regulator.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_ARCH_MSM8960) += mdm2.o mdm_common.o
|
||||
obj-$(CONFIG_MSM_RTB) += msm_rtb.o
|
||||
obj-$(CONFIG_MSM_CACHE_ERP) += cache_erp.o
|
||||
obj-$(CONFIG_MSM_CACHE_DUMP) += msm_cache_dump.o
|
||||
|
||||
obj-$(CONFIG_MSM_HSIC_SYSMON) += hsic_sysmon.o
|
||||
obj-$(CONFIG_MSM_HSIC_SYSMON_TEST) += hsic_sysmon_test.o
|
||||
|
||||
obj-$(CONFIG_MSM_RPM_SMD) += rpm-smd.o
|
||||
|
||||
@@ -1,3 +1,60 @@
|
||||
zreladdr-y += 0x10008000
|
||||
params_phys-y := 0x10000100
|
||||
initrd_phys-y := 0x10800000
|
||||
# MSM7x01A
|
||||
zreladdr-$(CONFIG_ARCH_MSM7X01A) := 0x10008000
|
||||
params_phys-$(CONFIG_ARCH_MSM7X01A) := 0x10000100
|
||||
initrd_phys-$(CONFIG_ARCH_MSM7X01A) := 0x10800000
|
||||
|
||||
# MSM7x25
|
||||
zreladdr-$(CONFIG_ARCH_MSM7X25) := 0x00208000
|
||||
params_phys-$(CONFIG_ARCH_MSM7X25) := 0x00200100
|
||||
initrd_phys-$(CONFIG_ARCH_MSM7X25) := 0x0A000000
|
||||
|
||||
# MSM7x27
|
||||
zreladdr-$(CONFIG_ARCH_MSM7X27) := 0x00208000
|
||||
params_phys-$(CONFIG_ARCH_MSM7X27) := 0x00200100
|
||||
initrd_phys-$(CONFIG_ARCH_MSM7X27) := 0x0A000000
|
||||
|
||||
# MSM7x27A
|
||||
zreladdr-$(CONFIG_ARCH_MSM7X27A) := 0x00208000
|
||||
params_phys-$(CONFIG_ARCH_MSM7X27A) := 0x00200100
|
||||
|
||||
# MSM8625
|
||||
zreladdr-$(CONFIG_ARCH_MSM8625) := 0x00208000
|
||||
params_phys-$(CONFIG_ARCH_MSM8625) := 0x00200100
|
||||
|
||||
# MSM7x30
|
||||
zreladdr-$(CONFIG_ARCH_MSM7X30) := 0x00208000
|
||||
params_phys-$(CONFIG_ARCH_MSM7X30) := 0x00200100
|
||||
initrd_phys-$(CONFIG_ARCH_MSM7X30) := 0x01200000
|
||||
|
||||
ifeq ($(CONFIG_MSM_SOC_REV_A),y)
|
||||
# QSD8x50
|
||||
zreladdr-$(CONFIG_ARCH_QSD8X50) := 0x20008000
|
||||
params_phys-$(CONFIG_ARCH_QSD8X50) := 0x20000100
|
||||
initrd_phys-$(CONFIG_ARCH_QSD8X50) := 0x24000000
|
||||
endif
|
||||
|
||||
# MSM8x60
|
||||
zreladdr-$(CONFIG_ARCH_MSM8X60) := 0x40208000
|
||||
|
||||
# MSM8960
|
||||
zreladdr-$(CONFIG_ARCH_MSM8960) := 0x80208000
|
||||
|
||||
# MSM8930
|
||||
zreladdr-$(CONFIG_ARCH_MSM8930) := 0x80208000
|
||||
|
||||
# APQ8064
|
||||
zreladdr-$(CONFIG_ARCH_APQ8064) := 0x80208000
|
||||
|
||||
# MSMCOPPER
|
||||
zreladdr-$(CONFIG_ARCH_MSMCOPPER) := 0x00008000
|
||||
|
||||
# MSM9615
|
||||
zreladdr-$(CONFIG_ARCH_MSM9615) := 0x40808000
|
||||
|
||||
# MSM9625
|
||||
zreladdr-$(CONFIG_ARCH_MSM9625) := 0x20208000
|
||||
|
||||
# FSM9XXX
|
||||
zreladdr-$(CONFIG_ARCH_FSM9XXX) := 0x10008000
|
||||
params_phys-$(CONFIG_ARCH_FSM9XXX) := 0x10000100
|
||||
initrd_phys-$(CONFIG_ARCH_FSM9XXX) := 0x12000000
|
||||
|
||||
992
arch/arm/mach-msm/acpuclock-7627.c
Normal file
992
arch/arm/mach-msm/acpuclock-7627.c
Normal file
@@ -0,0 +1,992 @@
|
||||
/*
|
||||
* MSM architecture clock driver
|
||||
*
|
||||
* Copyright (C) 2007 Google, Inc.
|
||||
* Copyright (c) 2007-2012, Code Aurora Forum. All rights reserved.
|
||||
* Author: San Mehat <san@android.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/version.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sort.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/msm_iomap.h>
|
||||
#include <mach/socinfo.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/cpu.h>
|
||||
|
||||
#include "smd_private.h"
|
||||
#include "acpuclock.h"
|
||||
|
||||
#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
|
||||
#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
|
||||
#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
|
||||
|
||||
|
||||
#define POWER_COLLAPSE_KHZ 19200
|
||||
|
||||
/* Max CPU frequency allowed by hardware while in standby waiting for an irq. */
|
||||
#define MAX_WAIT_FOR_IRQ_KHZ 128000
|
||||
|
||||
/**
|
||||
* enum - For acpuclock PLL IDs
|
||||
*/
|
||||
enum {
|
||||
ACPU_PLL_0 = 0,
|
||||
ACPU_PLL_1,
|
||||
ACPU_PLL_2,
|
||||
ACPU_PLL_3,
|
||||
ACPU_PLL_4,
|
||||
ACPU_PLL_TCXO,
|
||||
ACPU_PLL_END,
|
||||
};
|
||||
|
||||
struct acpu_clk_src {
|
||||
struct clk *clk;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
static struct acpu_clk_src pll_clk[ACPU_PLL_END] = {
|
||||
[ACPU_PLL_0] = { .name = "pll0_clk" },
|
||||
[ACPU_PLL_1] = { .name = "pll1_clk" },
|
||||
[ACPU_PLL_2] = { .name = "pll2_clk" },
|
||||
[ACPU_PLL_4] = { .name = "pll4_clk" },
|
||||
};
|
||||
|
||||
struct clock_state {
|
||||
struct clkctl_acpu_speed *current_speed;
|
||||
struct mutex lock;
|
||||
uint32_t max_speed_delta_khz;
|
||||
struct clk *ebi1_clk;
|
||||
};
|
||||
|
||||
struct clkctl_acpu_speed {
|
||||
unsigned int use_for_scaling;
|
||||
unsigned int a11clk_khz;
|
||||
int pll;
|
||||
unsigned int a11clk_src_sel;
|
||||
unsigned int a11clk_src_div;
|
||||
unsigned int ahbclk_khz;
|
||||
unsigned int ahbclk_div;
|
||||
int vdd;
|
||||
unsigned int axiclk_khz;
|
||||
unsigned long lpj; /* loops_per_jiffy */
|
||||
/* Pointers in acpu_freq_tbl[] for max up/down steppings. */
|
||||
struct clkctl_acpu_speed *down[ACPU_PLL_END];
|
||||
struct clkctl_acpu_speed *up[ACPU_PLL_END];
|
||||
};
|
||||
|
||||
static struct clock_state drv_state = { 0 };
|
||||
static struct clkctl_acpu_speed *acpu_freq_tbl;
|
||||
|
||||
/*
|
||||
* ACPU freq tables used for different PLLs frequency combinations. The
|
||||
* correct table is selected during init.
|
||||
*
|
||||
* Table stepping up/down entries are calculated during boot to choose the
|
||||
* largest frequency jump that's less than max_speed_delta_khz on each PLL.
|
||||
*/
|
||||
|
||||
/* 7627 with GSM capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_pll4_0[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, 0, 30720 },
|
||||
{ 0, 120000, ACPU_PLL_0, 4, 7, 60000, 1, 3, 61440 },
|
||||
{ 1, 122880, ACPU_PLL_1, 1, 1, 61440, 1, 3, 61440 },
|
||||
{ 0, 200000, ACPU_PLL_2, 2, 5, 66667, 2, 4, 61440 },
|
||||
{ 1, 245760, ACPU_PLL_1, 1, 0, 122880, 1, 4, 61440 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 160000, 1, 5, 160000 },
|
||||
{ 0, 400000, ACPU_PLL_2, 2, 2, 133333, 2, 5, 160000 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 160000, 2, 6, 160000 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 200000, 2, 7, 200000 },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 7627 with CDMA capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_196_pll2_1200_pll4_0[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, 0, 24576 },
|
||||
{ 1, 98304, ACPU_PLL_1, 1, 1, 98304, 0, 3, 49152 },
|
||||
{ 0, 120000, ACPU_PLL_0, 4, 7, 60000, 1, 3, 49152 },
|
||||
{ 1, 196608, ACPU_PLL_1, 1, 0, 65536, 2, 4, 98304 },
|
||||
{ 0, 200000, ACPU_PLL_2, 2, 5, 66667, 2, 4, 98304 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 160000, 1, 5, 160000 },
|
||||
{ 0, 400000, ACPU_PLL_2, 2, 2, 133333, 2, 5, 160000 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 160000, 2, 6, 160000 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 200000, 2, 7, 200000 },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 7627 with GSM capable modem - PLL2 @ 800 */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_800_pll4_0[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, 0, 30720 },
|
||||
{ 0, 120000, ACPU_PLL_0, 4, 7, 60000, 1, 3, 61440 },
|
||||
{ 1, 122880, ACPU_PLL_1, 1, 1, 61440, 1, 3, 61440 },
|
||||
{ 0, 200000, ACPU_PLL_2, 2, 3, 66667, 2, 4, 61440 },
|
||||
{ 1, 245760, ACPU_PLL_1, 1, 0, 122880, 1, 4, 61440 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 160000, 1, 5, 160000 },
|
||||
{ 0, 400000, ACPU_PLL_2, 2, 1, 133333, 2, 5, 160000 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 160000, 2, 6, 160000 },
|
||||
{ 1, 800000, ACPU_PLL_2, 2, 0, 200000, 3, 7, 200000 },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 7627 with CDMA capable modem - PLL2 @ 800 */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_196_pll2_800_pll4_0[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, 0, 24576 },
|
||||
{ 1, 98304, ACPU_PLL_1, 1, 1, 98304, 0, 3, 49152 },
|
||||
{ 0, 120000, ACPU_PLL_0, 4, 7, 60000, 1, 3, 49152 },
|
||||
{ 1, 196608, ACPU_PLL_1, 1, 0, 65536, 2, 4, 98304 },
|
||||
{ 0, 200000, ACPU_PLL_2, 2, 3, 66667, 2, 4, 98304 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 160000, 1, 5, 160000 },
|
||||
{ 0, 400000, ACPU_PLL_2, 2, 1, 133333, 2, 5, 160000 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 160000, 2, 6, 160000 },
|
||||
{ 1, 800000, ACPU_PLL_2, 2, 0, 200000, 3, 7, 200000 },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 7627a PLL2 @ 1200MHz with GSM capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_pll4_800[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
|
||||
{ 0, 61440, ACPU_PLL_1, 1, 3, 7680, 3, 1, 61440 },
|
||||
{ 1, 122880, ACPU_PLL_1, 1, 1, 15360, 3, 2, 61440 },
|
||||
{ 1, 245760, ACPU_PLL_1, 1, 0, 30720, 3, 3, 61440 },
|
||||
{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 122880 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
|
||||
{ 0, 400000, ACPU_PLL_4, 6, 1, 50000, 3, 4, 122880 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
|
||||
{ 1, 800000, ACPU_PLL_4, 6, 0, 100000, 3, 7, 200000 },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 7627a PLL2 @ 1200MHz with CDMA capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_196_pll2_1200_pll4_800[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 24576 },
|
||||
{ 0, 65536, ACPU_PLL_1, 1, 3, 8192, 3, 1, 49152 },
|
||||
{ 1, 98304, ACPU_PLL_1, 1, 1, 12288, 3, 2, 49152 },
|
||||
{ 1, 196608, ACPU_PLL_1, 1, 0, 24576, 3, 3, 98304 },
|
||||
{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 120000 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 120000 },
|
||||
{ 0, 400000, ACPU_PLL_4, 6, 1, 50000, 3, 4, 120000 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 120000 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
|
||||
{ 1, 800000, ACPU_PLL_4, 6, 0, 100000, 3, 7, 200000 },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 7627aa PLL4 @ 1008MHz with GSM capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_pll4_1008[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
|
||||
{ 0, 61440, ACPU_PLL_1, 1, 3, 7680, 3, 1, 61440 },
|
||||
{ 1, 122880, ACPU_PLL_1, 1, 1, 15360, 3, 2, 61440 },
|
||||
{ 1, 245760, ACPU_PLL_1, 1, 0, 30720, 3, 3, 61440 },
|
||||
{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 122880 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
|
||||
{ 0, 504000, ACPU_PLL_4, 6, 1, 63000, 3, 6, 160000 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
|
||||
{ 1, 1008000, ACPU_PLL_4, 6, 0, 126000, 3, 7, 200000},
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 7627aa PLL4 @ 1008MHz with CDMA capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_196_pll2_1200_pll4_1008[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 24576 },
|
||||
{ 0, 65536, ACPU_PLL_1, 1, 3, 8192, 3, 1, 49152 },
|
||||
{ 1, 98304, ACPU_PLL_1, 1, 1, 12288, 3, 2, 49152 },
|
||||
{ 1, 196608, ACPU_PLL_1, 1, 0, 24576, 3, 3, 98304 },
|
||||
{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 122880 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
|
||||
{ 0, 504000, ACPU_PLL_4, 6, 1, 63000, 3, 6, 160000 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
|
||||
{ 1, 1008000, ACPU_PLL_4, 6, 0, 126000, 3, 7, 200000},
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 8625 PLL4 @ 1209MHz with GSM capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_pll4_1209[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
|
||||
{ 0, 61440, ACPU_PLL_1, 1, 3, 7680, 3, 1, 61440 },
|
||||
{ 1, 122880, ACPU_PLL_1, 1, 1, 15360, 3, 2, 61440 },
|
||||
{ 1, 245760, ACPU_PLL_1, 1, 0, 30720, 3, 3, 61440 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
|
||||
{ 0, 604800, ACPU_PLL_4, 6, 1, 75600, 3, 6, 160000 },
|
||||
{ 1, 1209600, ACPU_PLL_4, 6, 0, 151200, 3, 7, 200000},
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 8625 PLL4 @ 1209MHz with CDMA capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_196_pll2_1200_pll4_1209[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 24576 },
|
||||
{ 0, 65536, ACPU_PLL_1, 1, 3, 8192, 3, 1, 49152 },
|
||||
{ 1, 98304, ACPU_PLL_1, 1, 1, 12288, 3, 2, 49152 },
|
||||
{ 1, 196608, ACPU_PLL_1, 1, 0, 24576, 3, 3, 98304 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
|
||||
{ 0, 604800, ACPU_PLL_4, 6, 1, 75600, 3, 6, 160000 },
|
||||
{ 1, 1209600, ACPU_PLL_4, 6, 0, 151200, 3, 7, 200000},
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 8625 PLL4 @ 1152MHz with GSM capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_pll4_1152[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
|
||||
{ 0, 61440, ACPU_PLL_1, 1, 3, 7680, 3, 1, 61440 },
|
||||
{ 1, 122880, ACPU_PLL_1, 1, 1, 15360, 3, 2, 61440 },
|
||||
{ 1, 245760, ACPU_PLL_1, 1, 0, 30720, 3, 3, 61440 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
|
||||
{ 0, 576000, ACPU_PLL_4, 6, 1, 72000, 3, 6, 160000 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
|
||||
{ 1, 1152000, ACPU_PLL_4, 6, 0, 144000, 3, 7, 200000},
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 8625 PLL4 @ 1115MHz with CDMA capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_196_pll2_1200_pll4_1152[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 24576 },
|
||||
{ 0, 65536, ACPU_PLL_1, 1, 3, 8192, 3, 1, 49152 },
|
||||
{ 1, 98304, ACPU_PLL_1, 1, 1, 12288, 3, 2, 49152 },
|
||||
{ 1, 196608, ACPU_PLL_1, 1, 0, 24576, 3, 3, 98304 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
|
||||
{ 0, 576000, ACPU_PLL_4, 6, 1, 72000, 3, 6, 160000 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
|
||||
{ 1, 1152000, ACPU_PLL_4, 6, 0, 144000, 3, 7, 200000},
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
|
||||
/* 7625a PLL2 @ 1200MHz with GSM capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_25a[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
|
||||
{ 0, 61440, ACPU_PLL_1, 1, 3, 7680, 3, 1, 61440 },
|
||||
{ 1, 122880, ACPU_PLL_1, 1, 1, 15360, 3, 2, 61440 },
|
||||
{ 1, 245760, ACPU_PLL_1, 1, 0, 30720, 3, 3, 61440 },
|
||||
{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 122880 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
|
||||
{ 0, 400000, ACPU_PLL_2, 2, 2, 50000, 3, 4, 122880 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 200000 },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 7627a PLL2 @ 1200MHz with GSM capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_737_pll2_1200_pll4_800[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
|
||||
{ 0, 61440, ACPU_PLL_1, 1, 11, 7680, 3, 1, 61440 },
|
||||
{ 1, 122880, ACPU_PLL_1, 1, 5, 15360, 3, 2, 61440 },
|
||||
{ 1, 245760, ACPU_PLL_1, 1, 2, 30720, 3, 3, 61440 },
|
||||
{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 122880 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
|
||||
{ 0, 400000, ACPU_PLL_4, 6, 1, 50000, 3, 4, 122880 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
|
||||
{ 1, 800000, ACPU_PLL_4, 6, 0, 100000, 3, 7, 200000 },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 7627a PLL2 @ 1200MHz with CDMA capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_589_pll2_1200_pll4_800[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 24576 },
|
||||
{ 0, 65536, ACPU_PLL_1, 1, 8, 8192, 3, 1, 49152 },
|
||||
{ 1, 98304, ACPU_PLL_1, 1, 5, 12288, 3, 2, 49152 },
|
||||
{ 1, 196608, ACPU_PLL_1, 1, 2, 24576, 3, 3, 98304 },
|
||||
{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 120000 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 120000 },
|
||||
{ 0, 400000, ACPU_PLL_4, 6, 1, 50000, 3, 4, 120000 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 120000 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
|
||||
{ 1, 800000, ACPU_PLL_4, 6, 0, 100000, 3, 7, 200000 },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 7627aa PLL4 @ 1008MHz with GSM capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_737_pll2_1200_pll4_1008[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
|
||||
{ 0, 61440, ACPU_PLL_1, 1, 11, 7680, 3, 1, 61440 },
|
||||
{ 1, 122880, ACPU_PLL_1, 1, 5, 15360, 3, 2, 61440 },
|
||||
{ 1, 245760, ACPU_PLL_1, 1, 2, 30720, 3, 3, 61440 },
|
||||
{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 122880 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
|
||||
{ 0, 504000, ACPU_PLL_4, 6, 1, 63000, 3, 6, 160000 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
|
||||
{ 1, 1008000, ACPU_PLL_4, 6, 0, 126000, 3, 7, 200000},
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 7627aa PLL4 @ 1008MHz with CDMA capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_589_pll2_1200_pll4_1008[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 24576 },
|
||||
{ 0, 65536, ACPU_PLL_1, 1, 8, 8192, 3, 1, 49152 },
|
||||
{ 1, 98304, ACPU_PLL_1, 1, 5, 12288, 3, 2, 49152 },
|
||||
{ 1, 196608, ACPU_PLL_1, 1, 2, 24576, 3, 3, 98304 },
|
||||
{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 122880 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
|
||||
{ 0, 504000, ACPU_PLL_4, 6, 1, 63000, 3, 6, 160000 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
|
||||
{ 1, 1008000, ACPU_PLL_4, 6, 0, 126000, 3, 7, 200000},
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
/* 7625a PLL2 @ 1200MHz with GSM capable modem */
|
||||
static struct clkctl_acpu_speed pll0_960_pll1_737_pll2_1200_25a[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
|
||||
{ 0, 61440, ACPU_PLL_1, 1, 11, 7680, 3, 1, 61440 },
|
||||
{ 1, 122880, ACPU_PLL_1, 1, 5, 15360, 3, 2, 61440 },
|
||||
{ 1, 245760, ACPU_PLL_1, 1, 2, 30720, 3, 3, 61440 },
|
||||
{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 122880 },
|
||||
{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
|
||||
{ 0, 400000, ACPU_PLL_2, 2, 2, 50000, 3, 4, 122880 },
|
||||
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
|
||||
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 200000 },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
|
||||
};
|
||||
|
||||
#define PLL_CONFIG(m0, m1, m2, m4) { \
|
||||
m0, m1, m2, m4, \
|
||||
pll0_##m0##_pll1_##m1##_pll2_##m2##_pll4_##m4 \
|
||||
}
|
||||
|
||||
struct pll_freq_tbl_map {
|
||||
unsigned int pll0_rate;
|
||||
unsigned int pll1_rate;
|
||||
unsigned int pll2_rate;
|
||||
unsigned int pll4_rate;
|
||||
struct clkctl_acpu_speed *tbl;
|
||||
};
|
||||
|
||||
static struct pll_freq_tbl_map acpu_freq_tbl_list[] = {
|
||||
PLL_CONFIG(960, 196, 1200, 0),
|
||||
PLL_CONFIG(960, 245, 1200, 0),
|
||||
PLL_CONFIG(960, 196, 800, 0),
|
||||
PLL_CONFIG(960, 245, 800, 0),
|
||||
PLL_CONFIG(960, 245, 1200, 800),
|
||||
PLL_CONFIG(960, 196, 1200, 800),
|
||||
PLL_CONFIG(960, 245, 1200, 1008),
|
||||
PLL_CONFIG(960, 196, 1200, 1008),
|
||||
PLL_CONFIG(960, 737, 1200, 800),
|
||||
PLL_CONFIG(960, 589, 1200, 800),
|
||||
PLL_CONFIG(960, 737, 1200, 1008),
|
||||
PLL_CONFIG(960, 589, 1200, 1008),
|
||||
PLL_CONFIG(960, 245, 1200, 1209),
|
||||
PLL_CONFIG(960, 196, 1200, 1209),
|
||||
PLL_CONFIG(960, 245, 1200, 1152),
|
||||
PLL_CONFIG(960, 196, 1200, 1152),
|
||||
{ 0, 0, 0, 0, 0 }
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ_MSM
|
||||
static struct cpufreq_frequency_table freq_table[NR_CPUS][20];
|
||||
|
||||
static void __init cpufreq_table_init(void)
|
||||
{
|
||||
int cpu;
|
||||
for_each_possible_cpu(cpu) {
|
||||
unsigned int i, freq_cnt = 0;
|
||||
|
||||
/* Construct the freq_table table from acpu_freq_tbl since
|
||||
* the freq_table values need to match frequencies specified
|
||||
* in acpu_freq_tbl and acpu_freq_tbl needs to be fixed up
|
||||
* during init.
|
||||
*/
|
||||
for (i = 0; acpu_freq_tbl[i].a11clk_khz != 0
|
||||
&& freq_cnt < ARRAY_SIZE(*freq_table)-1; i++) {
|
||||
if (acpu_freq_tbl[i].use_for_scaling) {
|
||||
freq_table[cpu][freq_cnt].index = freq_cnt;
|
||||
freq_table[cpu][freq_cnt].frequency
|
||||
= acpu_freq_tbl[i].a11clk_khz;
|
||||
freq_cnt++;
|
||||
}
|
||||
}
|
||||
|
||||
/* freq_table not big enough to store all usable freqs. */
|
||||
BUG_ON(acpu_freq_tbl[i].a11clk_khz != 0);
|
||||
|
||||
freq_table[cpu][freq_cnt].index = freq_cnt;
|
||||
freq_table[cpu][freq_cnt].frequency = CPUFREQ_TABLE_END;
|
||||
/* Register table with CPUFreq. */
|
||||
cpufreq_frequency_table_get_attr(freq_table[cpu], cpu);
|
||||
pr_info("CPU%d: %d scaling frequencies supported.\n",
|
||||
cpu, freq_cnt);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static int acpuclk_set_vdd_level(int vdd)
|
||||
{
|
||||
uint32_t current_vdd;
|
||||
|
||||
/*
|
||||
* NOTE: v1.0 of 7x27a/7x25a chip doesn't have working
|
||||
* VDD switching support.
|
||||
*/
|
||||
if ((cpu_is_msm7x27a() || cpu_is_msm7x25a()) &&
|
||||
(SOCINFO_VERSION_MINOR(socinfo_get_version()) < 1))
|
||||
return 0;
|
||||
|
||||
current_vdd = readl_relaxed(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07;
|
||||
|
||||
pr_debug("Switching VDD from %u mV -> %d mV\n",
|
||||
current_vdd, vdd);
|
||||
|
||||
writel_relaxed((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR);
|
||||
mb();
|
||||
udelay(62);
|
||||
if ((readl_relaxed(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) {
|
||||
pr_err("VDD set failed\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
pr_debug("VDD switched\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Set proper dividers for the given clock speed. */
|
||||
static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s)
|
||||
{
|
||||
uint32_t reg_clkctl, reg_clksel, clk_div, src_sel;
|
||||
|
||||
reg_clksel = readl_relaxed(A11S_CLK_SEL_ADDR);
|
||||
|
||||
/* AHB_CLK_DIV */
|
||||
clk_div = (reg_clksel >> 1) & 0x03;
|
||||
/* CLK_SEL_SRC1NO */
|
||||
src_sel = reg_clksel & 1;
|
||||
|
||||
/*
|
||||
* If the new clock divider is higher than the previous, then
|
||||
* program the divider before switching the clock
|
||||
*/
|
||||
if (hunt_s->ahbclk_div > clk_div) {
|
||||
reg_clksel &= ~(0x3 << 1);
|
||||
reg_clksel |= (hunt_s->ahbclk_div << 1);
|
||||
writel_relaxed(reg_clksel, A11S_CLK_SEL_ADDR);
|
||||
}
|
||||
|
||||
/* Program clock source and divider */
|
||||
reg_clkctl = readl_relaxed(A11S_CLK_CNTL_ADDR);
|
||||
reg_clkctl &= ~(0xFF << (8 * src_sel));
|
||||
reg_clkctl |= hunt_s->a11clk_src_sel << (4 + 8 * src_sel);
|
||||
reg_clkctl |= hunt_s->a11clk_src_div << (0 + 8 * src_sel);
|
||||
writel_relaxed(reg_clkctl, A11S_CLK_CNTL_ADDR);
|
||||
|
||||
/* Program clock source selection */
|
||||
reg_clksel ^= 1;
|
||||
writel_relaxed(reg_clksel, A11S_CLK_SEL_ADDR);
|
||||
|
||||
/* Wait for the clock switch to complete */
|
||||
mb();
|
||||
udelay(50);
|
||||
|
||||
/*
|
||||
* If the new clock divider is lower than the previous, then
|
||||
* program the divider after switching the clock
|
||||
*/
|
||||
if (hunt_s->ahbclk_div < clk_div) {
|
||||
reg_clksel &= ~(0x3 << 1);
|
||||
reg_clksel |= (hunt_s->ahbclk_div << 1);
|
||||
writel_relaxed(reg_clksel, A11S_CLK_SEL_ADDR);
|
||||
}
|
||||
}
|
||||
|
||||
static int acpuclk_7627_set_rate(int cpu, unsigned long rate,
|
||||
enum setrate_reason reason)
|
||||
{
|
||||
uint32_t reg_clkctl;
|
||||
struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s;
|
||||
int res, rc = 0;
|
||||
unsigned int plls_enabled = 0, pll;
|
||||
|
||||
if (reason == SETRATE_CPUFREQ)
|
||||
mutex_lock(&drv_state.lock);
|
||||
|
||||
strt_s = cur_s = drv_state.current_speed;
|
||||
|
||||
WARN_ONCE(cur_s == NULL, "%s: not initialized\n", __func__);
|
||||
if (cur_s == NULL) {
|
||||
rc = -ENOENT;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (rate == cur_s->a11clk_khz)
|
||||
goto out;
|
||||
|
||||
for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) {
|
||||
if (tgt_s->a11clk_khz == rate)
|
||||
break;
|
||||
}
|
||||
|
||||
if (tgt_s->a11clk_khz == 0) {
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Choose the highest speed at or below 'rate' with same PLL. */
|
||||
if (reason != SETRATE_CPUFREQ
|
||||
&& tgt_s->a11clk_khz < cur_s->a11clk_khz) {
|
||||
while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll)
|
||||
tgt_s--;
|
||||
}
|
||||
|
||||
if (strt_s->pll != ACPU_PLL_TCXO)
|
||||
plls_enabled |= 1 << strt_s->pll;
|
||||
|
||||
if (reason == SETRATE_CPUFREQ) {
|
||||
if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) {
|
||||
rc = clk_enable(pll_clk[tgt_s->pll].clk);
|
||||
if (rc < 0) {
|
||||
pr_err("PLL%d enable failed (%d)\n",
|
||||
tgt_s->pll, rc);
|
||||
goto out;
|
||||
}
|
||||
plls_enabled |= 1 << tgt_s->pll;
|
||||
}
|
||||
}
|
||||
/* Need to do this when coming out of power collapse since some modem
|
||||
* firmwares reset the VDD when the application processor enters power
|
||||
* collapse. */
|
||||
if (reason == SETRATE_CPUFREQ || reason == SETRATE_PC) {
|
||||
/* Increase VDD if needed. */
|
||||
if (tgt_s->vdd > cur_s->vdd) {
|
||||
rc = acpuclk_set_vdd_level(tgt_s->vdd);
|
||||
if (rc < 0) {
|
||||
pr_err("Unable to switch ACPU vdd (%d)\n", rc);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Set wait states for CPU inbetween frequency changes */
|
||||
reg_clkctl = readl_relaxed(A11S_CLK_CNTL_ADDR);
|
||||
reg_clkctl |= (100 << 16); /* set WT_ST_CNT */
|
||||
writel_relaxed(reg_clkctl, A11S_CLK_CNTL_ADDR);
|
||||
|
||||
pr_debug("Switching from ACPU rate %u KHz -> %u KHz\n",
|
||||
strt_s->a11clk_khz, tgt_s->a11clk_khz);
|
||||
|
||||
while (cur_s != tgt_s) {
|
||||
/*
|
||||
* Always jump to target freq if within max_speed_delta_khz,
|
||||
* regardless of PLL. If differnece is greater, use the
|
||||
* predefined steppings in the table.
|
||||
*/
|
||||
int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz));
|
||||
if (d > drv_state.max_speed_delta_khz) {
|
||||
|
||||
if (tgt_s->a11clk_khz > cur_s->a11clk_khz) {
|
||||
/* Step up: jump to target PLL as early as
|
||||
* possible so indexing using TCXO (up[-1])
|
||||
* never occurs. */
|
||||
if (likely(cur_s->up[tgt_s->pll]))
|
||||
cur_s = cur_s->up[tgt_s->pll];
|
||||
else
|
||||
cur_s = cur_s->up[cur_s->pll];
|
||||
} else {
|
||||
/* Step down: stay on current PLL as long as
|
||||
* possible so indexing using TCXO (down[-1])
|
||||
* never occurs. */
|
||||
if (likely(cur_s->down[cur_s->pll]))
|
||||
cur_s = cur_s->down[cur_s->pll];
|
||||
else
|
||||
cur_s = cur_s->down[tgt_s->pll];
|
||||
}
|
||||
|
||||
if (cur_s == NULL) { /* This should not happen. */
|
||||
pr_err("No stepping frequencies found. "
|
||||
"strt_s:%u tgt_s:%u\n",
|
||||
strt_s->a11clk_khz, tgt_s->a11clk_khz);
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
} else {
|
||||
cur_s = tgt_s;
|
||||
}
|
||||
|
||||
pr_debug("STEP khz = %u, pll = %d\n",
|
||||
cur_s->a11clk_khz, cur_s->pll);
|
||||
|
||||
if (cur_s->pll != ACPU_PLL_TCXO
|
||||
&& !(plls_enabled & (1 << cur_s->pll))) {
|
||||
rc = clk_enable(pll_clk[cur_s->pll].clk);
|
||||
if (rc < 0) {
|
||||
pr_err("PLL%d enable failed (%d)\n",
|
||||
cur_s->pll, rc);
|
||||
goto out;
|
||||
}
|
||||
plls_enabled |= 1 << cur_s->pll;
|
||||
}
|
||||
|
||||
acpuclk_set_div(cur_s);
|
||||
drv_state.current_speed = cur_s;
|
||||
/* Re-adjust lpj for the new clock speed. */
|
||||
#ifdef CONFIG_SMP
|
||||
for_each_possible_cpu(cpu) {
|
||||
per_cpu(cpu_data, cpu).loops_per_jiffy =
|
||||
cur_s->lpj;
|
||||
}
|
||||
#endif
|
||||
/* Adjust the global one */
|
||||
loops_per_jiffy = cur_s->lpj;
|
||||
|
||||
}
|
||||
|
||||
/* Nothing else to do for SWFI. */
|
||||
if (reason == SETRATE_SWFI)
|
||||
goto out;
|
||||
|
||||
/* Change the AXI bus frequency if we can. */
|
||||
if (strt_s->axiclk_khz != tgt_s->axiclk_khz) {
|
||||
res = clk_set_rate(drv_state.ebi1_clk,
|
||||
tgt_s->axiclk_khz * 1000);
|
||||
if (res < 0)
|
||||
pr_warning("Setting AXI min rate failed (%d)\n", res);
|
||||
}
|
||||
|
||||
/* Disable PLLs we are not using anymore. */
|
||||
if (tgt_s->pll != ACPU_PLL_TCXO)
|
||||
plls_enabled &= ~(1 << tgt_s->pll);
|
||||
for (pll = ACPU_PLL_0; pll < ACPU_PLL_END; pll++)
|
||||
if (plls_enabled & (1 << pll))
|
||||
clk_disable(pll_clk[pll].clk);
|
||||
|
||||
/* Nothing else to do for power collapse. */
|
||||
if (reason == SETRATE_PC)
|
||||
goto out;
|
||||
|
||||
/* Drop VDD level if we can. */
|
||||
if (tgt_s->vdd < strt_s->vdd) {
|
||||
res = acpuclk_set_vdd_level(tgt_s->vdd);
|
||||
if (res < 0)
|
||||
pr_warning("Unable to drop ACPU vdd (%d)\n", res);
|
||||
}
|
||||
|
||||
pr_debug("ACPU speed change complete\n");
|
||||
out:
|
||||
if (reason == SETRATE_CPUFREQ)
|
||||
mutex_unlock(&drv_state.lock);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void __init acpuclk_hw_init(void)
|
||||
{
|
||||
struct clkctl_acpu_speed *speed;
|
||||
uint32_t div, sel, reg_clksel;
|
||||
int res;
|
||||
|
||||
/*
|
||||
* Prepare all the PLLs because we enable/disable them
|
||||
* from atomic context and can't always ensure they're
|
||||
* all prepared in non-atomic context. Same goes for
|
||||
* ebi1_acpu_clk.
|
||||
*/
|
||||
BUG_ON(clk_prepare(pll_clk[ACPU_PLL_0].clk));
|
||||
BUG_ON(clk_prepare(pll_clk[ACPU_PLL_1].clk));
|
||||
BUG_ON(clk_prepare(pll_clk[ACPU_PLL_2].clk));
|
||||
BUG_ON(clk_prepare(pll_clk[ACPU_PLL_4].clk));
|
||||
BUG_ON(clk_prepare(drv_state.ebi1_clk));
|
||||
|
||||
/*
|
||||
* Determine the rate of ACPU clock
|
||||
*/
|
||||
|
||||
if (!(readl_relaxed(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */
|
||||
/* CLK_SRC0_SEL */
|
||||
sel = (readl_relaxed(A11S_CLK_CNTL_ADDR) >> 12) & 0x7;
|
||||
/* CLK_SRC0_DIV */
|
||||
div = (readl_relaxed(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f;
|
||||
} else {
|
||||
/* CLK_SRC1_SEL */
|
||||
sel = (readl_relaxed(A11S_CLK_CNTL_ADDR) >> 4) & 0x07;
|
||||
/* CLK_SRC1_DIV */
|
||||
div = readl_relaxed(A11S_CLK_CNTL_ADDR) & 0x0f;
|
||||
}
|
||||
|
||||
for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) {
|
||||
if (speed->a11clk_src_sel == sel
|
||||
&& (speed->a11clk_src_div == div))
|
||||
break;
|
||||
}
|
||||
if (speed->a11clk_khz == 0) {
|
||||
pr_err("Error - ACPU clock reports invalid speed\n");
|
||||
return;
|
||||
}
|
||||
|
||||
drv_state.current_speed = speed;
|
||||
if (speed->pll != ACPU_PLL_TCXO) {
|
||||
if (clk_enable(pll_clk[speed->pll].clk))
|
||||
pr_warning("Failed to vote for boot PLL\n");
|
||||
}
|
||||
|
||||
/* Fix div2 to 2 for 7x27/5a(aa) targets */
|
||||
if (!cpu_is_msm7x27()) {
|
||||
reg_clksel = readl_relaxed(A11S_CLK_SEL_ADDR);
|
||||
reg_clksel &= ~(0x3 << 14);
|
||||
reg_clksel |= (0x1 << 14);
|
||||
writel_relaxed(reg_clksel, A11S_CLK_SEL_ADDR);
|
||||
}
|
||||
|
||||
res = clk_set_rate(drv_state.ebi1_clk, speed->axiclk_khz * 1000);
|
||||
if (res < 0)
|
||||
pr_warning("Setting AXI min rate failed (%d)\n", res);
|
||||
res = clk_enable(drv_state.ebi1_clk);
|
||||
if (res < 0)
|
||||
pr_warning("Enabling AXI clock failed (%d)\n", res);
|
||||
|
||||
pr_info("ACPU running at %d KHz\n", speed->a11clk_khz);
|
||||
}
|
||||
|
||||
static unsigned long acpuclk_7627_get_rate(int cpu)
|
||||
{
|
||||
WARN_ONCE(drv_state.current_speed == NULL,
|
||||
"%s: not initialized\n", __func__);
|
||||
if (drv_state.current_speed)
|
||||
return drv_state.current_speed->a11clk_khz;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Clock driver initialization
|
||||
*---------------------------------------------------------------------------*/
|
||||
#define MHZ 1000000
|
||||
static void __init select_freq_plan(void)
|
||||
{
|
||||
unsigned long pll_mhz[ACPU_PLL_END];
|
||||
struct pll_freq_tbl_map *t;
|
||||
int i;
|
||||
|
||||
/* Get PLL clocks */
|
||||
for (i = 0; i < ACPU_PLL_END; i++) {
|
||||
if (pll_clk[i].name) {
|
||||
pll_clk[i].clk = clk_get_sys("acpu", pll_clk[i].name);
|
||||
if (IS_ERR(pll_clk[i].clk)) {
|
||||
pll_mhz[i] = 0;
|
||||
continue;
|
||||
}
|
||||
/* Get PLL's Rate */
|
||||
pll_mhz[i] = clk_get_rate(pll_clk[i].clk)/MHZ;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* For the pll configuration used in acpuclock table e.g.
|
||||
* pll0_960_pll1_245_pll2_1200" is same for 7627 and
|
||||
* 7625a (as pll0,pll1,pll2) having same rates, but frequency
|
||||
* table is different for both targets.
|
||||
*
|
||||
* Hence below for loop will not be able to select correct
|
||||
* table based on PLL rates as rates are same. Hence we need
|
||||
* to add this cpu check for selecting the correct acpuclock table.
|
||||
*/
|
||||
if (cpu_is_msm7x25a()) {
|
||||
if (pll_mhz[ACPU_PLL_1] == 245) {
|
||||
acpu_freq_tbl =
|
||||
pll0_960_pll1_245_pll2_1200_25a;
|
||||
} else if (pll_mhz[ACPU_PLL_1] == 737) {
|
||||
acpu_freq_tbl =
|
||||
pll0_960_pll1_737_pll2_1200_25a;
|
||||
}
|
||||
} else {
|
||||
/* Select the right table to use. */
|
||||
for (t = acpu_freq_tbl_list; t->tbl != 0; t++) {
|
||||
if (t->pll0_rate == pll_mhz[ACPU_PLL_0]
|
||||
&& t->pll1_rate == pll_mhz[ACPU_PLL_1]
|
||||
&& t->pll2_rate == pll_mhz[ACPU_PLL_2]
|
||||
&& t->pll4_rate == pll_mhz[ACPU_PLL_4]) {
|
||||
acpu_freq_tbl = t->tbl;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (acpu_freq_tbl == NULL) {
|
||||
pr_crit("Unknown PLL configuration!\n");
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Hardware requires the CPU to be dropped to less than MAX_WAIT_FOR_IRQ_KHZ
|
||||
* before entering a wait for irq low-power mode. Find a suitable rate.
|
||||
*/
|
||||
static unsigned long __init find_wait_for_irq_khz(void)
|
||||
{
|
||||
unsigned long found_khz = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; acpu_freq_tbl[i].a11clk_khz &&
|
||||
acpu_freq_tbl[i].a11clk_khz <= MAX_WAIT_FOR_IRQ_KHZ; i++)
|
||||
found_khz = acpu_freq_tbl[i].a11clk_khz;
|
||||
|
||||
return found_khz;
|
||||
}
|
||||
|
||||
static void __init lpj_init(void)
|
||||
{
|
||||
int i = 0, cpu;
|
||||
const struct clkctl_acpu_speed *base_clk = drv_state.current_speed;
|
||||
unsigned long loops;
|
||||
|
||||
for_each_possible_cpu(cpu) {
|
||||
#ifdef CONFIG_SMP
|
||||
loops = per_cpu(cpu_data, cpu).loops_per_jiffy;
|
||||
#else
|
||||
loops = loops_per_jiffy;
|
||||
#endif
|
||||
for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) {
|
||||
acpu_freq_tbl[i].lpj = cpufreq_scale(
|
||||
loops,
|
||||
base_clk->a11clk_khz,
|
||||
acpu_freq_tbl[i].a11clk_khz);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void __init precompute_stepping(void)
|
||||
{
|
||||
int i, step_idx;
|
||||
|
||||
#define cur_freq acpu_freq_tbl[i].a11clk_khz
|
||||
#define step_freq acpu_freq_tbl[step_idx].a11clk_khz
|
||||
#define cur_pll acpu_freq_tbl[i].pll
|
||||
#define step_pll acpu_freq_tbl[step_idx].pll
|
||||
|
||||
for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) {
|
||||
|
||||
/* Calculate max "up" step for each destination PLL */
|
||||
step_idx = i + 1;
|
||||
while (step_freq && (step_freq - cur_freq)
|
||||
<= drv_state.max_speed_delta_khz) {
|
||||
acpu_freq_tbl[i].up[step_pll] =
|
||||
&acpu_freq_tbl[step_idx];
|
||||
step_idx++;
|
||||
}
|
||||
if (step_idx == (i + 1) && step_freq) {
|
||||
pr_crit("Delta between freqs %u KHz and %u KHz is"
|
||||
" too high!\n", cur_freq, step_freq);
|
||||
BUG();
|
||||
}
|
||||
|
||||
/* Calculate max "down" step for each destination PLL */
|
||||
step_idx = i - 1;
|
||||
while (step_idx >= 0 && (cur_freq - step_freq)
|
||||
<= drv_state.max_speed_delta_khz) {
|
||||
acpu_freq_tbl[i].down[step_pll] =
|
||||
&acpu_freq_tbl[step_idx];
|
||||
step_idx--;
|
||||
}
|
||||
if (step_idx == (i - 1) && i > 0) {
|
||||
pr_crit("Delta between freqs %u KHz and %u KHz is"
|
||||
" too high!\n", cur_freq, step_freq);
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void __init print_acpu_freq_tbl(void)
|
||||
{
|
||||
struct clkctl_acpu_speed *t;
|
||||
short down_idx[ACPU_PLL_END];
|
||||
short up_idx[ACPU_PLL_END];
|
||||
int i, j;
|
||||
|
||||
#define FREQ_IDX(freq_ptr) (freq_ptr - acpu_freq_tbl)
|
||||
pr_info("Id CPU-KHz PLL DIV AHB-KHz ADIV AXI-KHz "
|
||||
"D0 D1 D2 D4 U0 U1 U2 U4\n");
|
||||
|
||||
t = &acpu_freq_tbl[0];
|
||||
for (i = 0; t->a11clk_khz != 0; i++) {
|
||||
|
||||
for (j = 0; j < ACPU_PLL_END; j++) {
|
||||
down_idx[j] = t->down[j] ? FREQ_IDX(t->down[j]) : -1;
|
||||
up_idx[j] = t->up[j] ? FREQ_IDX(t->up[j]) : -1;
|
||||
}
|
||||
|
||||
pr_info("%2d %7d %3d %3d %7d %4d %7d "
|
||||
"%2d %2d %2d %2d %2d %2d %2d %2d\n",
|
||||
i, t->a11clk_khz, t->pll, t->a11clk_src_div + 1,
|
||||
t->ahbclk_khz, t->ahbclk_div + 1, t->axiclk_khz,
|
||||
down_idx[0], down_idx[1], down_idx[2], down_idx[4],
|
||||
up_idx[0], up_idx[1], up_idx[2], up_idx[4]);
|
||||
|
||||
t++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static struct acpuclk_data acpuclk_7627_data = {
|
||||
.set_rate = acpuclk_7627_set_rate,
|
||||
.get_rate = acpuclk_7627_get_rate,
|
||||
.power_collapse_khz = POWER_COLLAPSE_KHZ,
|
||||
.switch_time_us = 50,
|
||||
};
|
||||
|
||||
static int __init acpuclk_7627_init(struct acpuclk_soc_data *soc_data)
|
||||
{
|
||||
pr_info("%s()\n", __func__);
|
||||
|
||||
drv_state.ebi1_clk = clk_get(NULL, "ebi1_acpu_clk");
|
||||
BUG_ON(IS_ERR(drv_state.ebi1_clk));
|
||||
|
||||
mutex_init(&drv_state.lock);
|
||||
drv_state.max_speed_delta_khz = soc_data->max_speed_delta_khz;
|
||||
select_freq_plan();
|
||||
acpuclk_7627_data.wait_for_irq_khz = find_wait_for_irq_khz();
|
||||
precompute_stepping();
|
||||
acpuclk_hw_init();
|
||||
lpj_init();
|
||||
print_acpu_freq_tbl();
|
||||
acpuclk_register(&acpuclk_7627_data);
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ_MSM
|
||||
cpufreq_table_init();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct acpuclk_soc_data acpuclk_7x27_soc_data __initdata = {
|
||||
.max_speed_delta_khz = 400000,
|
||||
.init = acpuclk_7627_init,
|
||||
};
|
||||
|
||||
struct acpuclk_soc_data acpuclk_7x27a_soc_data __initdata = {
|
||||
.max_speed_delta_khz = 400000,
|
||||
.init = acpuclk_7627_init,
|
||||
};
|
||||
|
||||
struct acpuclk_soc_data acpuclk_7x27aa_soc_data __initdata = {
|
||||
.max_speed_delta_khz = 504000,
|
||||
.init = acpuclk_7627_init,
|
||||
};
|
||||
|
||||
struct acpuclk_soc_data acpuclk_8625_soc_data __initdata = {
|
||||
/* TODO: Need to update speed delta from H/w Team */
|
||||
.max_speed_delta_khz = 604800,
|
||||
.init = acpuclk_7627_init,
|
||||
};
|
||||
499
arch/arm/mach-msm/acpuclock-7x30.c
Normal file
499
arch/arm/mach-msm/acpuclock-7x30.c
Normal file
@@ -0,0 +1,499 @@
|
||||
/*
|
||||
*
|
||||
* Copyright (C) 2007 Google, Inc.
|
||||
* Copyright (c) 2007-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/version.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sort.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/msm_iomap.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include "smd_private.h"
|
||||
#include "clock.h"
|
||||
#include "acpuclock.h"
|
||||
#include "spm.h"
|
||||
|
||||
#define SCSS_CLK_CTL_ADDR (MSM_ACC0_BASE + 0x04)
|
||||
#define SCSS_CLK_SEL_ADDR (MSM_ACC0_BASE + 0x08)
|
||||
|
||||
#define PLL2_L_VAL_ADDR (MSM_CLK_CTL_BASE + 0x33C)
|
||||
#define PLL2_M_VAL_ADDR (MSM_CLK_CTL_BASE + 0x340)
|
||||
#define PLL2_N_VAL_ADDR (MSM_CLK_CTL_BASE + 0x344)
|
||||
#define PLL2_CONFIG_ADDR (MSM_CLK_CTL_BASE + 0x34C)
|
||||
|
||||
#define VREF_SEL 1 /* 0: 0.625V (50mV step), 1: 0.3125V (25mV step). */
|
||||
#define V_STEP (25 * (2 - VREF_SEL)) /* Minimum voltage step size. */
|
||||
#define VREG_DATA (VREG_CONFIG | (VREF_SEL << 5))
|
||||
#define VREG_CONFIG (BIT(7) | BIT(6)) /* Enable VREG, pull-down if disabled. */
|
||||
/* Cause a compile error if the voltage is not a multiple of the step size. */
|
||||
#define MV(mv) ((mv) / (!((mv) % V_STEP)))
|
||||
/* mv = (750mV + (raw * 25mV)) * (2 - VREF_SEL) */
|
||||
#define VDD_RAW(mv) (((MV(mv) / V_STEP) - 30) | VREG_DATA)
|
||||
|
||||
#define MAX_AXI_KHZ 192000
|
||||
|
||||
struct clock_state {
|
||||
struct clkctl_acpu_speed *current_speed;
|
||||
struct mutex lock;
|
||||
struct clk *ebi1_clk;
|
||||
};
|
||||
|
||||
struct pll {
|
||||
unsigned int l;
|
||||
unsigned int m;
|
||||
unsigned int n;
|
||||
unsigned int pre_div;
|
||||
};
|
||||
|
||||
struct clkctl_acpu_speed {
|
||||
unsigned int use_for_scaling;
|
||||
unsigned int acpu_clk_khz;
|
||||
int src;
|
||||
unsigned int acpu_src_sel;
|
||||
unsigned int acpu_src_div;
|
||||
unsigned int axi_clk_hz;
|
||||
unsigned int vdd_mv;
|
||||
unsigned int vdd_raw;
|
||||
struct pll *pll_rate;
|
||||
unsigned long lpj; /* loops_per_jiffy */
|
||||
};
|
||||
|
||||
static struct clock_state drv_state = { 0 };
|
||||
|
||||
/* Switch to this when reprogramming PLL2 */
|
||||
static struct clkctl_acpu_speed *backup_s;
|
||||
|
||||
static struct pll pll2_tbl[] = {
|
||||
{ 42, 0, 1, 0 }, /* 806 MHz */
|
||||
{ 53, 1, 3, 0 }, /* 1024 MHz */
|
||||
{ 125, 0, 1, 1 }, /* 1200 MHz */
|
||||
{ 73, 0, 1, 0 }, /* 1401 MHz */
|
||||
};
|
||||
|
||||
/* Use negative numbers for sources that can't be enabled/disabled */
|
||||
|
||||
enum acpuclk_source {
|
||||
LPXO = -2,
|
||||
AXI = -1,
|
||||
PLL_0 = 0,
|
||||
PLL_1,
|
||||
PLL_2,
|
||||
PLL_3,
|
||||
MAX_SOURCE
|
||||
};
|
||||
|
||||
static struct clk *acpuclk_sources[MAX_SOURCE];
|
||||
|
||||
/*
|
||||
* Each ACPU frequency has a certain minimum MSMC1 voltage requirement
|
||||
* that is implicitly met by voting for a specific minimum AXI frequency.
|
||||
* Do NOT change the AXI frequency unless you are _absoulutely_ sure you
|
||||
* know all the h/w requirements.
|
||||
*/
|
||||
static struct clkctl_acpu_speed acpu_freq_tbl[] = {
|
||||
{ 0, 24576, LPXO, 0, 0, 30720000, 900, VDD_RAW(900) },
|
||||
{ 0, 61440, PLL_3, 5, 11, 61440000, 900, VDD_RAW(900) },
|
||||
{ 1, 122880, PLL_3, 5, 5, 61440000, 900, VDD_RAW(900) },
|
||||
{ 0, 184320, PLL_3, 5, 4, 61440000, 900, VDD_RAW(900) },
|
||||
{ 0, MAX_AXI_KHZ, AXI, 1, 0, 61440000, 900, VDD_RAW(900) },
|
||||
{ 1, 245760, PLL_3, 5, 2, 61440000, 900, VDD_RAW(900) },
|
||||
{ 1, 368640, PLL_3, 5, 1, 122800000, 900, VDD_RAW(900) },
|
||||
/* AXI has MSMC1 implications. See above. */
|
||||
{ 1, 768000, PLL_1, 2, 0, 153600000, 1050, VDD_RAW(1050) },
|
||||
/*
|
||||
* AXI has MSMC1 implications. See above.
|
||||
*/
|
||||
{ 1, 806400, PLL_2, 3, 0, UINT_MAX, 1100, VDD_RAW(1100), &pll2_tbl[0]},
|
||||
{ 1, 1024000, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &pll2_tbl[1]},
|
||||
{ 1, 1200000, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &pll2_tbl[2]},
|
||||
{ 1, 1401600, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &pll2_tbl[3]},
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
static int acpuclk_set_acpu_vdd(struct clkctl_acpu_speed *s)
|
||||
{
|
||||
int ret = msm_spm_set_vdd(0, s->vdd_raw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Wait for voltage to stabilize. */
|
||||
udelay(62);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Assumes PLL2 is off and the acpuclock isn't sourced from PLL2 */
|
||||
static void acpuclk_config_pll2(struct pll *pll)
|
||||
{
|
||||
uint32_t config = readl_relaxed(PLL2_CONFIG_ADDR);
|
||||
|
||||
/* Make sure write to disable PLL_2 has completed
|
||||
* before reconfiguring that PLL. */
|
||||
mb();
|
||||
writel_relaxed(pll->l, PLL2_L_VAL_ADDR);
|
||||
writel_relaxed(pll->m, PLL2_M_VAL_ADDR);
|
||||
writel_relaxed(pll->n, PLL2_N_VAL_ADDR);
|
||||
if (pll->pre_div)
|
||||
config |= BIT(15);
|
||||
else
|
||||
config &= ~BIT(15);
|
||||
writel_relaxed(config, PLL2_CONFIG_ADDR);
|
||||
/* Make sure PLL is programmed before returning. */
|
||||
mb();
|
||||
}
|
||||
|
||||
/* Set clock source and divider given a clock speed */
|
||||
static void acpuclk_set_src(const struct clkctl_acpu_speed *s)
|
||||
{
|
||||
uint32_t reg_clksel, reg_clkctl, src_sel;
|
||||
|
||||
reg_clksel = readl_relaxed(SCSS_CLK_SEL_ADDR);
|
||||
|
||||
/* CLK_SEL_SRC1NO */
|
||||
src_sel = reg_clksel & 1;
|
||||
|
||||
/* Program clock source and divider. */
|
||||
reg_clkctl = readl_relaxed(SCSS_CLK_CTL_ADDR);
|
||||
reg_clkctl &= ~(0xFF << (8 * src_sel));
|
||||
reg_clkctl |= s->acpu_src_sel << (4 + 8 * src_sel);
|
||||
reg_clkctl |= s->acpu_src_div << (0 + 8 * src_sel);
|
||||
writel_relaxed(reg_clkctl, SCSS_CLK_CTL_ADDR);
|
||||
|
||||
/* Toggle clock source. */
|
||||
reg_clksel ^= 1;
|
||||
|
||||
/* Program clock source selection. */
|
||||
writel_relaxed(reg_clksel, SCSS_CLK_SEL_ADDR);
|
||||
|
||||
/* Make sure switch to new source is complete. */
|
||||
mb();
|
||||
}
|
||||
|
||||
static int acpuclk_7x30_set_rate(int cpu, unsigned long rate,
|
||||
enum setrate_reason reason)
|
||||
{
|
||||
struct clkctl_acpu_speed *tgt_s, *strt_s;
|
||||
int res, rc = 0;
|
||||
|
||||
if (reason == SETRATE_CPUFREQ)
|
||||
mutex_lock(&drv_state.lock);
|
||||
|
||||
strt_s = drv_state.current_speed;
|
||||
|
||||
if (rate == strt_s->acpu_clk_khz)
|
||||
goto out;
|
||||
|
||||
for (tgt_s = acpu_freq_tbl; tgt_s->acpu_clk_khz != 0; tgt_s++) {
|
||||
if (tgt_s->acpu_clk_khz == rate)
|
||||
break;
|
||||
}
|
||||
if (tgt_s->acpu_clk_khz == 0) {
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (reason == SETRATE_CPUFREQ) {
|
||||
/* Increase VDD if needed. */
|
||||
if (tgt_s->vdd_mv > strt_s->vdd_mv) {
|
||||
rc = acpuclk_set_acpu_vdd(tgt_s);
|
||||
if (rc < 0) {
|
||||
pr_err("ACPU VDD increase to %d mV failed "
|
||||
"(%d)\n", tgt_s->vdd_mv, rc);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pr_debug("Switching from ACPU rate %u KHz -> %u KHz\n",
|
||||
strt_s->acpu_clk_khz, tgt_s->acpu_clk_khz);
|
||||
|
||||
/* Increase the AXI bus frequency if needed. This must be done before
|
||||
* increasing the ACPU frequency, since voting for high AXI rates
|
||||
* implicitly takes care of increasing the MSMC1 voltage, as needed. */
|
||||
if (tgt_s->axi_clk_hz > strt_s->axi_clk_hz) {
|
||||
rc = clk_set_rate(drv_state.ebi1_clk, tgt_s->axi_clk_hz);
|
||||
if (rc < 0) {
|
||||
pr_err("Setting AXI min rate failed (%d)\n", rc);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
/* Move off of PLL2 if we're reprogramming it */
|
||||
if (tgt_s->src == PLL_2 && strt_s->src == PLL_2) {
|
||||
clk_enable(acpuclk_sources[backup_s->src]);
|
||||
acpuclk_set_src(backup_s);
|
||||
clk_disable(acpuclk_sources[strt_s->src]);
|
||||
}
|
||||
|
||||
/* Reconfigure PLL2 if we're moving to it */
|
||||
if (tgt_s->src == PLL_2)
|
||||
acpuclk_config_pll2(tgt_s->pll_rate);
|
||||
|
||||
/* Make sure target PLL is on. */
|
||||
if ((strt_s->src != tgt_s->src && tgt_s->src >= 0) ||
|
||||
(tgt_s->src == PLL_2 && strt_s->src == PLL_2)) {
|
||||
pr_debug("Enabling PLL %d\n", tgt_s->src);
|
||||
clk_enable(acpuclk_sources[tgt_s->src]);
|
||||
}
|
||||
|
||||
/* Perform the frequency switch */
|
||||
acpuclk_set_src(tgt_s);
|
||||
drv_state.current_speed = tgt_s;
|
||||
loops_per_jiffy = tgt_s->lpj;
|
||||
|
||||
if (tgt_s->src == PLL_2 && strt_s->src == PLL_2)
|
||||
clk_disable(acpuclk_sources[backup_s->src]);
|
||||
|
||||
/* Nothing else to do for SWFI. */
|
||||
if (reason == SETRATE_SWFI)
|
||||
goto out;
|
||||
|
||||
/* Turn off previous PLL if not used. */
|
||||
if (strt_s->src != tgt_s->src && strt_s->src >= 0) {
|
||||
pr_debug("Disabling PLL %d\n", strt_s->src);
|
||||
clk_disable(acpuclk_sources[strt_s->src]);
|
||||
}
|
||||
|
||||
/* Decrease the AXI bus frequency if we can. */
|
||||
if (tgt_s->axi_clk_hz < strt_s->axi_clk_hz) {
|
||||
res = clk_set_rate(drv_state.ebi1_clk, tgt_s->axi_clk_hz);
|
||||
if (res < 0)
|
||||
pr_warning("Setting AXI min rate failed (%d)\n", res);
|
||||
}
|
||||
|
||||
/* Nothing else to do for power collapse. */
|
||||
if (reason == SETRATE_PC)
|
||||
goto out;
|
||||
|
||||
/* Drop VDD level if we can. */
|
||||
if (tgt_s->vdd_mv < strt_s->vdd_mv) {
|
||||
res = acpuclk_set_acpu_vdd(tgt_s);
|
||||
if (res)
|
||||
pr_warning("ACPU VDD decrease to %d mV failed (%d)\n",
|
||||
tgt_s->vdd_mv, res);
|
||||
}
|
||||
|
||||
pr_debug("ACPU speed change complete\n");
|
||||
out:
|
||||
if (reason == SETRATE_CPUFREQ)
|
||||
mutex_unlock(&drv_state.lock);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static unsigned long acpuclk_7x30_get_rate(int cpu)
|
||||
{
|
||||
WARN_ONCE(drv_state.current_speed == NULL,
|
||||
"acpuclk_get_rate: not initialized\n");
|
||||
if (drv_state.current_speed)
|
||||
return drv_state.current_speed->acpu_clk_khz;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Clock driver initialization
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
static void __init acpuclk_hw_init(void)
|
||||
{
|
||||
struct clkctl_acpu_speed *s;
|
||||
uint32_t div, sel, src_num;
|
||||
uint32_t reg_clksel, reg_clkctl;
|
||||
int res;
|
||||
u8 pll2_l = readl_relaxed(PLL2_L_VAL_ADDR) & 0xFF;
|
||||
|
||||
drv_state.ebi1_clk = clk_get(NULL, "ebi1_clk");
|
||||
BUG_ON(IS_ERR(drv_state.ebi1_clk));
|
||||
|
||||
reg_clksel = readl_relaxed(SCSS_CLK_SEL_ADDR);
|
||||
|
||||
/* Determine the ACPU clock rate. */
|
||||
switch ((reg_clksel >> 1) & 0x3) {
|
||||
case 0: /* Running off the output of the raw clock source mux. */
|
||||
reg_clkctl = readl_relaxed(SCSS_CLK_CTL_ADDR);
|
||||
src_num = reg_clksel & 0x1;
|
||||
sel = (reg_clkctl >> (12 - (8 * src_num))) & 0x7;
|
||||
div = (reg_clkctl >> (8 - (8 * src_num))) & 0xF;
|
||||
|
||||
/* Check frequency table for matching sel/div pair. */
|
||||
for (s = acpu_freq_tbl; s->acpu_clk_khz != 0; s++) {
|
||||
if (s->acpu_src_sel == sel && s->acpu_src_div == div)
|
||||
break;
|
||||
}
|
||||
if (s->acpu_clk_khz == 0) {
|
||||
pr_err("Error - ACPU clock reports invalid speed\n");
|
||||
return;
|
||||
}
|
||||
break;
|
||||
case 2: /* Running off of the SCPLL selected through the core mux. */
|
||||
/* Switch to run off of the SCPLL selected through the raw
|
||||
* clock source mux. */
|
||||
for (s = acpu_freq_tbl; s->acpu_clk_khz != 0
|
||||
&& s->src != PLL_2 && s->acpu_src_div == 0; s++)
|
||||
;
|
||||
if (s->acpu_clk_khz != 0) {
|
||||
/* Program raw clock source mux. */
|
||||
acpuclk_set_src(s);
|
||||
|
||||
/* Switch to raw clock source input of the core mux. */
|
||||
reg_clksel = readl_relaxed(SCSS_CLK_SEL_ADDR);
|
||||
reg_clksel &= ~(0x3 << 1);
|
||||
writel_relaxed(reg_clksel, SCSS_CLK_SEL_ADDR);
|
||||
break;
|
||||
}
|
||||
/* else fall through */
|
||||
default:
|
||||
pr_err("Error - ACPU clock reports invalid source\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Look at PLL2's L val to determine what speed PLL2 is running at */
|
||||
if (s->src == PLL_2)
|
||||
for ( ; s->acpu_clk_khz; s++)
|
||||
if (s->pll_rate && s->pll_rate->l == pll2_l)
|
||||
break;
|
||||
|
||||
/* Set initial ACPU VDD. */
|
||||
acpuclk_set_acpu_vdd(s);
|
||||
|
||||
drv_state.current_speed = s;
|
||||
|
||||
/* Initialize current PLL's reference count. */
|
||||
if (s->src >= 0)
|
||||
clk_enable(acpuclk_sources[s->src]);
|
||||
|
||||
res = clk_set_rate(drv_state.ebi1_clk, s->axi_clk_hz);
|
||||
if (res < 0)
|
||||
pr_warning("Setting AXI min rate failed!\n");
|
||||
|
||||
pr_info("ACPU running at %d KHz\n", s->acpu_clk_khz);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* Initalize the lpj field in the acpu_freq_tbl. */
|
||||
static void __init lpj_init(void)
|
||||
{
|
||||
int i;
|
||||
const struct clkctl_acpu_speed *base_clk = drv_state.current_speed;
|
||||
|
||||
for (i = 0; acpu_freq_tbl[i].acpu_clk_khz; i++) {
|
||||
acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy,
|
||||
base_clk->acpu_clk_khz,
|
||||
acpu_freq_tbl[i].acpu_clk_khz);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ_MSM
|
||||
static struct cpufreq_frequency_table cpufreq_tbl[ARRAY_SIZE(acpu_freq_tbl)];
|
||||
|
||||
static void setup_cpufreq_table(void)
|
||||
{
|
||||
unsigned i = 0;
|
||||
const struct clkctl_acpu_speed *speed;
|
||||
|
||||
for (speed = acpu_freq_tbl; speed->acpu_clk_khz; speed++)
|
||||
if (speed->use_for_scaling) {
|
||||
cpufreq_tbl[i].index = i;
|
||||
cpufreq_tbl[i].frequency = speed->acpu_clk_khz;
|
||||
i++;
|
||||
}
|
||||
cpufreq_tbl[i].frequency = CPUFREQ_TABLE_END;
|
||||
|
||||
cpufreq_frequency_table_get_attr(cpufreq_tbl, smp_processor_id());
|
||||
}
|
||||
#else
|
||||
static inline void setup_cpufreq_table(void) { }
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Truncate the frequency table at the current PLL2 rate and determine the
|
||||
* backup PLL to use when scaling PLL2.
|
||||
*/
|
||||
void __init pll2_fixup(void)
|
||||
{
|
||||
struct clkctl_acpu_speed *speed = acpu_freq_tbl;
|
||||
u8 pll2_l = readl_relaxed(PLL2_L_VAL_ADDR) & 0xFF;
|
||||
|
||||
for ( ; speed->acpu_clk_khz; speed++) {
|
||||
if (speed->src != PLL_2)
|
||||
backup_s = speed;
|
||||
if (speed->pll_rate && speed->pll_rate->l == pll2_l) {
|
||||
speed++;
|
||||
speed->acpu_clk_khz = 0;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
pr_err("Unknown PLL2 lval %d\n", pll2_l);
|
||||
BUG();
|
||||
}
|
||||
|
||||
#define RPM_BYPASS_MASK (1 << 3)
|
||||
#define PMIC_MODE_MASK (1 << 4)
|
||||
|
||||
static void __init populate_plls(void)
|
||||
{
|
||||
acpuclk_sources[PLL_1] = clk_get_sys("acpu", "pll1_clk");
|
||||
BUG_ON(IS_ERR(acpuclk_sources[PLL_1]));
|
||||
acpuclk_sources[PLL_2] = clk_get_sys("acpu", "pll2_clk");
|
||||
BUG_ON(IS_ERR(acpuclk_sources[PLL_2]));
|
||||
acpuclk_sources[PLL_3] = clk_get_sys("acpu", "pll3_clk");
|
||||
BUG_ON(IS_ERR(acpuclk_sources[PLL_3]));
|
||||
/*
|
||||
* Prepare all the PLLs because we enable/disable them
|
||||
* from atomic context and can't always ensure they're
|
||||
* all prepared in non-atomic context.
|
||||
*/
|
||||
BUG_ON(clk_prepare(acpuclk_sources[PLL_1]));
|
||||
BUG_ON(clk_prepare(acpuclk_sources[PLL_2]));
|
||||
BUG_ON(clk_prepare(acpuclk_sources[PLL_3]));
|
||||
}
|
||||
|
||||
static struct acpuclk_data acpuclk_7x30_data = {
|
||||
.set_rate = acpuclk_7x30_set_rate,
|
||||
.get_rate = acpuclk_7x30_get_rate,
|
||||
.power_collapse_khz = MAX_AXI_KHZ,
|
||||
.wait_for_irq_khz = MAX_AXI_KHZ,
|
||||
.switch_time_us = 50,
|
||||
};
|
||||
|
||||
static int __init acpuclk_7x30_init(struct acpuclk_soc_data *soc_data)
|
||||
{
|
||||
pr_info("%s()\n", __func__);
|
||||
|
||||
mutex_init(&drv_state.lock);
|
||||
pll2_fixup();
|
||||
populate_plls();
|
||||
acpuclk_hw_init();
|
||||
lpj_init();
|
||||
setup_cpufreq_table();
|
||||
acpuclk_register(&acpuclk_7x30_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct acpuclk_soc_data acpuclk_7x30_soc_data __initdata = {
|
||||
.init = acpuclk_7x30_init,
|
||||
};
|
||||
1619
arch/arm/mach-msm/acpuclock-8960.c
Normal file
1619
arch/arm/mach-msm/acpuclock-8960.c
Normal file
File diff suppressed because it is too large
Load Diff
741
arch/arm/mach-msm/acpuclock-8x50.c
Normal file
741
arch/arm/mach-msm/acpuclock-8x50.c
Normal file
@@ -0,0 +1,741 @@
|
||||
/* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/mfd/tps65023.h>
|
||||
|
||||
#include <mach/board.h>
|
||||
#include <mach/msm_iomap.h>
|
||||
|
||||
#include "acpuclock.h"
|
||||
#include "avs.h"
|
||||
|
||||
#define SHOT_SWITCH 4
|
||||
#define HOP_SWITCH 5
|
||||
#define SIMPLE_SLEW 6
|
||||
#define COMPLEX_SLEW 7
|
||||
|
||||
#define SPSS_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
|
||||
#define SPSS_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
|
||||
|
||||
/* Scorpion PLL registers */
|
||||
#define SCPLL_CTL_ADDR (MSM_SCPLL_BASE + 0x4)
|
||||
#define SCPLL_STATUS_ADDR (MSM_SCPLL_BASE + 0x18)
|
||||
#define SCPLL_FSM_CTL_EXT_ADDR (MSM_SCPLL_BASE + 0x10)
|
||||
|
||||
#ifdef CONFIG_QSD_SVS
|
||||
#define TPS65023_MAX_DCDC1 1600
|
||||
#else
|
||||
#define TPS65023_MAX_DCDC1 CONFIG_QSD_PMIC_DEFAULT_DCDC1
|
||||
#endif
|
||||
|
||||
enum {
|
||||
ACPU_PLL_TCXO = -1,
|
||||
ACPU_PLL_0 = 0,
|
||||
ACPU_PLL_1,
|
||||
ACPU_PLL_2,
|
||||
ACPU_PLL_3,
|
||||
ACPU_PLL_END,
|
||||
};
|
||||
|
||||
struct clkctl_acpu_speed {
|
||||
unsigned int use_for_scaling;
|
||||
unsigned int acpuclk_khz;
|
||||
int pll;
|
||||
unsigned int acpuclk_src_sel;
|
||||
unsigned int acpuclk_src_div;
|
||||
unsigned int ahbclk_khz;
|
||||
unsigned int ahbclk_div;
|
||||
unsigned int axiclk_khz;
|
||||
unsigned int sc_core_src_sel_mask;
|
||||
unsigned int sc_l_value;
|
||||
int vdd;
|
||||
unsigned long lpj; /* loops_per_jiffy */
|
||||
};
|
||||
|
||||
struct clkctl_acpu_speed acpu_freq_tbl_998[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
|
||||
{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
|
||||
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
|
||||
/* Update AXI_S and PLL0_S macros if above row numbers change. */
|
||||
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
|
||||
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
|
||||
{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
|
||||
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
|
||||
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
|
||||
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
|
||||
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
|
||||
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
|
||||
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
|
||||
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
|
||||
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
|
||||
{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
|
||||
{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
|
||||
{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
|
||||
{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
|
||||
{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
|
||||
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
struct clkctl_acpu_speed acpu_freq_tbl_768[] = {
|
||||
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
|
||||
{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
|
||||
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
|
||||
/* Update AXI_S and PLL0_S macros if above row numbers change. */
|
||||
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1075},
|
||||
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1100},
|
||||
{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1125},
|
||||
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1150},
|
||||
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1150},
|
||||
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1150},
|
||||
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1175},
|
||||
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1200},
|
||||
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1225},
|
||||
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1250},
|
||||
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1250},
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_998;
|
||||
#define AXI_S (&acpu_freq_tbl[1])
|
||||
#define PLL0_S (&acpu_freq_tbl[2])
|
||||
|
||||
/* Use 128MHz for PC since ACPU will auto-switch to AXI (128MHz) before
|
||||
* coming back up. This allows detection of return-from-PC, since 128MHz
|
||||
* is only used for power collapse. */
|
||||
#define POWER_COLLAPSE_KHZ 128000
|
||||
/* Use 245MHz (not 128MHz) for SWFI to avoid unnecessary steps between
|
||||
* 128MHz<->245MHz. Jumping to high frequencies from 128MHz directly
|
||||
* is not allowed. */
|
||||
#define WAIT_FOR_IRQ_KHZ 245760
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ_MSM
|
||||
static struct cpufreq_frequency_table freq_table[20];
|
||||
|
||||
static void __init cpufreq_table_init(void)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned int freq_cnt = 0;
|
||||
|
||||
/* Construct the freq_table table from acpu_freq_tbl since the
|
||||
* freq_table values need to match frequencies specified in
|
||||
* acpu_freq_tbl and acpu_freq_tbl needs to be fixed up during init.
|
||||
*/
|
||||
for (i = 0; acpu_freq_tbl[i].acpuclk_khz != 0
|
||||
&& freq_cnt < ARRAY_SIZE(freq_table)-1; i++) {
|
||||
if (acpu_freq_tbl[i].use_for_scaling) {
|
||||
freq_table[freq_cnt].index = freq_cnt;
|
||||
freq_table[freq_cnt].frequency
|
||||
= acpu_freq_tbl[i].acpuclk_khz;
|
||||
freq_cnt++;
|
||||
}
|
||||
}
|
||||
|
||||
/* freq_table not big enough to store all usable freqs. */
|
||||
BUG_ON(acpu_freq_tbl[i].acpuclk_khz != 0);
|
||||
|
||||
freq_table[freq_cnt].index = freq_cnt;
|
||||
freq_table[freq_cnt].frequency = CPUFREQ_TABLE_END;
|
||||
|
||||
pr_info("%d scaling frequencies supported.\n", freq_cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
struct clock_state {
|
||||
struct clkctl_acpu_speed *current_speed;
|
||||
struct mutex lock;
|
||||
struct clk *ebi1_clk;
|
||||
int (*acpu_set_vdd) (int mvolts);
|
||||
};
|
||||
|
||||
static struct clock_state drv_state = { 0 };
|
||||
|
||||
static void scpll_set_freq(uint32_t lval, unsigned freq_switch)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
if (lval > 33)
|
||||
lval = 33;
|
||||
if (lval < 10)
|
||||
lval = 10;
|
||||
|
||||
/* wait for any calibrations or frequency switches to finish */
|
||||
while (readl(SCPLL_STATUS_ADDR) & 0x3)
|
||||
;
|
||||
|
||||
/* write the new L val and switch mode */
|
||||
regval = readl(SCPLL_FSM_CTL_EXT_ADDR);
|
||||
regval &= ~(0x3f << 3);
|
||||
regval |= (lval << 3);
|
||||
if (freq_switch == SIMPLE_SLEW)
|
||||
regval |= (0x1 << 9);
|
||||
|
||||
regval &= ~(0x3 << 0);
|
||||
regval |= (freq_switch << 0);
|
||||
writel(regval, SCPLL_FSM_CTL_EXT_ADDR);
|
||||
|
||||
dmb();
|
||||
|
||||
/* put in normal mode */
|
||||
regval = readl(SCPLL_CTL_ADDR);
|
||||
regval |= 0x7;
|
||||
writel(regval, SCPLL_CTL_ADDR);
|
||||
|
||||
dmb();
|
||||
|
||||
/* wait for frequency switch to finish */
|
||||
while (readl(SCPLL_STATUS_ADDR) & 0x1)
|
||||
;
|
||||
|
||||
/* status bit seems to clear early, using
|
||||
* 100us to handle the worst case. */
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
static void scpll_apps_enable(bool state)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
if (state)
|
||||
pr_debug("Enabling PLL 3\n");
|
||||
else
|
||||
pr_debug("Disabling PLL 3\n");
|
||||
|
||||
/* Wait for any frequency switches to finish. */
|
||||
while (readl(SCPLL_STATUS_ADDR) & 0x1)
|
||||
;
|
||||
|
||||
/* put the pll in standby mode */
|
||||
regval = readl(SCPLL_CTL_ADDR);
|
||||
regval &= ~(0x7);
|
||||
regval |= (0x2);
|
||||
writel(regval, SCPLL_CTL_ADDR);
|
||||
|
||||
dmb();
|
||||
|
||||
if (state) {
|
||||
/* put the pll in normal mode */
|
||||
regval = readl(SCPLL_CTL_ADDR);
|
||||
regval |= (0x7);
|
||||
writel(regval, SCPLL_CTL_ADDR);
|
||||
udelay(200);
|
||||
} else {
|
||||
/* put the pll in power down mode */
|
||||
regval = readl(SCPLL_CTL_ADDR);
|
||||
regval &= ~(0x7);
|
||||
writel(regval, SCPLL_CTL_ADDR);
|
||||
}
|
||||
udelay(62);
|
||||
|
||||
if (state)
|
||||
pr_debug("PLL 3 Enabled\n");
|
||||
else
|
||||
pr_debug("PLL 3 Disabled\n");
|
||||
}
|
||||
|
||||
static void scpll_init(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
#define L_VAL_384MHZ 0xA
|
||||
#define L_VAL_768MHZ 0x14
|
||||
|
||||
pr_debug("Initializing PLL 3\n");
|
||||
|
||||
/* power down scpll */
|
||||
writel(0x0, SCPLL_CTL_ADDR);
|
||||
|
||||
dmb();
|
||||
|
||||
/* set bypassnl, put into standby */
|
||||
writel(0x00400002, SCPLL_CTL_ADDR);
|
||||
|
||||
/* set bypassnl, reset_n, full calibration */
|
||||
writel(0x00600004, SCPLL_CTL_ADDR);
|
||||
|
||||
/* Ensure register write to initiate calibration has taken
|
||||
effect before reading status flag */
|
||||
dmb();
|
||||
|
||||
/* wait for cal_all_done */
|
||||
while (readl(SCPLL_STATUS_ADDR) & 0x2)
|
||||
;
|
||||
|
||||
/* Start: Set of experimentally derived steps
|
||||
* to work around a h/w bug. */
|
||||
|
||||
/* Put the pll in normal mode */
|
||||
scpll_apps_enable(1);
|
||||
|
||||
/* SHOT switch to 384 MHz */
|
||||
regval = readl(SCPLL_FSM_CTL_EXT_ADDR);
|
||||
regval &= ~(0x3f << 3);
|
||||
regval |= (L_VAL_384MHZ << 3);
|
||||
|
||||
regval &= ~0x7;
|
||||
regval |= SHOT_SWITCH;
|
||||
writel(regval, SCPLL_FSM_CTL_EXT_ADDR);
|
||||
|
||||
/* Trigger the freq switch by putting pll in normal mode. */
|
||||
regval = readl(SCPLL_CTL_ADDR);
|
||||
regval |= (0x7);
|
||||
writel(regval, SCPLL_CTL_ADDR);
|
||||
|
||||
/* Wait for frequency switch to finish */
|
||||
while (readl(SCPLL_STATUS_ADDR) & 0x1)
|
||||
;
|
||||
|
||||
/* Status bit seems to clear early, using
|
||||
* 800 microseconds for the worst case. */
|
||||
udelay(800);
|
||||
|
||||
/* HOP switch to 768 MHz. */
|
||||
regval = readl(SCPLL_FSM_CTL_EXT_ADDR);
|
||||
regval &= ~(0x3f << 3);
|
||||
regval |= (L_VAL_768MHZ << 3);
|
||||
|
||||
regval &= ~0x7;
|
||||
regval |= HOP_SWITCH;
|
||||
writel(regval, SCPLL_FSM_CTL_EXT_ADDR);
|
||||
|
||||
/* Trigger the freq switch by putting pll in normal mode. */
|
||||
regval = readl(SCPLL_CTL_ADDR);
|
||||
regval |= (0x7);
|
||||
writel(regval, SCPLL_CTL_ADDR);
|
||||
|
||||
/* Wait for frequency switch to finish */
|
||||
while (readl(SCPLL_STATUS_ADDR) & 0x1)
|
||||
;
|
||||
|
||||
/* Status bit seems to clear early, using
|
||||
* 100 microseconds for the worst case. */
|
||||
udelay(100);
|
||||
|
||||
/* End: Work around for h/w bug */
|
||||
|
||||
/* Power down scpll */
|
||||
scpll_apps_enable(0);
|
||||
}
|
||||
|
||||
static void config_pll(struct clkctl_acpu_speed *s)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
if (s->pll == ACPU_PLL_3)
|
||||
scpll_set_freq(s->sc_l_value, HOP_SWITCH);
|
||||
/* Configure the PLL divider mux if we plan to use it. */
|
||||
else if (s->sc_core_src_sel_mask == 0) {
|
||||
/* get the current clock source selection */
|
||||
regval = readl(SPSS_CLK_SEL_ADDR) & 0x1;
|
||||
|
||||
/* configure the other clock source, then switch to it,
|
||||
* using the glitch free mux */
|
||||
switch (regval) {
|
||||
case 0x0:
|
||||
regval = readl(SPSS_CLK_CNTL_ADDR);
|
||||
regval &= ~(0x7 << 4 | 0xf);
|
||||
regval |= (s->acpuclk_src_sel << 4);
|
||||
regval |= (s->acpuclk_src_div << 0);
|
||||
writel(regval, SPSS_CLK_CNTL_ADDR);
|
||||
|
||||
regval = readl(SPSS_CLK_SEL_ADDR);
|
||||
regval |= 0x1;
|
||||
writel(regval, SPSS_CLK_SEL_ADDR);
|
||||
break;
|
||||
|
||||
case 0x1:
|
||||
regval = readl(SPSS_CLK_CNTL_ADDR);
|
||||
regval &= ~(0x7 << 12 | 0xf << 8);
|
||||
regval |= (s->acpuclk_src_sel << 12);
|
||||
regval |= (s->acpuclk_src_div << 8);
|
||||
writel(regval, SPSS_CLK_CNTL_ADDR);
|
||||
|
||||
regval = readl(SPSS_CLK_SEL_ADDR);
|
||||
regval &= ~0x1;
|
||||
writel(regval, SPSS_CLK_SEL_ADDR);
|
||||
break;
|
||||
}
|
||||
dmb();
|
||||
}
|
||||
|
||||
regval = readl(SPSS_CLK_SEL_ADDR);
|
||||
regval &= ~(0x3 << 1);
|
||||
regval |= (s->sc_core_src_sel_mask << 1);
|
||||
writel(regval, SPSS_CLK_SEL_ADDR);
|
||||
}
|
||||
|
||||
static int acpuclk_set_vdd_level(int vdd)
|
||||
{
|
||||
if (drv_state.acpu_set_vdd) {
|
||||
pr_debug("Switching VDD to %d mV\n", vdd);
|
||||
return drv_state.acpu_set_vdd(vdd);
|
||||
} else {
|
||||
/* Assume that the PMIC supports scaling the processor
|
||||
* to its maximum frequency at its default voltage.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static int acpuclk_8x50_set_rate(int cpu, unsigned long rate,
|
||||
enum setrate_reason reason)
|
||||
{
|
||||
struct clkctl_acpu_speed *tgt_s, *strt_s;
|
||||
int res, rc = 0;
|
||||
int freq_index = 0;
|
||||
|
||||
if (reason == SETRATE_CPUFREQ)
|
||||
mutex_lock(&drv_state.lock);
|
||||
|
||||
strt_s = drv_state.current_speed;
|
||||
|
||||
if (rate == strt_s->acpuclk_khz)
|
||||
goto out;
|
||||
|
||||
for (tgt_s = acpu_freq_tbl; tgt_s->acpuclk_khz != 0; tgt_s++) {
|
||||
if (tgt_s->acpuclk_khz == rate)
|
||||
break;
|
||||
freq_index++;
|
||||
}
|
||||
|
||||
if (tgt_s->acpuclk_khz == 0) {
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (reason == SETRATE_CPUFREQ) {
|
||||
#ifdef CONFIG_MSM_CPU_AVS
|
||||
/* Notify avs before changing frequency */
|
||||
rc = avs_adjust_freq(freq_index, 1);
|
||||
if (rc) {
|
||||
pr_err("Unable to increase ACPU vdd (%d)\n", rc);
|
||||
goto out;
|
||||
}
|
||||
#endif
|
||||
/* Increase VDD if needed. */
|
||||
if (tgt_s->vdd > strt_s->vdd) {
|
||||
rc = acpuclk_set_vdd_level(tgt_s->vdd);
|
||||
if (rc) {
|
||||
pr_err("Unable to increase ACPU vdd (%d)\n",
|
||||
rc);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
} else if (reason == SETRATE_PC
|
||||
&& rate != POWER_COLLAPSE_KHZ) {
|
||||
/* Returning from PC. ACPU is running on AXI source.
|
||||
* Step up to PLL0 before ramping up higher. */
|
||||
config_pll(PLL0_S);
|
||||
}
|
||||
|
||||
pr_debug("Switching from ACPU rate %u KHz -> %u KHz\n",
|
||||
strt_s->acpuclk_khz, tgt_s->acpuclk_khz);
|
||||
|
||||
if (strt_s->pll != ACPU_PLL_3 && tgt_s->pll != ACPU_PLL_3) {
|
||||
config_pll(tgt_s);
|
||||
} else if (strt_s->pll != ACPU_PLL_3 && tgt_s->pll == ACPU_PLL_3) {
|
||||
scpll_apps_enable(1);
|
||||
config_pll(tgt_s);
|
||||
} else if (strt_s->pll == ACPU_PLL_3 && tgt_s->pll != ACPU_PLL_3) {
|
||||
config_pll(tgt_s);
|
||||
scpll_apps_enable(0);
|
||||
} else {
|
||||
/* Temporarily switch to PLL0 while reconfiguring PLL3. */
|
||||
config_pll(PLL0_S);
|
||||
config_pll(tgt_s);
|
||||
}
|
||||
|
||||
/* Update the driver state with the new clock freq */
|
||||
drv_state.current_speed = tgt_s;
|
||||
|
||||
/* Re-adjust lpj for the new clock speed. */
|
||||
loops_per_jiffy = tgt_s->lpj;
|
||||
|
||||
/* Nothing else to do for SWFI. */
|
||||
if (reason == SETRATE_SWFI)
|
||||
goto out;
|
||||
|
||||
if (strt_s->axiclk_khz != tgt_s->axiclk_khz) {
|
||||
res = clk_set_rate(drv_state.ebi1_clk,
|
||||
tgt_s->axiclk_khz * 1000);
|
||||
if (res < 0)
|
||||
pr_warning("Setting AXI min rate failed (%d)\n", res);
|
||||
}
|
||||
|
||||
/* Nothing else to do for power collapse */
|
||||
if (reason == SETRATE_PC)
|
||||
goto out;
|
||||
|
||||
#ifdef CONFIG_MSM_CPU_AVS
|
||||
/* notify avs after changing frequency */
|
||||
res = avs_adjust_freq(freq_index, 0);
|
||||
if (res)
|
||||
pr_warning("Unable to drop ACPU vdd (%d)\n", res);
|
||||
#endif
|
||||
|
||||
/* Drop VDD level if we can. */
|
||||
if (tgt_s->vdd < strt_s->vdd) {
|
||||
res = acpuclk_set_vdd_level(tgt_s->vdd);
|
||||
if (res)
|
||||
pr_warning("Unable to drop ACPU vdd (%d)\n", res);
|
||||
}
|
||||
|
||||
pr_debug("ACPU speed change complete\n");
|
||||
out:
|
||||
if (reason == SETRATE_CPUFREQ)
|
||||
mutex_unlock(&drv_state.lock);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void __init acpuclk_hw_init(void)
|
||||
{
|
||||
struct clkctl_acpu_speed *speed;
|
||||
uint32_t div, sel, regval;
|
||||
int res;
|
||||
|
||||
/* Determine the source of the Scorpion clock. */
|
||||
regval = readl(SPSS_CLK_SEL_ADDR);
|
||||
switch ((regval & 0x6) >> 1) {
|
||||
case 0: /* raw source clock */
|
||||
case 3: /* low jitter PLL1 (768Mhz) */
|
||||
if (regval & 0x1) {
|
||||
sel = ((readl(SPSS_CLK_CNTL_ADDR) >> 4) & 0x7);
|
||||
div = ((readl(SPSS_CLK_CNTL_ADDR) >> 0) & 0xf);
|
||||
} else {
|
||||
sel = ((readl(SPSS_CLK_CNTL_ADDR) >> 12) & 0x7);
|
||||
div = ((readl(SPSS_CLK_CNTL_ADDR) >> 8) & 0xf);
|
||||
}
|
||||
|
||||
/* Find the matching clock rate. */
|
||||
for (speed = acpu_freq_tbl; speed->acpuclk_khz != 0; speed++) {
|
||||
if (speed->acpuclk_src_sel == sel &&
|
||||
speed->acpuclk_src_div == div)
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 1: /* unbuffered scorpion pll (384Mhz to 998.4Mhz) */
|
||||
sel = ((readl(SCPLL_FSM_CTL_EXT_ADDR) >> 3) & 0x3f);
|
||||
|
||||
/* Find the matching clock rate. */
|
||||
for (speed = acpu_freq_tbl; speed->acpuclk_khz != 0; speed++) {
|
||||
if (speed->sc_l_value == sel &&
|
||||
speed->sc_core_src_sel_mask == 1)
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 2: /* AXI bus clock (128Mhz) */
|
||||
speed = AXI_S;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
||||
/* Initialize scpll only if it wasn't already initialized by the boot
|
||||
* loader. If the CPU is already running on scpll, then the scpll was
|
||||
* initialized by the boot loader. */
|
||||
if (speed->pll != ACPU_PLL_3)
|
||||
scpll_init();
|
||||
|
||||
if (speed->acpuclk_khz == 0) {
|
||||
pr_err("Error - ACPU clock reports invalid speed\n");
|
||||
return;
|
||||
}
|
||||
|
||||
drv_state.current_speed = speed;
|
||||
res = clk_set_rate(drv_state.ebi1_clk, speed->axiclk_khz * 1000);
|
||||
if (res < 0)
|
||||
pr_warning("Setting AXI min rate failed (%d)\n", res);
|
||||
res = clk_enable(drv_state.ebi1_clk);
|
||||
if (res < 0)
|
||||
pr_warning("Enabling AXI clock failed (%d)\n", res);
|
||||
|
||||
pr_info("ACPU running at %d KHz\n", speed->acpuclk_khz);
|
||||
}
|
||||
|
||||
static unsigned long acpuclk_8x50_get_rate(int cpu)
|
||||
{
|
||||
return drv_state.current_speed->acpuclk_khz;
|
||||
}
|
||||
|
||||
/* Spare register populated with efuse data on max ACPU freq. */
|
||||
#define CT_CSR_PHYS 0xA8700000
|
||||
#define TCSR_SPARE2_ADDR (ct_csr_base + 0x60)
|
||||
|
||||
#define PLL0_M_VAL_ADDR (MSM_CLK_CTL_BASE + 0x308)
|
||||
|
||||
static void __init acpu_freq_tbl_fixup(void)
|
||||
{
|
||||
void __iomem *ct_csr_base;
|
||||
uint32_t tcsr_spare2, pll0_m_val;
|
||||
unsigned int max_acpu_khz;
|
||||
unsigned int i;
|
||||
|
||||
ct_csr_base = ioremap(CT_CSR_PHYS, PAGE_SIZE);
|
||||
BUG_ON(ct_csr_base == NULL);
|
||||
|
||||
tcsr_spare2 = readl(TCSR_SPARE2_ADDR);
|
||||
|
||||
/* Check if the register is supported and meaningful. */
|
||||
if ((tcsr_spare2 & 0xF000) != 0xA000) {
|
||||
pr_info("Efuse data on Max ACPU freq not present.\n");
|
||||
goto skip_efuse_fixup;
|
||||
}
|
||||
|
||||
switch (tcsr_spare2 & 0xF0) {
|
||||
case 0x70:
|
||||
acpu_freq_tbl = acpu_freq_tbl_768;
|
||||
max_acpu_khz = 768000;
|
||||
break;
|
||||
case 0x30:
|
||||
case 0x00:
|
||||
max_acpu_khz = 998400;
|
||||
break;
|
||||
case 0x10:
|
||||
max_acpu_khz = 1267200;
|
||||
break;
|
||||
default:
|
||||
pr_warning("Invalid efuse data (%x) on Max ACPU freq!\n",
|
||||
tcsr_spare2);
|
||||
goto skip_efuse_fixup;
|
||||
}
|
||||
|
||||
pr_info("Max ACPU freq from efuse data is %d KHz\n", max_acpu_khz);
|
||||
|
||||
for (i = 0; acpu_freq_tbl[i].acpuclk_khz != 0; i++) {
|
||||
if (acpu_freq_tbl[i].acpuclk_khz > max_acpu_khz) {
|
||||
acpu_freq_tbl[i].acpuclk_khz = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
skip_efuse_fixup:
|
||||
iounmap(ct_csr_base);
|
||||
|
||||
/* pll0_m_val will be 36 when PLL0 is run at 235MHz
|
||||
* instead of the usual 245MHz. */
|
||||
pll0_m_val = readl(PLL0_M_VAL_ADDR) & 0x7FFFF;
|
||||
if (pll0_m_val == 36)
|
||||
PLL0_S->acpuclk_khz = 235930;
|
||||
|
||||
for (i = 0; acpu_freq_tbl[i].acpuclk_khz != 0; i++) {
|
||||
if (acpu_freq_tbl[i].vdd > TPS65023_MAX_DCDC1) {
|
||||
acpu_freq_tbl[i].acpuclk_khz = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Initalize the lpj field in the acpu_freq_tbl. */
|
||||
static void __init lpj_init(void)
|
||||
{
|
||||
int i;
|
||||
const struct clkctl_acpu_speed *base_clk = drv_state.current_speed;
|
||||
for (i = 0; acpu_freq_tbl[i].acpuclk_khz; i++) {
|
||||
acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy,
|
||||
base_clk->acpuclk_khz,
|
||||
acpu_freq_tbl[i].acpuclk_khz);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MSM_CPU_AVS
|
||||
static int __init acpu_avs_init(int (*set_vdd) (int), int khz)
|
||||
{
|
||||
int i;
|
||||
int freq_count = 0;
|
||||
int freq_index = -1;
|
||||
|
||||
for (i = 0; acpu_freq_tbl[i].acpuclk_khz; i++) {
|
||||
freq_count++;
|
||||
if (acpu_freq_tbl[i].acpuclk_khz == khz)
|
||||
freq_index = i;
|
||||
}
|
||||
|
||||
return avs_init(set_vdd, freq_count, freq_index);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int qsd8x50_tps65023_set_dcdc1(int mVolts)
|
||||
{
|
||||
int rc = 0;
|
||||
#ifdef CONFIG_QSD_SVS
|
||||
rc = tps65023_set_dcdc1_level(mVolts);
|
||||
/*
|
||||
* By default the TPS65023 will be initialized to 1.225V.
|
||||
* So we can safely switch to any frequency within this
|
||||
* voltage even if the device is not probed/ready.
|
||||
*/
|
||||
if (rc == -ENODEV && mVolts <= CONFIG_QSD_PMIC_DEFAULT_DCDC1)
|
||||
rc = 0;
|
||||
#else
|
||||
/*
|
||||
* Disallow frequencies not supported in the default PMIC
|
||||
* output voltage.
|
||||
*/
|
||||
if (mVolts > CONFIG_QSD_PMIC_DEFAULT_DCDC1)
|
||||
rc = -EFAULT;
|
||||
#endif
|
||||
return rc;
|
||||
}
|
||||
|
||||
static struct acpuclk_data acpuclk_8x50_data = {
|
||||
.set_rate = acpuclk_8x50_set_rate,
|
||||
.get_rate = acpuclk_8x50_get_rate,
|
||||
.power_collapse_khz = POWER_COLLAPSE_KHZ,
|
||||
.wait_for_irq_khz = WAIT_FOR_IRQ_KHZ,
|
||||
.switch_time_us = 20,
|
||||
};
|
||||
|
||||
static int __init acpuclk_8x50_init(struct acpuclk_soc_data *soc_data)
|
||||
{
|
||||
mutex_init(&drv_state.lock);
|
||||
drv_state.acpu_set_vdd = qsd8x50_tps65023_set_dcdc1;
|
||||
|
||||
drv_state.ebi1_clk = clk_get(NULL, "ebi1_acpu_clk");
|
||||
BUG_ON(IS_ERR(drv_state.ebi1_clk));
|
||||
|
||||
acpu_freq_tbl_fixup();
|
||||
acpuclk_hw_init();
|
||||
lpj_init();
|
||||
/* Set a lower bound for ACPU rate for boot. This limits the
|
||||
* maximum frequency hop caused by the first CPUFREQ switch. */
|
||||
if (drv_state.current_speed->acpuclk_khz < PLL0_S->acpuclk_khz)
|
||||
acpuclk_set_rate(0, PLL0_S->acpuclk_khz, SETRATE_CPUFREQ);
|
||||
|
||||
acpuclk_register(&acpuclk_8x50_data);
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ_MSM
|
||||
cpufreq_table_init();
|
||||
cpufreq_frequency_table_get_attr(freq_table, smp_processor_id());
|
||||
#endif
|
||||
#ifdef CONFIG_MSM_CPU_AVS
|
||||
if (!acpu_avs_init(drv_state.acpu_set_vdd,
|
||||
drv_state.current_speed->acpuclk_khz)) {
|
||||
/* avs init successful. avs will handle voltage changes */
|
||||
drv_state.acpu_set_vdd = NULL;
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct acpuclk_soc_data acpuclk_8x50_soc_data __initdata = {
|
||||
.init = acpuclk_8x50_init,
|
||||
};
|
||||
1096
arch/arm/mach-msm/acpuclock-8x60.c
Normal file
1096
arch/arm/mach-msm/acpuclock-8x60.c
Normal file
File diff suppressed because it is too large
Load Diff
356
arch/arm/mach-msm/acpuclock-9615.c
Normal file
356
arch/arm/mach-msm/acpuclock-9615.c
Normal file
@@ -0,0 +1,356 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <asm/cpu.h>
|
||||
|
||||
#include <mach/board.h>
|
||||
#include <mach/msm_iomap.h>
|
||||
#include <mach/msm_bus.h>
|
||||
#include <mach/msm_bus_board.h>
|
||||
#include <mach/rpm-regulator.h>
|
||||
|
||||
#include "acpuclock.h"
|
||||
|
||||
#define REG_CLKSEL_0 (MSM_APCS_GLB_BASE + 0x08)
|
||||
#define REG_CLKDIV_0 (MSM_APCS_GLB_BASE + 0x0C)
|
||||
#define REG_CLKSEL_1 (MSM_APCS_GLB_BASE + 0x10)
|
||||
#define REG_CLKDIV_1 (MSM_APCS_GLB_BASE + 0x14)
|
||||
#define REG_CLKOUTSEL (MSM_APCS_GLB_BASE + 0x18)
|
||||
|
||||
#define MAX_VDD_CPU 1150000
|
||||
#define MAX_VDD_MEM 1150000
|
||||
|
||||
enum clk_src {
|
||||
SRC_CXO,
|
||||
SRC_PLL0,
|
||||
SRC_PLL8,
|
||||
SRC_PLL9,
|
||||
NUM_SRC,
|
||||
};
|
||||
|
||||
struct src_clock {
|
||||
struct clk *clk;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
static struct src_clock clocks[NUM_SRC] = {
|
||||
[SRC_PLL0].name = "pll0",
|
||||
[SRC_PLL8].name = "pll8",
|
||||
[SRC_PLL9].name = "pll9",
|
||||
};
|
||||
|
||||
struct clkctl_acpu_speed {
|
||||
bool use_for_scaling;
|
||||
unsigned int khz;
|
||||
int src;
|
||||
unsigned int src_sel;
|
||||
unsigned int src_div;
|
||||
unsigned int vdd_cpu;
|
||||
unsigned int vdd_mem;
|
||||
unsigned int bw_level;
|
||||
};
|
||||
|
||||
struct acpuclk_state {
|
||||
struct mutex lock;
|
||||
struct clkctl_acpu_speed *current_speed;
|
||||
};
|
||||
|
||||
static struct acpuclk_state drv_state = {
|
||||
.current_speed = &(struct clkctl_acpu_speed){ 0 },
|
||||
};
|
||||
|
||||
/* Instantaneous bandwidth requests in MB/s. */
|
||||
#define BW_MBPS(_bw) \
|
||||
{ \
|
||||
.vectors = &(struct msm_bus_vectors){ \
|
||||
.src = MSM_BUS_MASTER_AMPSS_M0, \
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0, \
|
||||
.ib = (_bw) * 1000000UL, \
|
||||
.ab = 0, \
|
||||
}, \
|
||||
.num_paths = 1, \
|
||||
}
|
||||
static struct msm_bus_paths bw_level_tbl[] = {
|
||||
[0] = BW_MBPS(152), /* At least 19 MHz on bus. */
|
||||
[1] = BW_MBPS(368), /* At least 46 MHz on bus. */
|
||||
[2] = BW_MBPS(552), /* At least 69 MHz on bus. */
|
||||
[3] = BW_MBPS(736), /* At least 92 MHz on bus. */
|
||||
[4] = BW_MBPS(1064), /* At least 133 MHz on bus. */
|
||||
[5] = BW_MBPS(1536), /* At least 192 MHz on bus. */
|
||||
};
|
||||
|
||||
static struct msm_bus_scale_pdata bus_client_pdata = {
|
||||
.usecase = bw_level_tbl,
|
||||
.num_usecases = ARRAY_SIZE(bw_level_tbl),
|
||||
.active_only = 1,
|
||||
.name = "acpuclock",
|
||||
};
|
||||
|
||||
static uint32_t bus_perf_client;
|
||||
|
||||
static struct clkctl_acpu_speed acpu_freq_tbl[] = {
|
||||
{ 0, 19200, SRC_CXO, 0, 0, 950000, 1050000, 0 },
|
||||
{ 1, 138000, SRC_PLL0, 6, 1, 950000, 1050000, 2 },
|
||||
{ 1, 276000, SRC_PLL0, 6, 0, 1050000, 1050000, 2 },
|
||||
{ 1, 384000, SRC_PLL8, 3, 0, 1150000, 1150000, 4 },
|
||||
/* The row below may be changed at runtime depending on hw rev. */
|
||||
{ 1, 440000, SRC_PLL9, 2, 0, 1150000, 1150000, 4 },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
static void select_clk_source_div(struct clkctl_acpu_speed *s)
|
||||
{
|
||||
static void * __iomem const sel_reg[] = {REG_CLKSEL_0, REG_CLKSEL_1};
|
||||
static void * __iomem const div_reg[] = {REG_CLKDIV_0, REG_CLKDIV_1};
|
||||
uint32_t next_bank;
|
||||
|
||||
next_bank = !(readl_relaxed(REG_CLKOUTSEL) & 1);
|
||||
writel_relaxed(s->src_sel, sel_reg[next_bank]);
|
||||
writel_relaxed(s->src_div, div_reg[next_bank]);
|
||||
writel_relaxed(next_bank, REG_CLKOUTSEL);
|
||||
|
||||
/* Wait for switch to complete. */
|
||||
mb();
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
/* Update the bus bandwidth request. */
|
||||
static void set_bus_bw(unsigned int bw)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Bounds check. */
|
||||
if (bw >= ARRAY_SIZE(bw_level_tbl)) {
|
||||
pr_err("invalid bandwidth request (%d)\n", bw);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Update bandwidth if request has changed. This may sleep. */
|
||||
ret = msm_bus_scale_client_update_request(bus_perf_client, bw);
|
||||
if (ret)
|
||||
pr_err("bandwidth request failed (%d)\n", ret);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* Apply any per-cpu voltage increases. */
|
||||
static int increase_vdd(unsigned int vdd_cpu, unsigned int vdd_mem)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
/*
|
||||
* Increase vdd_mem active-set before vdd_cpu.
|
||||
* vdd_mem should be >= vdd_cpu.
|
||||
*/
|
||||
rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8018_L9, RPM_VREG_VOTER1,
|
||||
vdd_mem, MAX_VDD_MEM, 0);
|
||||
if (rc) {
|
||||
pr_err("vdd_mem increase failed (%d)\n", rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8018_S1, RPM_VREG_VOTER1,
|
||||
vdd_cpu, MAX_VDD_CPU, 0);
|
||||
if (rc)
|
||||
pr_err("vdd_cpu increase failed (%d)\n", rc);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Apply any per-cpu voltage decreases. */
|
||||
static void decrease_vdd(unsigned int vdd_cpu, unsigned int vdd_mem)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Update CPU voltage. */
|
||||
ret = rpm_vreg_set_voltage(RPM_VREG_ID_PM8018_S1, RPM_VREG_VOTER1,
|
||||
vdd_cpu, MAX_VDD_CPU, 0);
|
||||
if (ret) {
|
||||
pr_err("vdd_cpu decrease failed (%d)\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Decrease vdd_mem active-set after vdd_cpu.
|
||||
* vdd_mem should be >= vdd_cpu.
|
||||
*/
|
||||
ret = rpm_vreg_set_voltage(RPM_VREG_ID_PM8018_L9, RPM_VREG_VOTER1,
|
||||
vdd_mem, MAX_VDD_MEM, 0);
|
||||
if (ret)
|
||||
pr_err("vdd_mem decrease failed (%d)\n", ret);
|
||||
}
|
||||
|
||||
static int acpuclk_9615_set_rate(int cpu, unsigned long rate,
|
||||
enum setrate_reason reason)
|
||||
{
|
||||
struct clkctl_acpu_speed *tgt_s, *strt_s;
|
||||
int rc = 0;
|
||||
|
||||
if (reason == SETRATE_CPUFREQ)
|
||||
mutex_lock(&drv_state.lock);
|
||||
|
||||
strt_s = drv_state.current_speed;
|
||||
|
||||
/* Return early if rate didn't change. */
|
||||
if (rate == strt_s->khz)
|
||||
goto out;
|
||||
|
||||
/* Find target frequency. */
|
||||
for (tgt_s = acpu_freq_tbl; tgt_s->khz != 0; tgt_s++)
|
||||
if (tgt_s->khz == rate)
|
||||
break;
|
||||
if (tgt_s->khz == 0) {
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Increase VDD levels if needed. */
|
||||
if ((reason == SETRATE_CPUFREQ || reason == SETRATE_INIT)
|
||||
&& (tgt_s->khz > strt_s->khz)) {
|
||||
rc = increase_vdd(tgt_s->vdd_cpu, tgt_s->vdd_mem);
|
||||
if (rc)
|
||||
goto out;
|
||||
}
|
||||
|
||||
pr_debug("Switching from CPU rate %u KHz -> %u KHz\n",
|
||||
strt_s->khz, tgt_s->khz);
|
||||
|
||||
/* Switch CPU speed. */
|
||||
clk_enable(clocks[tgt_s->src].clk);
|
||||
select_clk_source_div(tgt_s);
|
||||
clk_disable(clocks[strt_s->src].clk);
|
||||
|
||||
drv_state.current_speed = tgt_s;
|
||||
pr_debug("CPU speed change complete\n");
|
||||
|
||||
/* Nothing else to do for SWFI or power-collapse. */
|
||||
if (reason == SETRATE_SWFI || reason == SETRATE_PC)
|
||||
goto out;
|
||||
|
||||
/* Update bus bandwith request. */
|
||||
set_bus_bw(tgt_s->bw_level);
|
||||
|
||||
/* Drop VDD levels if we can. */
|
||||
if (tgt_s->khz < strt_s->khz)
|
||||
decrease_vdd(tgt_s->vdd_cpu, tgt_s->vdd_mem);
|
||||
|
||||
out:
|
||||
if (reason == SETRATE_CPUFREQ)
|
||||
mutex_unlock(&drv_state.lock);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static unsigned long acpuclk_9615_get_rate(int cpu)
|
||||
{
|
||||
return drv_state.current_speed->khz;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ_MSM
|
||||
static struct cpufreq_frequency_table freq_table[30];
|
||||
|
||||
static void __init cpufreq_table_init(void)
|
||||
{
|
||||
int i, freq_cnt = 0;
|
||||
|
||||
/* Construct the freq_table tables from acpu_freq_tbl. */
|
||||
for (i = 0; acpu_freq_tbl[i].khz != 0
|
||||
&& freq_cnt < ARRAY_SIZE(freq_table); i++) {
|
||||
if (acpu_freq_tbl[i].use_for_scaling) {
|
||||
freq_table[freq_cnt].index = freq_cnt;
|
||||
freq_table[freq_cnt].frequency
|
||||
= acpu_freq_tbl[i].khz;
|
||||
freq_cnt++;
|
||||
}
|
||||
}
|
||||
/* freq_table not big enough to store all usable freqs. */
|
||||
BUG_ON(acpu_freq_tbl[i].khz != 0);
|
||||
|
||||
freq_table[freq_cnt].index = freq_cnt;
|
||||
freq_table[freq_cnt].frequency = CPUFREQ_TABLE_END;
|
||||
|
||||
pr_info("CPU: %d scaling frequencies supported.\n", freq_cnt);
|
||||
|
||||
/* Register table with CPUFreq. */
|
||||
cpufreq_frequency_table_get_attr(freq_table, smp_processor_id());
|
||||
}
|
||||
#else
|
||||
static void __init cpufreq_table_init(void) {}
|
||||
#endif
|
||||
|
||||
static struct acpuclk_data acpuclk_9615_data = {
|
||||
.set_rate = acpuclk_9615_set_rate,
|
||||
.get_rate = acpuclk_9615_get_rate,
|
||||
.power_collapse_khz = 19200,
|
||||
.wait_for_irq_khz = 19200,
|
||||
};
|
||||
|
||||
static int __init acpuclk_9615_init(struct acpuclk_soc_data *soc_data)
|
||||
{
|
||||
unsigned long max_cpu_khz = 0;
|
||||
int i;
|
||||
|
||||
mutex_init(&drv_state.lock);
|
||||
|
||||
bus_perf_client = msm_bus_scale_register_client(&bus_client_pdata);
|
||||
if (!bus_perf_client) {
|
||||
pr_err("Unable to register bus client\n");
|
||||
BUG();
|
||||
}
|
||||
|
||||
for (i = 0; i < NUM_SRC; i++) {
|
||||
if (clocks[i].name) {
|
||||
clocks[i].clk = clk_get_sys("acpu", clocks[i].name);
|
||||
BUG_ON(IS_ERR(clocks[i].clk));
|
||||
/*
|
||||
* Prepare the PLLs because we enable/disable them
|
||||
* in atomic context during power collapse/restore.
|
||||
*/
|
||||
BUG_ON(clk_prepare(clocks[i].clk));
|
||||
}
|
||||
}
|
||||
|
||||
/* Determine the rate of PLL9 and fixup tables accordingly */
|
||||
if (clk_get_rate(clocks[SRC_PLL9].clk) == 550000000) {
|
||||
for (i = 0; i < ARRAY_SIZE(acpu_freq_tbl); i++)
|
||||
if (acpu_freq_tbl[i].src == SRC_PLL9) {
|
||||
acpu_freq_tbl[i].khz = 550000;
|
||||
acpu_freq_tbl[i].bw_level = 5;
|
||||
}
|
||||
}
|
||||
|
||||
/* Improve boot time by ramping up CPU immediately. */
|
||||
for (i = 0; acpu_freq_tbl[i].khz != 0; i++)
|
||||
max_cpu_khz = acpu_freq_tbl[i].khz;
|
||||
acpuclk_9615_set_rate(smp_processor_id(), max_cpu_khz, SETRATE_INIT);
|
||||
|
||||
acpuclk_register(&acpuclk_9615_data);
|
||||
cpufreq_table_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct acpuclk_soc_data acpuclk_9615_soc_data __initdata = {
|
||||
.init = acpuclk_9615_init,
|
||||
};
|
||||
@@ -17,6 +17,7 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/version.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/list.h>
|
||||
@@ -29,8 +30,8 @@
|
||||
#include <linux/io.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/msm_iomap.h>
|
||||
#include <mach/proc_comm.h>
|
||||
|
||||
#include "proc_comm.h"
|
||||
#include "acpuclock.h"
|
||||
|
||||
|
||||
@@ -97,7 +98,7 @@ struct clkctl_acpu_speed {
|
||||
|
||||
/*
|
||||
* ACPU speed table. Complete table is shown but certain speeds are commented
|
||||
* out to optimized speed switching. Initialize loops_per_jiffy to 0.
|
||||
* out to optimized speed switching. Initalize loops_per_jiffy to 0.
|
||||
*
|
||||
* Table stepping up/down is optimized for 256mhz jumps while staying on the
|
||||
* same PLL.
|
||||
@@ -493,7 +494,7 @@ uint32_t acpuclk_get_switch_time(void)
|
||||
* Clock driver initialization
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
/* Initialize the lpj field in the acpu_freq_tbl. */
|
||||
/* Initalize the lpj field in the acpu_freq_tbl. */
|
||||
static void __init lpj_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
211
arch/arm/mach-msm/acpuclock-copper.c
Normal file
211
arch/arm/mach-msm/acpuclock-copper.c
Normal file
@@ -0,0 +1,211 @@
|
||||
/*
|
||||
* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <mach/rpm-regulator.h>
|
||||
#include <mach/msm_bus_board.h>
|
||||
#include <mach/msm_bus.h>
|
||||
#include <mach/socinfo.h>
|
||||
|
||||
#include "acpuclock.h"
|
||||
#include "acpuclock-krait.h"
|
||||
|
||||
/* Corner type vreg VDD values */
|
||||
#define LVL_NONE RPM_VREG_CORNER_NONE
|
||||
#define LVL_LOW RPM_VREG_CORNER_LOW
|
||||
#define LVL_NOM RPM_VREG_CORNER_NOMINAL
|
||||
#define LVL_HIGH RPM_VREG_CORNER_HIGH
|
||||
|
||||
static struct hfpll_data hfpll_data_cpu = {
|
||||
.mode_offset = 0x00,
|
||||
.l_offset = 0x04,
|
||||
.m_offset = 0x08,
|
||||
.n_offset = 0x0C,
|
||||
.config_offset = 0x14,
|
||||
/* TODO: Verify magic number for copper when available. */
|
||||
.config_val = 0x7845C665,
|
||||
.low_vdd_l_max = 52,
|
||||
.vdd[HFPLL_VDD_NONE] = 0,
|
||||
.vdd[HFPLL_VDD_LOW] = 810000,
|
||||
.vdd[HFPLL_VDD_NOM] = 900000,
|
||||
};
|
||||
|
||||
static struct hfpll_data hfpll_data_l2 = {
|
||||
.mode_offset = 0x00,
|
||||
.l_offset = 0x04,
|
||||
.m_offset = 0x08,
|
||||
.n_offset = 0x0C,
|
||||
.config_offset = 0x14,
|
||||
/* TODO: Verify magic number for copper when available. */
|
||||
.config_val = 0x7845C665,
|
||||
.low_vdd_l_max = 52,
|
||||
.vdd[HFPLL_VDD_NONE] = LVL_NONE,
|
||||
.vdd[HFPLL_VDD_LOW] = LVL_LOW,
|
||||
.vdd[HFPLL_VDD_NOM] = LVL_NOM,
|
||||
};
|
||||
|
||||
static struct scalable scalable[] = {
|
||||
[CPU0] = {
|
||||
.hfpll_phys_base = 0xF908A000,
|
||||
.hfpll_data = &hfpll_data_cpu,
|
||||
.l2cpmr_iaddr = 0x4501,
|
||||
.vreg[VREG_CORE] = { "krait0", 1050000, 3200000 },
|
||||
.vreg[VREG_MEM] = { "krait0_mem", 1050000, 0,
|
||||
RPM_VREG_VOTER1,
|
||||
RPM_VREG_ID_PM8941_S1 },
|
||||
.vreg[VREG_DIG] = { "krait0_dig", 1050000, 0,
|
||||
RPM_VREG_VOTER1,
|
||||
RPM_VREG_ID_PM8941_S2 },
|
||||
.vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
|
||||
RPM_VREG_VOTER1,
|
||||
RPM_VREG_ID_PM8941_L12 },
|
||||
},
|
||||
[CPU1] = {
|
||||
.hfpll_phys_base = 0xF909A000,
|
||||
.hfpll_data = &hfpll_data_cpu,
|
||||
.l2cpmr_iaddr = 0x5501,
|
||||
.vreg[VREG_CORE] = { "krait1", 1050000, 3200000 },
|
||||
.vreg[VREG_MEM] = { "krait1_mem", 1050000, 0,
|
||||
RPM_VREG_VOTER2,
|
||||
RPM_VREG_ID_PM8941_S1 },
|
||||
.vreg[VREG_DIG] = { "krait1_dig", 1050000, 0,
|
||||
RPM_VREG_VOTER2,
|
||||
RPM_VREG_ID_PM8941_S2 },
|
||||
.vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
|
||||
RPM_VREG_VOTER2,
|
||||
RPM_VREG_ID_PM8941_L12 },
|
||||
},
|
||||
[CPU2] = {
|
||||
.hfpll_phys_base = 0xF90AA000,
|
||||
.hfpll_data = &hfpll_data_cpu,
|
||||
.l2cpmr_iaddr = 0x6501,
|
||||
.vreg[VREG_CORE] = { "krait2", 1050000, 3200000 },
|
||||
.vreg[VREG_MEM] = { "krait2_mem", 1050000, 0,
|
||||
RPM_VREG_VOTER4,
|
||||
RPM_VREG_ID_PM8921_S1 },
|
||||
.vreg[VREG_DIG] = { "krait2_dig", 1050000, 0,
|
||||
RPM_VREG_VOTER4,
|
||||
RPM_VREG_ID_PM8921_S2 },
|
||||
.vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
|
||||
RPM_VREG_VOTER4,
|
||||
RPM_VREG_ID_PM8941_L12 },
|
||||
},
|
||||
[CPU3] = {
|
||||
.hfpll_phys_base = 0xF90BA000,
|
||||
.hfpll_data = &hfpll_data_cpu,
|
||||
.l2cpmr_iaddr = 0x7501,
|
||||
.vreg[VREG_CORE] = { "krait3", 1050000, 3200000 },
|
||||
.vreg[VREG_MEM] = { "krait3_mem", 1050000, 0,
|
||||
RPM_VREG_VOTER5,
|
||||
RPM_VREG_ID_PM8941_S1 },
|
||||
.vreg[VREG_DIG] = { "krait3_dig", 1050000, 0,
|
||||
RPM_VREG_VOTER5,
|
||||
RPM_VREG_ID_PM8941_S2 },
|
||||
.vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
|
||||
RPM_VREG_VOTER5,
|
||||
RPM_VREG_ID_PM8941_L12 },
|
||||
},
|
||||
[L2] = {
|
||||
.hfpll_phys_base = 0xF9016000,
|
||||
.hfpll_data = &hfpll_data_l2,
|
||||
.l2cpmr_iaddr = 0x0500,
|
||||
.vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
|
||||
RPM_VREG_VOTER6,
|
||||
RPM_VREG_ID_PM8941_L12 },
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_paths bw_level_tbl[] = {
|
||||
[0] = BW_MBPS(400), /* At least 50 MHz on bus. */
|
||||
[1] = BW_MBPS(800), /* At least 100 MHz on bus. */
|
||||
[2] = BW_MBPS(1334), /* At least 167 MHz on bus. */
|
||||
[3] = BW_MBPS(2666), /* At least 200 MHz on bus. */
|
||||
[4] = BW_MBPS(3200), /* At least 333 MHz on bus. */
|
||||
};
|
||||
|
||||
static struct msm_bus_scale_pdata bus_scale_data = {
|
||||
.usecase = bw_level_tbl,
|
||||
.num_usecases = ARRAY_SIZE(bw_level_tbl),
|
||||
.active_only = 1,
|
||||
.name = "acpuclk-copper",
|
||||
};
|
||||
|
||||
#define L2(x) (&l2_freq_tbl[(x)])
|
||||
static struct l2_level l2_freq_tbl[] = {
|
||||
[0] = { {STBY_KHZ, QSB, 0, 0, 0 }, LVL_NOM, 1050000, 0 },
|
||||
[1] = { { 300000, PLL_0, 0, 2, 0 }, LVL_NOM, 1050000, 2 },
|
||||
[2] = { { 384000, HFPLL, 2, 0, 40 }, LVL_NOM, 1050000, 2 },
|
||||
[3] = { { 460800, HFPLL, 2, 0, 48 }, LVL_NOM, 1050000, 2 },
|
||||
[4] = { { 537600, HFPLL, 1, 0, 28 }, LVL_NOM, 1050000, 2 },
|
||||
[5] = { { 576000, HFPLL, 1, 0, 30 }, LVL_NOM, 1050000, 3 },
|
||||
[6] = { { 652800, HFPLL, 1, 0, 34 }, LVL_NOM, 1050000, 3 },
|
||||
[7] = { { 729600, HFPLL, 1, 0, 38 }, LVL_NOM, 1050000, 3 },
|
||||
[8] = { { 806400, HFPLL, 1, 0, 42 }, LVL_NOM, 1050000, 3 },
|
||||
[9] = { { 883200, HFPLL, 1, 0, 46 }, LVL_NOM, 1050000, 4 },
|
||||
[10] = { { 960000, HFPLL, 1, 0, 50 }, LVL_NOM, 1050000, 4 },
|
||||
[11] = { { 1036800, HFPLL, 1, 0, 54 }, LVL_NOM, 1050000, 4 },
|
||||
};
|
||||
|
||||
static struct acpu_level acpu_freq_tbl[] = {
|
||||
{ 0, {STBY_KHZ, QSB, 0, 0, 0 }, L2(0), 1050000 },
|
||||
{ 1, { 300000, PLL_0, 0, 2, 0 }, L2(1), 1050000 },
|
||||
{ 1, { 384000, HFPLL, 2, 0, 40 }, L2(2), 1050000 },
|
||||
{ 1, { 460800, HFPLL, 2, 0, 48 }, L2(3), 1050000 },
|
||||
{ 1, { 537600, HFPLL, 1, 0, 28 }, L2(4), 1050000 },
|
||||
{ 1, { 576000, HFPLL, 1, 0, 30 }, L2(5), 1050000 },
|
||||
{ 1, { 652800, HFPLL, 1, 0, 34 }, L2(6), 1050000 },
|
||||
{ 1, { 729600, HFPLL, 1, 0, 38 }, L2(7), 1050000 },
|
||||
{ 1, { 806400, HFPLL, 1, 0, 42 }, L2(8), 1050000 },
|
||||
{ 1, { 883200, HFPLL, 1, 0, 46 }, L2(9), 1050000 },
|
||||
{ 1, { 960000, HFPLL, 1, 0, 50 }, L2(10), 1050000 },
|
||||
{ 1, { 1036800, HFPLL, 1, 0, 54 }, L2(11), 1050000 },
|
||||
{ 0, { 0 } }
|
||||
};
|
||||
|
||||
static struct acpuclk_krait_params acpuclk_copper_params = {
|
||||
.scalable = scalable,
|
||||
.pvs_acpu_freq_tbl[PVS_SLOW] = acpu_freq_tbl,
|
||||
.pvs_acpu_freq_tbl[PVS_NOMINAL] = acpu_freq_tbl,
|
||||
.pvs_acpu_freq_tbl[PVS_FAST] = acpu_freq_tbl,
|
||||
.l2_freq_tbl = l2_freq_tbl,
|
||||
.l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl),
|
||||
.bus_scale_data = &bus_scale_data,
|
||||
.qfprom_phys_base = 0xFC4A8000,
|
||||
};
|
||||
|
||||
static int __init acpuclk_copper_probe(struct platform_device *pdev)
|
||||
{
|
||||
return acpuclk_krait_init(&pdev->dev, &acpuclk_copper_params);
|
||||
}
|
||||
|
||||
static struct of_device_id acpuclk_copper_match_table[] = {
|
||||
{ .compatible = "qcom,acpuclk-copper" },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver acpuclk_copper_driver = {
|
||||
.driver = {
|
||||
.name = "acpuclk-copper",
|
||||
.of_match_table = acpuclk_copper_match_table,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init acpuclk_8960_init(void)
|
||||
{
|
||||
return platform_driver_probe(&acpuclk_copper_driver,
|
||||
acpuclk_copper_probe);
|
||||
}
|
||||
device_initcall(acpuclk_8960_init);
|
||||
52
arch/arm/mach-msm/acpuclock-fsm9xxx.c
Normal file
52
arch/arm/mach-msm/acpuclock-fsm9xxx.c
Normal file
@@ -0,0 +1,52 @@
|
||||
/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/board.h>
|
||||
|
||||
#include "acpuclock.h"
|
||||
|
||||
/* Registers */
|
||||
#define PLL1_CTL_ADDR (MSM_CLK_CTL_BASE + 0x604)
|
||||
|
||||
static unsigned long acpuclk_9xxx_get_rate(int cpu)
|
||||
{
|
||||
unsigned int pll1_ctl;
|
||||
unsigned int pll1_l, pll1_div2;
|
||||
unsigned int pll1_khz;
|
||||
|
||||
pll1_ctl = readl_relaxed(PLL1_CTL_ADDR);
|
||||
pll1_l = ((pll1_ctl >> 3) & 0x3f) * 2;
|
||||
pll1_div2 = pll1_ctl & 0x20000;
|
||||
pll1_khz = 19200 * pll1_l;
|
||||
if (pll1_div2)
|
||||
pll1_khz >>= 1;
|
||||
|
||||
return pll1_khz;
|
||||
}
|
||||
|
||||
static struct acpuclk_data acpuclk_9xxx_data = {
|
||||
.get_rate = acpuclk_9xxx_get_rate,
|
||||
};
|
||||
|
||||
static int __init acpuclk_9xxx_init(struct acpuclk_soc_data *soc_data)
|
||||
{
|
||||
acpuclk_register(&acpuclk_9xxx_data);
|
||||
pr_info("ACPU running at %lu KHz\n", acpuclk_get_rate(0));
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct acpuclk_soc_data acpuclk_9xxx_soc_data __initdata = {
|
||||
.init = acpuclk_9xxx_init,
|
||||
};
|
||||
784
arch/arm/mach-msm/acpuclock-krait.c
Normal file
784
arch/arm/mach-msm/acpuclock-krait.c
Normal file
@@ -0,0 +1,784 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/cpu.h>
|
||||
|
||||
#include <mach/board.h>
|
||||
#include <mach/msm_iomap.h>
|
||||
#include <mach/socinfo.h>
|
||||
#include <mach/msm-krait-l2-accessors.h>
|
||||
#include <mach/rpm-regulator.h>
|
||||
#include <mach/msm_bus.h>
|
||||
|
||||
#include "acpuclock.h"
|
||||
#include "acpuclock-krait.h"
|
||||
|
||||
/* MUX source selects. */
|
||||
#define PRI_SRC_SEL_SEC_SRC 0
|
||||
#define PRI_SRC_SEL_HFPLL 1
|
||||
#define PRI_SRC_SEL_HFPLL_DIV2 2
|
||||
#define SEC_SRC_SEL_QSB 0
|
||||
#define SEC_SRC_SEL_L2PLL 1
|
||||
#define SEC_SRC_SEL_AUX 2
|
||||
|
||||
/* PTE EFUSE register offset. */
|
||||
#define PTE_EFUSE 0xC0
|
||||
|
||||
static DEFINE_MUTEX(driver_lock);
|
||||
static DEFINE_SPINLOCK(l2_lock);
|
||||
|
||||
static struct drv_data {
|
||||
const struct acpu_level *acpu_freq_tbl;
|
||||
const struct l2_level *l2_freq_tbl;
|
||||
struct scalable *scalable;
|
||||
u32 bus_perf_client;
|
||||
struct device *dev;
|
||||
} drv;
|
||||
|
||||
static unsigned long acpuclk_krait_get_rate(int cpu)
|
||||
{
|
||||
return drv.scalable[cpu].cur_speed->khz;
|
||||
}
|
||||
|
||||
/* Select a source on the primary MUX. */
|
||||
static void set_pri_clk_src(struct scalable *sc, u32 pri_src_sel)
|
||||
{
|
||||
u32 regval;
|
||||
|
||||
regval = get_l2_indirect_reg(sc->l2cpmr_iaddr);
|
||||
regval &= ~0x3;
|
||||
regval |= (pri_src_sel & 0x3);
|
||||
set_l2_indirect_reg(sc->l2cpmr_iaddr, regval);
|
||||
/* Wait for switch to complete. */
|
||||
mb();
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
/* Select a source on the secondary MUX. */
|
||||
static void set_sec_clk_src(struct scalable *sc, u32 sec_src_sel)
|
||||
{
|
||||
u32 regval;
|
||||
|
||||
regval = get_l2_indirect_reg(sc->l2cpmr_iaddr);
|
||||
regval &= ~(0x3 << 2);
|
||||
regval |= ((sec_src_sel & 0x3) << 2);
|
||||
set_l2_indirect_reg(sc->l2cpmr_iaddr, regval);
|
||||
/* Wait for switch to complete. */
|
||||
mb();
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
/* Enable an already-configured HFPLL. */
|
||||
static void hfpll_enable(struct scalable *sc, bool skip_regulators)
|
||||
{
|
||||
int rc;
|
||||
|
||||
if (!skip_regulators) {
|
||||
/* Enable regulators required by the HFPLL. */
|
||||
if (sc->vreg[VREG_HFPLL_A].rpm_vreg_id) {
|
||||
rc = rpm_vreg_set_voltage(
|
||||
sc->vreg[VREG_HFPLL_A].rpm_vreg_id,
|
||||
sc->vreg[VREG_HFPLL_A].rpm_vreg_voter,
|
||||
sc->vreg[VREG_HFPLL_A].cur_vdd,
|
||||
sc->vreg[VREG_HFPLL_A].max_vdd, 0);
|
||||
if (rc)
|
||||
dev_err(drv.dev,
|
||||
"%s regulator enable failed (%d)\n",
|
||||
sc->vreg[VREG_HFPLL_A].name, rc);
|
||||
}
|
||||
if (sc->vreg[VREG_HFPLL_B].rpm_vreg_id) {
|
||||
rc = rpm_vreg_set_voltage(
|
||||
sc->vreg[VREG_HFPLL_B].rpm_vreg_id,
|
||||
sc->vreg[VREG_HFPLL_B].rpm_vreg_voter,
|
||||
sc->vreg[VREG_HFPLL_B].cur_vdd,
|
||||
sc->vreg[VREG_HFPLL_B].max_vdd, 0);
|
||||
if (rc)
|
||||
dev_err(drv.dev,
|
||||
"%s regulator enable failed (%d)\n",
|
||||
sc->vreg[VREG_HFPLL_B].name, rc);
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable PLL bypass mode. */
|
||||
writel_relaxed(0x2, sc->hfpll_base + sc->hfpll_data->mode_offset);
|
||||
|
||||
/*
|
||||
* H/W requires a 5us delay between disabling the bypass and
|
||||
* de-asserting the reset. Delay 10us just to be safe.
|
||||
*/
|
||||
mb();
|
||||
udelay(10);
|
||||
|
||||
/* De-assert active-low PLL reset. */
|
||||
writel_relaxed(0x6, sc->hfpll_base + sc->hfpll_data->mode_offset);
|
||||
|
||||
/* Wait for PLL to lock. */
|
||||
mb();
|
||||
udelay(60);
|
||||
|
||||
/* Enable PLL output. */
|
||||
writel_relaxed(0x7, sc->hfpll_base + sc->hfpll_data->mode_offset);
|
||||
}
|
||||
|
||||
/* Disable a HFPLL for power-savings or while it's being reprogrammed. */
|
||||
static void hfpll_disable(struct scalable *sc, bool skip_regulators)
|
||||
{
|
||||
int rc;
|
||||
|
||||
/*
|
||||
* Disable the PLL output, disable test mode, enable the bypass mode,
|
||||
* and assert the reset.
|
||||
*/
|
||||
writel_relaxed(0, sc->hfpll_base + sc->hfpll_data->mode_offset);
|
||||
|
||||
if (!skip_regulators) {
|
||||
/* Remove voltage votes required by the HFPLL. */
|
||||
if (sc->vreg[VREG_HFPLL_B].rpm_vreg_id) {
|
||||
rc = rpm_vreg_set_voltage(
|
||||
sc->vreg[VREG_HFPLL_B].rpm_vreg_id,
|
||||
sc->vreg[VREG_HFPLL_B].rpm_vreg_voter,
|
||||
0, 0, 0);
|
||||
if (rc)
|
||||
dev_err(drv.dev,
|
||||
"%s regulator enable failed (%d)\n",
|
||||
sc->vreg[VREG_HFPLL_B].name, rc);
|
||||
}
|
||||
if (sc->vreg[VREG_HFPLL_A].rpm_vreg_id) {
|
||||
rc = rpm_vreg_set_voltage(
|
||||
sc->vreg[VREG_HFPLL_A].rpm_vreg_id,
|
||||
sc->vreg[VREG_HFPLL_A].rpm_vreg_voter,
|
||||
0, 0, 0);
|
||||
if (rc)
|
||||
dev_err(drv.dev,
|
||||
"%s regulator enable failed (%d)\n",
|
||||
sc->vreg[VREG_HFPLL_A].name, rc);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Program the HFPLL rate. Assumes HFPLL is already disabled. */
|
||||
static void hfpll_set_rate(struct scalable *sc, const struct core_speed *tgt_s)
|
||||
{
|
||||
writel_relaxed(tgt_s->pll_l_val,
|
||||
sc->hfpll_base + sc->hfpll_data->l_offset);
|
||||
}
|
||||
|
||||
/* Return the L2 speed that should be applied. */
|
||||
static const struct l2_level *compute_l2_level(struct scalable *sc,
|
||||
const struct l2_level *vote_l)
|
||||
{
|
||||
const struct l2_level *new_l;
|
||||
int cpu;
|
||||
|
||||
/* Find max L2 speed vote. */
|
||||
sc->l2_vote = vote_l;
|
||||
new_l = drv.l2_freq_tbl;
|
||||
for_each_present_cpu(cpu)
|
||||
new_l = max(new_l, drv.scalable[cpu].l2_vote);
|
||||
|
||||
return new_l;
|
||||
}
|
||||
|
||||
/* Update the bus bandwidth request. */
|
||||
static void set_bus_bw(unsigned int bw)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Update bandwidth if request has changed. This may sleep. */
|
||||
ret = msm_bus_scale_client_update_request(drv.bus_perf_client, bw);
|
||||
if (ret)
|
||||
dev_err(drv.dev, "bandwidth request failed (%d)\n", ret);
|
||||
}
|
||||
|
||||
/* Set the CPU or L2 clock speed. */
|
||||
static void set_speed(struct scalable *sc, const struct core_speed *tgt_s)
|
||||
{
|
||||
const struct core_speed *strt_s = sc->cur_speed;
|
||||
|
||||
if (strt_s->src == HFPLL && tgt_s->src == HFPLL) {
|
||||
/*
|
||||
* Move to an always-on source running at a frequency
|
||||
* that does not require an elevated CPU voltage.
|
||||
*/
|
||||
set_sec_clk_src(sc, SEC_SRC_SEL_AUX);
|
||||
set_pri_clk_src(sc, PRI_SRC_SEL_SEC_SRC);
|
||||
|
||||
/* Re-program HFPLL. */
|
||||
hfpll_disable(sc, 1);
|
||||
hfpll_set_rate(sc, tgt_s);
|
||||
hfpll_enable(sc, 1);
|
||||
|
||||
/* Move to HFPLL. */
|
||||
set_pri_clk_src(sc, tgt_s->pri_src_sel);
|
||||
} else if (strt_s->src == HFPLL && tgt_s->src != HFPLL) {
|
||||
set_sec_clk_src(sc, tgt_s->sec_src_sel);
|
||||
set_pri_clk_src(sc, tgt_s->pri_src_sel);
|
||||
hfpll_disable(sc, 0);
|
||||
} else if (strt_s->src != HFPLL && tgt_s->src == HFPLL) {
|
||||
hfpll_set_rate(sc, tgt_s);
|
||||
hfpll_enable(sc, 0);
|
||||
set_pri_clk_src(sc, tgt_s->pri_src_sel);
|
||||
} else {
|
||||
set_sec_clk_src(sc, tgt_s->sec_src_sel);
|
||||
}
|
||||
|
||||
sc->cur_speed = tgt_s;
|
||||
}
|
||||
|
||||
/* Apply any per-cpu voltage increases. */
|
||||
static int increase_vdd(int cpu, int vdd_core, int vdd_mem, int vdd_dig,
|
||||
enum setrate_reason reason)
|
||||
{
|
||||
struct scalable *sc = &drv.scalable[cpu];
|
||||
int rc = 0;
|
||||
|
||||
/*
|
||||
* Increase vdd_mem active-set before vdd_dig.
|
||||
* vdd_mem should be >= vdd_dig.
|
||||
*/
|
||||
if (vdd_mem > sc->vreg[VREG_MEM].cur_vdd) {
|
||||
rc = rpm_vreg_set_voltage(sc->vreg[VREG_MEM].rpm_vreg_id,
|
||||
sc->vreg[VREG_MEM].rpm_vreg_voter, vdd_mem,
|
||||
sc->vreg[VREG_MEM].max_vdd, 0);
|
||||
if (rc) {
|
||||
dev_err(drv.dev,
|
||||
"vdd_mem (cpu%d) increase failed (%d)\n",
|
||||
cpu, rc);
|
||||
return rc;
|
||||
}
|
||||
sc->vreg[VREG_MEM].cur_vdd = vdd_mem;
|
||||
}
|
||||
|
||||
/* Increase vdd_dig active-set vote. */
|
||||
if (vdd_dig > sc->vreg[VREG_DIG].cur_vdd) {
|
||||
rc = rpm_vreg_set_voltage(sc->vreg[VREG_DIG].rpm_vreg_id,
|
||||
sc->vreg[VREG_DIG].rpm_vreg_voter, vdd_dig,
|
||||
sc->vreg[VREG_DIG].max_vdd, 0);
|
||||
if (rc) {
|
||||
dev_err(drv.dev,
|
||||
"vdd_dig (cpu%d) increase failed (%d)\n",
|
||||
cpu, rc);
|
||||
return rc;
|
||||
}
|
||||
sc->vreg[VREG_DIG].cur_vdd = vdd_dig;
|
||||
}
|
||||
|
||||
/*
|
||||
* Update per-CPU core voltage. Don't do this for the hotplug path for
|
||||
* which it should already be correct. Attempting to set it is bad
|
||||
* because we don't know what CPU we are running on at this point, but
|
||||
* the CPU regulator API requires we call it from the affected CPU.
|
||||
*/
|
||||
if (vdd_core > sc->vreg[VREG_CORE].cur_vdd
|
||||
&& reason != SETRATE_HOTPLUG) {
|
||||
rc = regulator_set_voltage(sc->vreg[VREG_CORE].reg, vdd_core,
|
||||
sc->vreg[VREG_CORE].max_vdd);
|
||||
if (rc) {
|
||||
dev_err(drv.dev,
|
||||
"vdd_core (cpu%d) increase failed (%d)\n",
|
||||
cpu, rc);
|
||||
return rc;
|
||||
}
|
||||
sc->vreg[VREG_CORE].cur_vdd = vdd_core;
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Apply any per-cpu voltage decreases. */
|
||||
static void decrease_vdd(int cpu, int vdd_core, int vdd_mem, int vdd_dig,
|
||||
enum setrate_reason reason)
|
||||
{
|
||||
struct scalable *sc = &drv.scalable[cpu];
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Update per-CPU core voltage. This must be called on the CPU
|
||||
* that's being affected. Don't do this in the hotplug remove path,
|
||||
* where the rail is off and we're executing on the other CPU.
|
||||
*/
|
||||
if (vdd_core < sc->vreg[VREG_CORE].cur_vdd
|
||||
&& reason != SETRATE_HOTPLUG) {
|
||||
ret = regulator_set_voltage(sc->vreg[VREG_CORE].reg, vdd_core,
|
||||
sc->vreg[VREG_CORE].max_vdd);
|
||||
if (ret) {
|
||||
dev_err(drv.dev,
|
||||
"vdd_core (cpu%d) decrease failed (%d)\n",
|
||||
cpu, ret);
|
||||
return;
|
||||
}
|
||||
sc->vreg[VREG_CORE].cur_vdd = vdd_core;
|
||||
}
|
||||
|
||||
/* Decrease vdd_dig active-set vote. */
|
||||
if (vdd_dig < sc->vreg[VREG_DIG].cur_vdd) {
|
||||
ret = rpm_vreg_set_voltage(sc->vreg[VREG_DIG].rpm_vreg_id,
|
||||
sc->vreg[VREG_DIG].rpm_vreg_voter, vdd_dig,
|
||||
sc->vreg[VREG_DIG].max_vdd, 0);
|
||||
if (ret) {
|
||||
dev_err(drv.dev,
|
||||
"vdd_dig (cpu%d) decrease failed (%d)\n",
|
||||
cpu, ret);
|
||||
return;
|
||||
}
|
||||
sc->vreg[VREG_DIG].cur_vdd = vdd_dig;
|
||||
}
|
||||
|
||||
/*
|
||||
* Decrease vdd_mem active-set after vdd_dig.
|
||||
* vdd_mem should be >= vdd_dig.
|
||||
*/
|
||||
if (vdd_mem < sc->vreg[VREG_MEM].cur_vdd) {
|
||||
ret = rpm_vreg_set_voltage(sc->vreg[VREG_MEM].rpm_vreg_id,
|
||||
sc->vreg[VREG_MEM].rpm_vreg_voter, vdd_mem,
|
||||
sc->vreg[VREG_MEM].max_vdd, 0);
|
||||
if (ret) {
|
||||
dev_err(drv.dev,
|
||||
"vdd_mem (cpu%d) decrease failed (%d)\n",
|
||||
cpu, ret);
|
||||
return;
|
||||
}
|
||||
sc->vreg[VREG_MEM].cur_vdd = vdd_mem;
|
||||
}
|
||||
}
|
||||
|
||||
static int calculate_vdd_mem(const struct acpu_level *tgt)
|
||||
{
|
||||
return tgt->l2_level->vdd_mem;
|
||||
}
|
||||
|
||||
static int calculate_vdd_dig(const struct acpu_level *tgt)
|
||||
{
|
||||
int pll_vdd_dig;
|
||||
const int *hfpll_vdd = drv.scalable[L2].hfpll_data->vdd;
|
||||
const u32 low_vdd_l_max = drv.scalable[L2].hfpll_data->low_vdd_l_max;
|
||||
|
||||
if (tgt->l2_level->speed.src != HFPLL)
|
||||
pll_vdd_dig = hfpll_vdd[HFPLL_VDD_NONE];
|
||||
else if (tgt->l2_level->speed.pll_l_val > low_vdd_l_max)
|
||||
pll_vdd_dig = hfpll_vdd[HFPLL_VDD_NOM];
|
||||
else
|
||||
pll_vdd_dig = hfpll_vdd[HFPLL_VDD_LOW];
|
||||
|
||||
return max(tgt->l2_level->vdd_dig, pll_vdd_dig);
|
||||
}
|
||||
|
||||
static int calculate_vdd_core(const struct acpu_level *tgt)
|
||||
{
|
||||
return tgt->vdd_core;
|
||||
}
|
||||
|
||||
/* Set the CPU's clock rate and adjust the L2 rate, voltage and BW requests. */
|
||||
static int acpuclk_krait_set_rate(int cpu, unsigned long rate,
|
||||
enum setrate_reason reason)
|
||||
{
|
||||
const struct core_speed *strt_acpu_s, *tgt_acpu_s;
|
||||
const struct l2_level *tgt_l2_l;
|
||||
const struct acpu_level *tgt;
|
||||
int vdd_mem, vdd_dig, vdd_core;
|
||||
unsigned long flags;
|
||||
int rc = 0;
|
||||
|
||||
if (cpu > num_possible_cpus()) {
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (reason == SETRATE_CPUFREQ || reason == SETRATE_HOTPLUG)
|
||||
mutex_lock(&driver_lock);
|
||||
|
||||
strt_acpu_s = drv.scalable[cpu].cur_speed;
|
||||
|
||||
/* Return early if rate didn't change. */
|
||||
if (rate == strt_acpu_s->khz)
|
||||
goto out;
|
||||
|
||||
/* Find target frequency. */
|
||||
for (tgt = drv.acpu_freq_tbl; tgt->speed.khz != 0; tgt++) {
|
||||
if (tgt->speed.khz == rate) {
|
||||
tgt_acpu_s = &tgt->speed;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (tgt->speed.khz == 0) {
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Calculate voltage requirements for the current CPU. */
|
||||
vdd_mem = calculate_vdd_mem(tgt);
|
||||
vdd_dig = calculate_vdd_dig(tgt);
|
||||
vdd_core = calculate_vdd_core(tgt);
|
||||
|
||||
/* Increase VDD levels if needed. */
|
||||
if (reason == SETRATE_CPUFREQ || reason == SETRATE_HOTPLUG) {
|
||||
rc = increase_vdd(cpu, vdd_core, vdd_mem, vdd_dig, reason);
|
||||
if (rc)
|
||||
goto out;
|
||||
}
|
||||
|
||||
pr_debug("Switching from ACPU%d rate %lu KHz -> %lu KHz\n",
|
||||
cpu, strt_acpu_s->khz, tgt_acpu_s->khz);
|
||||
|
||||
/* Set the new CPU speed. */
|
||||
set_speed(&drv.scalable[cpu], tgt_acpu_s);
|
||||
|
||||
/*
|
||||
* Update the L2 vote and apply the rate change. A spinlock is
|
||||
* necessary to ensure L2 rate is calculated and set atomically
|
||||
* with the CPU frequency, even if acpuclk_krait_set_rate() is
|
||||
* called from an atomic context and the driver_lock mutex is not
|
||||
* acquired.
|
||||
*/
|
||||
spin_lock_irqsave(&l2_lock, flags);
|
||||
tgt_l2_l = compute_l2_level(&drv.scalable[cpu], tgt->l2_level);
|
||||
set_speed(&drv.scalable[L2], &tgt_l2_l->speed);
|
||||
spin_unlock_irqrestore(&l2_lock, flags);
|
||||
|
||||
/* Nothing else to do for power collapse or SWFI. */
|
||||
if (reason == SETRATE_PC || reason == SETRATE_SWFI)
|
||||
goto out;
|
||||
|
||||
/* Update bus bandwith request. */
|
||||
set_bus_bw(tgt_l2_l->bw_level);
|
||||
|
||||
/* Drop VDD levels if we can. */
|
||||
decrease_vdd(cpu, vdd_core, vdd_mem, vdd_dig, reason);
|
||||
|
||||
pr_debug("ACPU%d speed change complete\n", cpu);
|
||||
|
||||
out:
|
||||
if (reason == SETRATE_CPUFREQ || reason == SETRATE_HOTPLUG)
|
||||
mutex_unlock(&driver_lock);
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Initialize a HFPLL at a given rate and enable it. */
|
||||
static void __init hfpll_init(struct scalable *sc,
|
||||
const struct core_speed *tgt_s)
|
||||
{
|
||||
pr_debug("Initializing HFPLL%d\n", sc - drv.scalable);
|
||||
|
||||
/* Disable the PLL for re-programming. */
|
||||
hfpll_disable(sc, 1);
|
||||
|
||||
/* Configure PLL parameters for integer mode. */
|
||||
writel_relaxed(sc->hfpll_data->config_val,
|
||||
sc->hfpll_base + sc->hfpll_data->config_offset);
|
||||
writel_relaxed(0, sc->hfpll_base + sc->hfpll_data->m_offset);
|
||||
writel_relaxed(1, sc->hfpll_base + sc->hfpll_data->n_offset);
|
||||
|
||||
/* Set an initial rate and enable the PLL. */
|
||||
hfpll_set_rate(sc, tgt_s);
|
||||
hfpll_enable(sc, 0);
|
||||
}
|
||||
|
||||
/* Voltage regulator initialization. */
|
||||
static void __init regulator_init(const struct acpu_level *lvl)
|
||||
{
|
||||
int cpu, ret;
|
||||
struct scalable *sc;
|
||||
int vdd_mem, vdd_dig, vdd_core;
|
||||
|
||||
vdd_mem = calculate_vdd_mem(lvl);
|
||||
vdd_dig = calculate_vdd_dig(lvl);
|
||||
|
||||
for_each_possible_cpu(cpu) {
|
||||
sc = &drv.scalable[cpu];
|
||||
|
||||
/* Set initial vdd_mem vote. */
|
||||
ret = rpm_vreg_set_voltage(sc->vreg[VREG_MEM].rpm_vreg_id,
|
||||
sc->vreg[VREG_MEM].rpm_vreg_voter, vdd_mem,
|
||||
sc->vreg[VREG_MEM].max_vdd, 0);
|
||||
if (ret) {
|
||||
dev_err(drv.dev, "%s initialization failed (%d)\n",
|
||||
sc->vreg[VREG_MEM].name, ret);
|
||||
BUG();
|
||||
}
|
||||
sc->vreg[VREG_MEM].cur_vdd = vdd_mem;
|
||||
|
||||
/* Set initial vdd_dig vote. */
|
||||
ret = rpm_vreg_set_voltage(sc->vreg[VREG_DIG].rpm_vreg_id,
|
||||
sc->vreg[VREG_DIG].rpm_vreg_voter, vdd_dig,
|
||||
sc->vreg[VREG_DIG].max_vdd, 0);
|
||||
if (ret) {
|
||||
dev_err(drv.dev, "%s initialization failed (%d)\n",
|
||||
sc->vreg[VREG_DIG].name, ret);
|
||||
BUG();
|
||||
}
|
||||
sc->vreg[VREG_DIG].cur_vdd = vdd_dig;
|
||||
|
||||
/* Setup Krait CPU regulators and initial core voltage. */
|
||||
sc->vreg[VREG_CORE].reg = regulator_get(NULL,
|
||||
sc->vreg[VREG_CORE].name);
|
||||
if (IS_ERR(sc->vreg[VREG_CORE].reg)) {
|
||||
dev_err(drv.dev, "regulator_get(%s) failed (%ld)\n",
|
||||
sc->vreg[VREG_CORE].name,
|
||||
PTR_ERR(sc->vreg[VREG_CORE].reg));
|
||||
BUG();
|
||||
}
|
||||
vdd_core = calculate_vdd_core(lvl);
|
||||
ret = regulator_set_voltage(sc->vreg[VREG_CORE].reg, vdd_core,
|
||||
sc->vreg[VREG_CORE].max_vdd);
|
||||
if (ret) {
|
||||
dev_err(drv.dev, "regulator_set_voltage(%s) (%d)\n",
|
||||
sc->vreg[VREG_CORE].name, ret);
|
||||
BUG();
|
||||
}
|
||||
sc->vreg[VREG_CORE].cur_vdd = vdd_core;
|
||||
ret = regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg,
|
||||
sc->vreg[VREG_CORE].peak_ua);
|
||||
if (ret < 0) {
|
||||
dev_err(drv.dev, "regulator_set_optimum_mode(%s) failed"
|
||||
" (%d)\n", sc->vreg[VREG_CORE].name, ret);
|
||||
BUG();
|
||||
}
|
||||
ret = regulator_enable(sc->vreg[VREG_CORE].reg);
|
||||
if (ret) {
|
||||
dev_err(drv.dev, "regulator_enable(%s) failed (%d)\n",
|
||||
sc->vreg[VREG_CORE].name, ret);
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Set initial rate for a given core. */
|
||||
static void __init init_clock_sources(struct scalable *sc,
|
||||
const struct core_speed *tgt_s)
|
||||
{
|
||||
u32 regval;
|
||||
|
||||
/* Program AUX source input to the secondary MUX. */
|
||||
if (sc->aux_clk_sel_addr)
|
||||
writel_relaxed(sc->aux_clk_sel, sc->aux_clk_sel_addr);
|
||||
|
||||
/* Switch away from the HFPLL while it's re-initialized. */
|
||||
set_sec_clk_src(sc, SEC_SRC_SEL_AUX);
|
||||
set_pri_clk_src(sc, PRI_SRC_SEL_SEC_SRC);
|
||||
hfpll_init(sc, tgt_s);
|
||||
|
||||
/* Set PRI_SRC_SEL_HFPLL_DIV2 divider to div-2. */
|
||||
regval = get_l2_indirect_reg(sc->l2cpmr_iaddr);
|
||||
regval &= ~(0x3 << 6);
|
||||
set_l2_indirect_reg(sc->l2cpmr_iaddr, regval);
|
||||
|
||||
/* Switch to the target clock source. */
|
||||
set_sec_clk_src(sc, tgt_s->sec_src_sel);
|
||||
set_pri_clk_src(sc, tgt_s->pri_src_sel);
|
||||
sc->cur_speed = tgt_s;
|
||||
}
|
||||
|
||||
static void __init per_cpu_init(int cpu, const struct acpu_level *max_level)
|
||||
{
|
||||
drv.scalable[cpu].hfpll_base =
|
||||
ioremap(drv.scalable[cpu].hfpll_phys_base, SZ_32);
|
||||
BUG_ON(!drv.scalable[cpu].hfpll_base);
|
||||
|
||||
init_clock_sources(&drv.scalable[cpu], &max_level->speed);
|
||||
drv.scalable[cpu].l2_vote = max_level->l2_level;
|
||||
}
|
||||
|
||||
/* Register with bus driver. */
|
||||
static void __init bus_init(struct msm_bus_scale_pdata *bus_scale_data,
|
||||
unsigned int init_bw)
|
||||
{
|
||||
int ret;
|
||||
|
||||
drv.bus_perf_client = msm_bus_scale_register_client(bus_scale_data);
|
||||
if (!drv.bus_perf_client) {
|
||||
dev_err(drv.dev, "unable to register bus client\n");
|
||||
BUG();
|
||||
}
|
||||
|
||||
ret = msm_bus_scale_client_update_request(drv.bus_perf_client, init_bw);
|
||||
if (ret)
|
||||
dev_err(drv.dev, "initial bandwidth req failed (%d)\n", ret);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ_MSM
|
||||
static struct cpufreq_frequency_table freq_table[NR_CPUS][35];
|
||||
|
||||
static void __init cpufreq_table_init(void)
|
||||
{
|
||||
int cpu;
|
||||
|
||||
for_each_possible_cpu(cpu) {
|
||||
int i, freq_cnt = 0;
|
||||
/* Construct the freq_table tables from acpu_freq_tbl. */
|
||||
for (i = 0; drv.acpu_freq_tbl[i].speed.khz != 0
|
||||
&& freq_cnt < ARRAY_SIZE(*freq_table); i++) {
|
||||
if (drv.acpu_freq_tbl[i].use_for_scaling) {
|
||||
freq_table[cpu][freq_cnt].index = freq_cnt;
|
||||
freq_table[cpu][freq_cnt].frequency
|
||||
= drv.acpu_freq_tbl[i].speed.khz;
|
||||
freq_cnt++;
|
||||
}
|
||||
}
|
||||
/* freq_table not big enough to store all usable freqs. */
|
||||
BUG_ON(drv.acpu_freq_tbl[i].speed.khz != 0);
|
||||
|
||||
freq_table[cpu][freq_cnt].index = freq_cnt;
|
||||
freq_table[cpu][freq_cnt].frequency = CPUFREQ_TABLE_END;
|
||||
|
||||
dev_info(drv.dev, "CPU%d: %d frequencies supported\n",
|
||||
cpu, freq_cnt);
|
||||
|
||||
/* Register table with CPUFreq. */
|
||||
cpufreq_frequency_table_get_attr(freq_table[cpu], cpu);
|
||||
}
|
||||
}
|
||||
#else
|
||||
static void __init cpufreq_table_init(void) {}
|
||||
#endif
|
||||
|
||||
#define HOT_UNPLUG_KHZ STBY_KHZ
|
||||
static int __cpuinit acpuclk_cpu_callback(struct notifier_block *nfb,
|
||||
unsigned long action, void *hcpu)
|
||||
{
|
||||
static int prev_khz[NR_CPUS];
|
||||
int rc, cpu = (int)hcpu;
|
||||
struct scalable *sc = &drv.scalable[cpu];
|
||||
|
||||
switch (action & ~CPU_TASKS_FROZEN) {
|
||||
case CPU_DEAD:
|
||||
prev_khz[cpu] = acpuclk_krait_get_rate(cpu);
|
||||
/* Fall through. */
|
||||
case CPU_UP_CANCELED:
|
||||
acpuclk_krait_set_rate(cpu, HOT_UNPLUG_KHZ, SETRATE_HOTPLUG);
|
||||
regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg, 0);
|
||||
break;
|
||||
case CPU_UP_PREPARE:
|
||||
if (WARN_ON(!prev_khz[cpu]))
|
||||
return NOTIFY_BAD;
|
||||
rc = regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg,
|
||||
sc->vreg[VREG_CORE].peak_ua);
|
||||
if (rc < 0)
|
||||
return NOTIFY_BAD;
|
||||
acpuclk_krait_set_rate(cpu, prev_khz[cpu], SETRATE_HOTPLUG);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
static struct notifier_block __cpuinitdata acpuclk_cpu_notifier = {
|
||||
.notifier_call = acpuclk_cpu_callback,
|
||||
};
|
||||
|
||||
static const struct acpu_level __init *select_freq_plan(
|
||||
const struct acpu_level *const *pvs_tbl, u32 qfprom_phys)
|
||||
{
|
||||
const struct acpu_level *l, *max_acpu_level = NULL;
|
||||
void __iomem *qfprom_base;
|
||||
u32 pte_efuse, pvs, tbl_idx;
|
||||
char *pvs_names[] = { "Slow", "Nominal", "Fast", "Unknown" };
|
||||
|
||||
qfprom_base = ioremap(qfprom_phys, SZ_256);
|
||||
/* Select frequency tables. */
|
||||
if (qfprom_base) {
|
||||
pte_efuse = readl_relaxed(qfprom_base + PTE_EFUSE);
|
||||
pvs = (pte_efuse >> 10) & 0x7;
|
||||
iounmap(qfprom_base);
|
||||
if (pvs == 0x7)
|
||||
pvs = (pte_efuse >> 13) & 0x7;
|
||||
|
||||
switch (pvs) {
|
||||
case 0x0:
|
||||
case 0x7:
|
||||
tbl_idx = PVS_SLOW;
|
||||
break;
|
||||
case 0x1:
|
||||
tbl_idx = PVS_NOMINAL;
|
||||
break;
|
||||
case 0x3:
|
||||
tbl_idx = PVS_FAST;
|
||||
break;
|
||||
default:
|
||||
tbl_idx = PVS_UNKNOWN;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
tbl_idx = PVS_UNKNOWN;
|
||||
dev_err(drv.dev, "Unable to map QFPROM base\n");
|
||||
}
|
||||
dev_info(drv.dev, "ACPU PVS: %s\n", pvs_names[tbl_idx]);
|
||||
if (tbl_idx == PVS_UNKNOWN) {
|
||||
tbl_idx = PVS_SLOW;
|
||||
dev_warn(drv.dev, "ACPU PVS: Defaulting to %s\n",
|
||||
pvs_names[tbl_idx]);
|
||||
}
|
||||
drv.acpu_freq_tbl = pvs_tbl[tbl_idx];
|
||||
|
||||
/* Find the max supported scaling frequency. */
|
||||
for (l = drv.acpu_freq_tbl; l->speed.khz != 0; l++)
|
||||
if (l->use_for_scaling)
|
||||
max_acpu_level = l;
|
||||
BUG_ON(!max_acpu_level);
|
||||
dev_info(drv.dev, "Max ACPU freq: %lu KHz\n",
|
||||
max_acpu_level->speed.khz);
|
||||
|
||||
return max_acpu_level;
|
||||
}
|
||||
|
||||
static struct acpuclk_data acpuclk_krait_data = {
|
||||
.set_rate = acpuclk_krait_set_rate,
|
||||
.get_rate = acpuclk_krait_get_rate,
|
||||
.power_collapse_khz = STBY_KHZ,
|
||||
.wait_for_irq_khz = STBY_KHZ,
|
||||
};
|
||||
|
||||
int __init acpuclk_krait_init(struct device *dev,
|
||||
const struct acpuclk_krait_params *params)
|
||||
{
|
||||
const struct acpu_level *max_acpu_level;
|
||||
int cpu;
|
||||
|
||||
drv.scalable = params->scalable;
|
||||
drv.l2_freq_tbl = params->l2_freq_tbl;
|
||||
drv.dev = dev;
|
||||
|
||||
drv.scalable[L2].hfpll_base =
|
||||
ioremap(drv.scalable[L2].hfpll_phys_base, SZ_32);
|
||||
BUG_ON(!drv.scalable[L2].hfpll_base);
|
||||
|
||||
max_acpu_level = select_freq_plan(params->pvs_acpu_freq_tbl,
|
||||
params->qfprom_phys_base);
|
||||
regulator_init(max_acpu_level);
|
||||
bus_init(params->bus_scale_data, max_acpu_level->l2_level->bw_level);
|
||||
init_clock_sources(&drv.scalable[L2], &max_acpu_level->l2_level->speed);
|
||||
for_each_online_cpu(cpu)
|
||||
per_cpu_init(cpu, max_acpu_level);
|
||||
|
||||
cpufreq_table_init();
|
||||
|
||||
acpuclk_register(&acpuclk_krait_data);
|
||||
register_hotcpu_notifier(&acpuclk_cpu_notifier);
|
||||
|
||||
return 0;
|
||||
}
|
||||
222
arch/arm/mach-msm/acpuclock-krait.h
Normal file
222
arch/arm/mach-msm/acpuclock-krait.h
Normal file
@@ -0,0 +1,222 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_KRAIT_H
|
||||
#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_KRAIT_H
|
||||
|
||||
#define STBY_KHZ 1
|
||||
|
||||
#define BW_MBPS(_bw) \
|
||||
{ \
|
||||
.vectors = (struct msm_bus_vectors[]){ \
|
||||
{\
|
||||
.src = MSM_BUS_MASTER_AMPSS_M0, \
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0, \
|
||||
.ib = (_bw) * 1000000UL, \
|
||||
}, \
|
||||
{ \
|
||||
.src = MSM_BUS_MASTER_AMPSS_M1, \
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0, \
|
||||
.ib = (_bw) * 1000000UL, \
|
||||
}, \
|
||||
}, \
|
||||
.num_paths = 2, \
|
||||
}
|
||||
|
||||
/**
|
||||
* src_id - Clock source IDs.
|
||||
*/
|
||||
enum src_id {
|
||||
PLL_0 = 0,
|
||||
HFPLL,
|
||||
QSB,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum pvs - IDs to distinguish between CPU frequency tables.
|
||||
*/
|
||||
enum pvs {
|
||||
PVS_SLOW = 0,
|
||||
PVS_NOMINAL,
|
||||
PVS_FAST,
|
||||
PVS_UNKNOWN,
|
||||
NUM_PVS
|
||||
};
|
||||
|
||||
/**
|
||||
* enum scalables - IDs of frequency scalable hardware blocks.
|
||||
*/
|
||||
enum scalables {
|
||||
CPU0 = 0,
|
||||
CPU1,
|
||||
CPU2,
|
||||
CPU3,
|
||||
L2,
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* enum hfpll_vdd_level - IDs of HFPLL voltage levels.
|
||||
*/
|
||||
enum hfpll_vdd_levels {
|
||||
HFPLL_VDD_NONE,
|
||||
HFPLL_VDD_LOW,
|
||||
HFPLL_VDD_NOM,
|
||||
NUM_HFPLL_VDD
|
||||
};
|
||||
|
||||
/**
|
||||
* enum vregs - IDs of voltage regulators.
|
||||
*/
|
||||
enum vregs {
|
||||
VREG_CORE,
|
||||
VREG_MEM,
|
||||
VREG_DIG,
|
||||
VREG_HFPLL_A,
|
||||
VREG_HFPLL_B,
|
||||
NUM_VREG
|
||||
};
|
||||
|
||||
/**
|
||||
* struct vreg - Voltage regulator data.
|
||||
* @name: Name of requlator.
|
||||
* @max_vdd: Limit the maximum-settable voltage.
|
||||
* @rpm_vreg_id: ID to use with rpm_vreg_*() APIs.
|
||||
* @reg: Regulator handle.
|
||||
* @cur_vdd: Last-set voltage in uV.
|
||||
* @peak_ua: Maximum current draw expected in uA.
|
||||
*/
|
||||
struct vreg {
|
||||
const char name[15];
|
||||
const int max_vdd;
|
||||
const int peak_ua;
|
||||
const int rpm_vreg_voter;
|
||||
const int rpm_vreg_id;
|
||||
struct regulator *reg;
|
||||
int cur_vdd;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct core_speed - Clock tree and configuration parameters.
|
||||
* @khz: Clock rate in KHz.
|
||||
* @src: Clock source ID.
|
||||
* @pri_src_sel: Input to select on the primary MUX.
|
||||
* @sec_src_sel: Input to select on the secondary MUX.
|
||||
* @pll_l_val: HFPLL "L" value to be applied when an HFPLL source is selected.
|
||||
*/
|
||||
struct core_speed {
|
||||
const unsigned long khz;
|
||||
const int src;
|
||||
const u32 pri_src_sel;
|
||||
const u32 sec_src_sel;
|
||||
const u32 pll_l_val;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct l2_level - L2 clock rate and associated voltage and b/w requirements.
|
||||
* @speed: L2 clock configuration.
|
||||
* @vdd_dig: vdd_dig voltage in uV.
|
||||
* @vdd_mem: vdd_mem voltage in uV.
|
||||
* @bw_level: Bandwidth performance level number.
|
||||
*/
|
||||
struct l2_level {
|
||||
const struct core_speed speed;
|
||||
const int vdd_dig;
|
||||
const int vdd_mem;
|
||||
const unsigned int bw_level;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct acpu_level - CPU clock rate and L2 rate and voltage requirements.
|
||||
* @use_for_scaling: Flag indicating whether or not the level should be used.
|
||||
* @speed: CPU clock configuration.
|
||||
* @l2_level: L2 configuration to use.
|
||||
* @vdd_core: CPU core voltage in uV.
|
||||
*/
|
||||
struct acpu_level {
|
||||
const int use_for_scaling;
|
||||
const struct core_speed speed;
|
||||
const struct l2_level *l2_level;
|
||||
const int vdd_core;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct hfpll_data - Descriptive data of HFPLL hardware.
|
||||
* @mode_offset: Mode register offset from base address.
|
||||
* @l_offset: "L" value register offset from base address.
|
||||
* @m_offset: "M" value register offset from base address.
|
||||
* @n_offset: "N" value register offset from base address.
|
||||
* @config_offset: Configuration register offset from base address.
|
||||
* @config_val: Value to initialize the @config_offset register to.
|
||||
* @vdd: voltage requirements for each VDD level.
|
||||
*/
|
||||
struct hfpll_data {
|
||||
const u32 mode_offset;
|
||||
const u32 l_offset;
|
||||
const u32 m_offset;
|
||||
const u32 n_offset;
|
||||
const u32 config_offset;
|
||||
const u32 config_val;
|
||||
const u32 low_vdd_l_max;
|
||||
const int vdd[NUM_HFPLL_VDD];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct scalable - Register locations and state associated with a scalable HW.
|
||||
* @hfpll_phys_base: Physical base address of HFPLL register.
|
||||
* @hfpll_base: Virtual base address of HFPLL registers.
|
||||
* @aux_clk_sel_addr: Virtual address of auxiliary MUX.
|
||||
* @aux_clk_sel: Auxiliary mux input to select at boot.
|
||||
* @l2cpmr_iaddr: Indirect address of the CPMR MUX/divider CP15 register.
|
||||
* @hfpll_data: Descriptive data of HFPLL hardware.
|
||||
* @cur_speed: Pointer to currently-set speed.
|
||||
* @l2_vote: L2 performance level vote associate with the current CPU speed.
|
||||
* @vreg: Array of voltage regulators needed by the scalable.
|
||||
*/
|
||||
struct scalable {
|
||||
const u32 hfpll_phys_base;
|
||||
void __iomem *hfpll_base;
|
||||
void __iomem *aux_clk_sel_addr;
|
||||
const u32 aux_clk_sel;
|
||||
const u32 l2cpmr_iaddr;
|
||||
const struct hfpll_data *hfpll_data;
|
||||
const struct core_speed *cur_speed;
|
||||
const struct l2_level *l2_vote;
|
||||
struct vreg vreg[NUM_VREG];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct acpuclk_krait_params - SoC specific driver parameters.
|
||||
* @scalable: Array of scalables.
|
||||
* @pvs_acpu_freq_tbl: Array of CPU frequency tables.
|
||||
* @l2_freq_tbl: L2 frequency table.
|
||||
* @l2_freq_tbl_size: Number of rows in @l2_freq_tbl.
|
||||
* @qfprom_phys_base: Physical base address of QFPROM.
|
||||
* @bus_scale_data: MSM bus driver parameters.
|
||||
*/
|
||||
struct acpuclk_krait_params {
|
||||
struct scalable *scalable;
|
||||
const struct acpu_level *pvs_acpu_freq_tbl[NUM_PVS];
|
||||
const struct l2_level *l2_freq_tbl;
|
||||
const size_t l2_freq_tbl_size;
|
||||
const u32 qfprom_phys_base;
|
||||
struct msm_bus_scale_pdata *bus_scale_data;
|
||||
};
|
||||
|
||||
/**
|
||||
* acpuclk_krait_init - Initialize the Krait CPU clock driver give SoC params.
|
||||
*/
|
||||
extern int acpuclk_krait_init(struct device *dev,
|
||||
const struct acpuclk_krait_params *params);
|
||||
|
||||
#endif
|
||||
76
arch/arm/mach-msm/acpuclock.c
Normal file
76
arch/arm/mach-msm/acpuclock.c
Normal file
@@ -0,0 +1,76 @@
|
||||
/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/smp.h>
|
||||
#include "acpuclock.h"
|
||||
|
||||
static struct acpuclk_data *acpuclk_data;
|
||||
|
||||
unsigned long acpuclk_get_rate(int cpu)
|
||||
{
|
||||
if (!acpuclk_data->get_rate)
|
||||
return 0;
|
||||
|
||||
return acpuclk_data->get_rate(cpu);
|
||||
}
|
||||
|
||||
int acpuclk_set_rate(int cpu, unsigned long rate, enum setrate_reason reason)
|
||||
{
|
||||
if (!acpuclk_data->set_rate)
|
||||
return 0;
|
||||
|
||||
return acpuclk_data->set_rate(cpu, rate, reason);
|
||||
}
|
||||
|
||||
uint32_t acpuclk_get_switch_time(void)
|
||||
{
|
||||
return acpuclk_data->switch_time_us;
|
||||
}
|
||||
|
||||
unsigned long acpuclk_power_collapse(void)
|
||||
{
|
||||
unsigned long rate = acpuclk_get_rate(smp_processor_id());
|
||||
acpuclk_set_rate(smp_processor_id(), acpuclk_data->power_collapse_khz,
|
||||
SETRATE_PC);
|
||||
return rate;
|
||||
}
|
||||
|
||||
unsigned long acpuclk_wait_for_irq(void)
|
||||
{
|
||||
unsigned long rate = acpuclk_get_rate(smp_processor_id());
|
||||
acpuclk_set_rate(smp_processor_id(), acpuclk_data->wait_for_irq_khz,
|
||||
SETRATE_SWFI);
|
||||
return rate;
|
||||
}
|
||||
|
||||
void __init acpuclk_register(struct acpuclk_data *data)
|
||||
{
|
||||
acpuclk_data = data;
|
||||
}
|
||||
|
||||
int __init acpuclk_init(struct acpuclk_soc_data *soc_data)
|
||||
{
|
||||
int rc;
|
||||
|
||||
if (!soc_data->init)
|
||||
return -EINVAL;
|
||||
|
||||
rc = soc_data->init(soc_data);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
if (!acpuclk_data)
|
||||
return -ENODEV;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,9 +1,8 @@
|
||||
/* arch/arm/mach-msm/acpuclock.h
|
||||
*
|
||||
* MSM architecture clock driver header
|
||||
/*
|
||||
* MSM architecture CPU clock driver header
|
||||
*
|
||||
* Copyright (C) 2007 Google, Inc.
|
||||
* Copyright (c) 2007 QUALCOMM Incorporated
|
||||
* Copyright (c) 2007-2012, Code Aurora Forum. All rights reserved.
|
||||
* Author: San Mehat <san@android.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
@@ -20,13 +19,97 @@
|
||||
#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
|
||||
#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
|
||||
|
||||
int acpuclk_set_rate(unsigned long rate, int for_power_collapse);
|
||||
unsigned long acpuclk_get_rate(void);
|
||||
uint32_t acpuclk_get_switch_time(void);
|
||||
unsigned long acpuclk_wait_for_irq(void);
|
||||
unsigned long acpuclk_power_collapse(void);
|
||||
unsigned long acpuclk_get_wfi_rate(void);
|
||||
/**
|
||||
* enum setrate_reason - Reasons for use with acpuclk_set_rate()
|
||||
*/
|
||||
enum setrate_reason {
|
||||
SETRATE_CPUFREQ = 0,
|
||||
SETRATE_SWFI,
|
||||
SETRATE_PC,
|
||||
SETRATE_HOTPLUG,
|
||||
SETRATE_INIT,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct acpuclk_soc_data - SoC data for acpuclk_init()
|
||||
*/
|
||||
struct acpuclk_soc_data {
|
||||
unsigned long max_speed_delta_khz;
|
||||
unsigned int max_axi_khz;
|
||||
int (*init)(struct acpuclk_soc_data *);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct acpuclk_data - Function pointers and data for function implementations
|
||||
*/
|
||||
struct acpuclk_data {
|
||||
unsigned long (*get_rate)(int cpu);
|
||||
int (*set_rate)(int cpu, unsigned long rate, enum setrate_reason);
|
||||
uint32_t switch_time_us;
|
||||
unsigned long power_collapse_khz;
|
||||
unsigned long wait_for_irq_khz;
|
||||
};
|
||||
|
||||
/**
|
||||
* acpulock_get_rate() - Get a CPU's clock rate in KHz
|
||||
* @cpu: CPU to query the rate of
|
||||
*/
|
||||
unsigned long acpuclk_get_rate(int cpu);
|
||||
|
||||
/**
|
||||
* acpuclk_set_rate() - Set a CPU's clock rate
|
||||
* @cpu: CPU to set rate of
|
||||
* @rate: Desired rate in KHz
|
||||
* @setrate_reason: Reason for the rate switch
|
||||
*
|
||||
* Returns 0 for success.
|
||||
*/
|
||||
int acpuclk_set_rate(int cpu, unsigned long rate, enum setrate_reason);
|
||||
|
||||
/**
|
||||
* acpuclk_get_switch_time() - Query estimated time in us for a CPU rate switch
|
||||
*/
|
||||
uint32_t acpuclk_get_switch_time(void);
|
||||
|
||||
/**
|
||||
* acpuclk_power_collapse() - Prepare current CPU clocks for power-collapse
|
||||
*
|
||||
* Returns the previous rate of the CPU in KHz.
|
||||
*/
|
||||
unsigned long acpuclk_power_collapse(void);
|
||||
|
||||
/**
|
||||
* acpuclk_wait_for_irq() - Prepare current CPU clocks for SWFI
|
||||
*
|
||||
* Returns the previous rate of the CPU in KHz.
|
||||
*/
|
||||
unsigned long acpuclk_wait_for_irq(void);
|
||||
|
||||
/**
|
||||
* acpuclk_register() - Register acpuclk_data function implementations
|
||||
* @data: acpuclock API implementations and data
|
||||
*/
|
||||
void acpuclk_register(struct acpuclk_data *data);
|
||||
|
||||
/**
|
||||
* acpuclk_init() - acpuclock driver initialization function
|
||||
*
|
||||
* Return 0 for success.
|
||||
*/
|
||||
int acpuclk_init(struct acpuclk_soc_data *);
|
||||
|
||||
/* SoC-specific acpuclock initialization functions. */
|
||||
extern struct acpuclk_soc_data acpuclk_7x27_soc_data;
|
||||
extern struct acpuclk_soc_data acpuclk_7x27a_soc_data;
|
||||
extern struct acpuclk_soc_data acpuclk_7x27aa_soc_data;
|
||||
extern struct acpuclk_soc_data acpuclk_7x30_soc_data;
|
||||
extern struct acpuclk_soc_data acpuclk_8x50_soc_data;
|
||||
extern struct acpuclk_soc_data acpuclk_8x60_soc_data;
|
||||
extern struct acpuclk_soc_data acpuclk_8960_soc_data;
|
||||
extern struct acpuclk_soc_data acpuclk_9xxx_soc_data;
|
||||
extern struct acpuclk_soc_data acpuclk_9615_soc_data;
|
||||
extern struct acpuclk_soc_data acpuclk_8930_soc_data;
|
||||
extern struct acpuclk_soc_data acpuclk_8064_soc_data;
|
||||
extern struct acpuclk_soc_data acpuclk_8625_soc_data;
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
483
arch/arm/mach-msm/arch-init-scorpion.S
Normal file
483
arch/arm/mach-msm/arch-init-scorpion.S
Normal file
@@ -0,0 +1,483 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
|
||||
* Copyright (c) 2008-2009, Google Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Google, Inc. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
/* TODO:
|
||||
* - style cleanup
|
||||
* - do we need to do *all* of this at boot?
|
||||
*/
|
||||
|
||||
.text
|
||||
.code 32
|
||||
|
||||
#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
|
||||
#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
|
||||
|
||||
.equ TCSR_SPARE2, 0xA8700060
|
||||
|
||||
SET_SA:
|
||||
ldr r0, =TCSR_SPARE2
|
||||
ldr r12, [r0]
|
||||
|
||||
/* pack bits 8,2,0 into 2,1,0 */
|
||||
and r0, r12, #0x001
|
||||
and r1, r12, #0x004
|
||||
and r2, r12, #0x100
|
||||
orr r0, r1, lsr #1
|
||||
orr r0, r2, lsr #6
|
||||
|
||||
adr r1, table_l1_acc
|
||||
mov r0, r0, lsl #2
|
||||
ldr r3, [r1, r0]
|
||||
|
||||
/* write 3800XXXX to PVR0F0 */
|
||||
orr r0, r3, #0x38000000
|
||||
mcr p15, 0, r0, c15, c15, 0
|
||||
|
||||
/* write XXXX0000 to PVR2F0 */
|
||||
mov r1, r3, lsl #16
|
||||
mcr p15, 2, r1, c15, c15, 0
|
||||
|
||||
adr r1, table_l2_acc
|
||||
and r0, r12, #0x008
|
||||
and r2, r12, #0x002
|
||||
orr r0, r0, r2, lsl #1
|
||||
ldr r2, [r1, r0]
|
||||
|
||||
/* write to L2VR3F1 */
|
||||
mcr p15, 3, r2, c15, c15, 1
|
||||
|
||||
bx lr
|
||||
|
||||
table_l1_acc:
|
||||
.word 0xFC00
|
||||
.word 0xFC00
|
||||
.word 0x7C00
|
||||
.word 0xFC00
|
||||
.word 0x3C00
|
||||
.word 0x0400
|
||||
.word 0x0C00
|
||||
.word 0x1C00
|
||||
|
||||
table_l2_acc:
|
||||
.word 0x010102
|
||||
.word 0x010102
|
||||
.word 0x010101
|
||||
.word 0x212102
|
||||
|
||||
.globl __cpu_early_init
|
||||
__cpu_early_init:
|
||||
//; Zero out r0 for use throughout this code. All other GPRs
|
||||
//; (r1-r3) are set throughout this code to help establish
|
||||
//; a consistent startup state for any code that follows.
|
||||
//; Users should add code at the end of this routine to establish
|
||||
//; their own stack address (r13), add translation page tables, enable
|
||||
//; the caches, etc.
|
||||
MOV r0, #0x0
|
||||
|
||||
|
||||
//; Remove hardcoded cache settings. appsbl_handler.s calls Set_SA
|
||||
//; API to dynamically configure cache for slow/nominal/fast parts
|
||||
|
||||
//; DCIALL to invalidate L2 cache bank (needs to be run 4 times, once per bank)
|
||||
//; This must be done early in code (prior to enabling the caches)
|
||||
MOV r1, #0x2
|
||||
MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank D ([15:14] == 2'b00)
|
||||
ORR r1, r1, #0x00004000
|
||||
MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank C ([15:14] == 2'b01)
|
||||
ADD r1, r1, #0x00004000
|
||||
MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank B ([15:14] == 2'b10)
|
||||
ADD r1, r1, #0x00004000
|
||||
MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank A ([15:14] == 2'b11)
|
||||
|
||||
//; Initialize the BPCR - setup Global History Mask (GHRM) to all 1's
|
||||
//; and have all address bits (AM) participate.
|
||||
//; Different settings can be used to improve performance
|
||||
// MOVW r1, #0x01FF
|
||||
.word 0xe30011ff // hardcoded MOVW instruction due to lack of compiler support
|
||||
// MOVT r1, #0x01FF
|
||||
.word 0xe34011ff // hardcoded MOVT instruction due to lack of compiler support
|
||||
MCR p15, 7, r1, c15, c0, 2 //; WCP15_BPCR
|
||||
|
||||
|
||||
//; Initialize all I$ Victim Registers to 0 for startup
|
||||
MCR p15, 0, r0, c9, c1, 0 //; WCP15_ICVIC0 r0
|
||||
MCR p15, 0, r0, c9, c1, 1 //; WCP15_ICVIC1 r0
|
||||
MCR p15, 0, r0, c9, c1, 2 //; WCP15_ICVIC2 r0
|
||||
MCR p15, 0, r0, c9, c1, 3 //; WCP15_ICVIC3 r0
|
||||
MCR p15, 0, r0, c9, c1, 4 //; WCP15_ICVIC4 r0
|
||||
MCR p15, 0, r0, c9, c1, 5 //; WCP15_ICVIC5 r0
|
||||
MCR p15, 0, r0, c9, c1, 6 //; WCP15_ICVIC5 r0
|
||||
MCR p15, 0, r0, c9, c1, 7 //; WCP15_ICVIC7 r0
|
||||
|
||||
//; Initialize all I$ Locked Victim Registers (Unlocked Floors) to 0
|
||||
MCR p15, 1, r0, c9, c1, 0 //; WCP15_ICFLOOR0 r0
|
||||
MCR p15, 1, r0, c9, c1, 1 //; WCP15_ICFLOOR1 r0
|
||||
MCR p15, 1, r0, c9, c1, 2 //; WCP15_ICFLOOR2 r0
|
||||
MCR p15, 1, r0, c9, c1, 3 //; WCP15_ICFLOOR3 r0
|
||||
MCR p15, 1, r0, c9, c1, 4 //; WCP15_ICFLOOR4 r0
|
||||
MCR p15, 1, r0, c9, c1, 5 //; WCP15_ICFLOOR5 r0
|
||||
MCR p15, 1, r0, c9, c1, 6 //; WCP15_ICFLOOR6 r0
|
||||
MCR p15, 1, r0, c9, c1, 7 //; WCP15_ICFLOOR7 r0
|
||||
|
||||
//; Initialize all D$ Victim Registers to 0
|
||||
MCR p15, 2, r0, c9, c1, 0 //; WP15_DCVIC0 r0
|
||||
MCR p15, 2, r0, c9, c1, 1 //; WP15_DCVIC1 r0
|
||||
MCR p15, 2, r0, c9, c1, 2 //; WP15_DCVIC2 r0
|
||||
MCR p15, 2, r0, c9, c1, 3 //; WP15_DCVIC3 r0
|
||||
MCR p15, 2, r0, c9, c1, 4 //; WP15_DCVIC4 r0
|
||||
MCR p15, 2, r0, c9, c1, 5 //; WP15_DCVIC5 r0
|
||||
MCR p15, 2, r0, c9, c1, 6 //; WP15_DCVIC6 r0
|
||||
MCR p15, 2, r0, c9, c1, 7 //; WP15_DCVIC7 r0
|
||||
|
||||
//; Initialize all D$ Locked VDCtim Registers (Unlocked Floors) to 0
|
||||
MCR p15, 3, r0, c9, c1, 0 //; WCP15_DCFLOOR0 r0
|
||||
MCR p15, 3, r0, c9, c1, 1 //; WCP15_DCFLOOR1 r0
|
||||
MCR p15, 3, r0, c9, c1, 2 //; WCP15_DCFLOOR2 r0
|
||||
MCR p15, 3, r0, c9, c1, 3 //; WCP15_DCFLOOR3 r0
|
||||
MCR p15, 3, r0, c9, c1, 4 //; WCP15_DCFLOOR4 r0
|
||||
MCR p15, 3, r0, c9, c1, 5 //; WCP15_DCFLOOR5 r0
|
||||
MCR p15, 3, r0, c9, c1, 6 //; WCP15_DCFLOOR6 r0
|
||||
MCR p15, 3, r0, c9, c1, 7 //; WCP15_DCFLOOR7 r0
|
||||
|
||||
//; Initialize ASID to zero
|
||||
MCR p15, 0, r0, c13, c0, 1 //; WCP15_CONTEXTIDR r0
|
||||
|
||||
//; ICIALL to invalidate entire I-Cache
|
||||
MCR p15, 0, r0, c7, c5, 0 //; ICIALLU
|
||||
|
||||
//; DCIALL to invalidate entire D-Cache
|
||||
MCR p15, 0, r0, c9, c0, 6 //; DCIALL r0
|
||||
|
||||
|
||||
//; The VBAR (Vector Base Address Register) should be initialized
|
||||
//; early in your code. We are setting it to zero
|
||||
MCR p15, 0, r0, c12, c0, 0 //; WCP15_VBAR r0
|
||||
|
||||
//; Ensure the MCR's above have completed their operation before continuing
|
||||
DSB
|
||||
ISB
|
||||
|
||||
//;-------------------------------------------------------------------
|
||||
//; There are a number of registers that must be set prior to enabling
|
||||
//; the MMU. The DCAR is one of these registers. We are setting
|
||||
//; it to zero (no access) to easily detect improper setup in subsequent
|
||||
//; code sequences
|
||||
//;-------------------------------------------------------------------
|
||||
//; Setup DACR (Domain Access Control Register) to zero
|
||||
MCR p15, 0, r0, c3, c0, 0 //; WCP15_DACR r0
|
||||
|
||||
//; Setup DCLKCR to allow normal D-Cache line fills
|
||||
MCR p15, 1, r0, c9, c0, 7 //; WCP15_DCLKCR r0
|
||||
|
||||
//; Initialize the ADFSR and EFSR registers.
|
||||
MCR p15, 0, r0, c5, c1, 0 //; ADFSR
|
||||
MCR p15, 7, r0, c15, c0, 1 //; EFSR
|
||||
|
||||
//; Setup the TLBLKCR
|
||||
//; Victim = 6'b000000; Floor = 6'b000000;
|
||||
//; IASIDCFG = 2'b00 (State-Machine); IALLCFG = 2'b01 (Flash); BNA = 1'b0;
|
||||
MOV r1, #0x02
|
||||
MCR p15, 0, r1, c10, c1, 3 //; WCP15_TLBLKCR r1
|
||||
|
||||
//;Make sure TLBLKCR is complete before continuing
|
||||
ISB
|
||||
|
||||
//; Invalidate the UTLB
|
||||
MCR p15, 0, r0, c8, c7, 0 //; UTLBIALL
|
||||
|
||||
//; Make sure UTLB request has been presented to macro before continuing
|
||||
ISB
|
||||
|
||||
//; setup L2CR1 to some default Instruction and data prefetching values
|
||||
//; Users may want specific settings for various performance enhancements
|
||||
//; In Halcyon we do not have broadcasting barriers. So we need to turn
|
||||
// ; on bit 8 of L2CR1; which DBB:( Disable barrier broadcast )
|
||||
MOV r2, #0x100
|
||||
MCR p15, 3, r2, c15, c0, 3 //; WCP15_L2CR1 r0
|
||||
|
||||
|
||||
//; Enable Z bit to enable branch prediction (default is off)
|
||||
MRC p15, 0, r2, c1, c0, 0 //; RCP15_SCTLR r2
|
||||
ORR r2, r2, #0x00000800
|
||||
MCR p15, 0, r2, c1, c0, 0 //; WCP15_SCTLR r2
|
||||
|
||||
#ifdef CONFIG_ARCH_QSD8X50
|
||||
/* disable predecode repair cache for thumb2 (DPRC, set bit 4 in PVR0F2) */
|
||||
mrc p15, 0, r2, c15, c15, 2
|
||||
orr r2, r2, #0x10
|
||||
mcr p15, 0, r2, c15, c15, 2
|
||||
#endif
|
||||
|
||||
mov r1, lr
|
||||
//; Make sure Link stack is initialized with branch and links to sequential addresses
|
||||
//; This aids in creating a predictable startup environment
|
||||
BL SEQ1
|
||||
SEQ1: BL SEQ2
|
||||
SEQ2: BL SEQ3
|
||||
SEQ3: BL SEQ4
|
||||
SEQ4: BL SEQ5
|
||||
SEQ5: BL SEQ6
|
||||
SEQ6: BL SEQ7
|
||||
SEQ7: BL SEQ8
|
||||
SEQ8:
|
||||
mov lr, r1
|
||||
|
||||
//; REMOVE FOLLOWING THREE INSTRUCTIONS WHEN POWER COLLAPSE IS ENA
|
||||
//;Make sure the DBGOSLSR[LOCK] bit is cleared to allow access to the debug registers
|
||||
//; Writing anything but the "secret code" to the DBGOSLAR clears the DBGOSLSR[LOCK] bit
|
||||
MCR p14, 0, r0, c1, c0, 4 //; WCP14_DBGOSLAR r0
|
||||
|
||||
|
||||
//; Read the DBGPRSR to clear the DBGPRSR[STICKYPD]
|
||||
//; Any read to DBGPRSR clear the STICKYPD bit
|
||||
//; ISB guarantees the read completes before attempting to
|
||||
//; execute a CP14 instruction.
|
||||
MRC p14, 0, r3, c1, c5, 4 //; RCP14_DBGPRSR r3
|
||||
ISB
|
||||
|
||||
//; Initialize the Watchpoint Control Registers to zero (optional)
|
||||
//;;; MCR p14, 0, r0, c0, c0, 7 ; WCP14_DBGWCR0 r0
|
||||
//;;; MCR p14, 0, r0, c0, c1, 7 ; WCP14_DBGWCR1 r0
|
||||
|
||||
|
||||
//;----------------------------------------------------------------------
|
||||
//; The saved Program Status Registers (SPSRs) should be setup
|
||||
//; prior to any automatic mode switches. The following
|
||||
//; code sets these registers up to a known state. Users will need to
|
||||
//; customize these settings to meet their needs.
|
||||
//;----------------------------------------------------------------------
|
||||
MOV r2, #0x1f
|
||||
MOV r1, #0x17 //;ABT mode
|
||||
msr cpsr_c, r1 //;ABT mode
|
||||
msr spsr_cxfs, r2 //;clear the spsr
|
||||
MOV r1, #0x1b //;UND mode
|
||||
msr cpsr_c, r1 //;UND mode
|
||||
msr spsr_cxfs, r2 //;clear the spsr
|
||||
MOV r1, #0x11 //;FIQ mode
|
||||
msr cpsr_c, r1 //;FIQ mode
|
||||
msr spsr_cxfs, r2 //;clear the spsr
|
||||
MOV r1, #0x12 //;IRQ mode
|
||||
msr cpsr_c, r1 //;IRQ mode
|
||||
msr spsr_cxfs, r2 //;clear the spsr
|
||||
MOV r1, #0x16 //;Monitor mode
|
||||
msr cpsr_c, r1 //;Monitor mode
|
||||
msr spsr_cxfs, r2 //;clear the spsr
|
||||
MOV r1, #0x13 //;SVC mode
|
||||
msr cpsr_c, r1 //;SVC mode
|
||||
msr spsr_cxfs, r2 //;clear the spsr
|
||||
|
||||
|
||||
//;----------------------------------------------------------------------
|
||||
//; Enabling Error reporting is something users may want to do at
|
||||
//; some other point in time. We have chosen some default settings
|
||||
//; that should be reviewed. Most of these registers come up in an
|
||||
//; unpredictable state after reset.
|
||||
//;----------------------------------------------------------------------
|
||||
//;Start of error and control setting
|
||||
|
||||
//; setup L2CR0 with various L2/TCM control settings
|
||||
//; enable out of order bus attributes and error reporting
|
||||
//; this register comes up unpredictable after reset
|
||||
// MOVW r1, #0x0F0F
|
||||
.word 0xe3001f0f // hardcoded MOVW instruction due to lack of compiler support
|
||||
// MOVT r1, #0xC005
|
||||
.word 0xe34c1005 // hardcoded MOVW instruction due to lack of compiler support
|
||||
MCR p15, 3, r1, c15, c0, 1 //; WCP15_L2CR0 r1
|
||||
|
||||
//; setup L2CPUCR
|
||||
//; MOV r2, #0xFF
|
||||
//; Enable I and D cache parity
|
||||
//;L2CPUCR[7:5] = 3~Rh7 ~V enable parity error reporting for modified,
|
||||
//;tag, and data parity errors
|
||||
MOV r2, #0xe0
|
||||
MCR p15, 3, r2, c15, c0, 2 //; WCP15_L2CPUCR r2
|
||||
|
||||
//; setup SPCR
|
||||
//; enable all error reporting (reset value is unpredicatble for most bits)
|
||||
MOV r3, #0x0F
|
||||
MCR p15, 0, r3, c9, c7, 0 //; WCP15_SPCR r3
|
||||
|
||||
//; setup DMACHCRs (reset value unpredictable)
|
||||
//; control setting and enable all error reporting
|
||||
MOV r1, #0x0F
|
||||
|
||||
//; DMACHCR0 = 0000000F
|
||||
MOV r2, #0x00 //; channel 0
|
||||
MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
|
||||
MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
|
||||
|
||||
//; DMACHCR1 = 0000000F
|
||||
MOV r2, #0x01 //; channel 1
|
||||
MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
|
||||
MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
|
||||
|
||||
//; DMACHCR2 = 0000000F
|
||||
MOV r2, #0x02 //; channel 2
|
||||
MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
|
||||
MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
|
||||
|
||||
//; DMACHCR3 = 0000000F
|
||||
MOV r2, #0x03 //; channel 3
|
||||
MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
|
||||
MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
|
||||
|
||||
//; Set ACTLR (reset unpredictable)
|
||||
//; Set AVIVT control, error reporting, etc.
|
||||
//; MOV r3, #0x07
|
||||
//; Enable I and D cache parity
|
||||
//;ACTLR[2:0] = 3'h7 - enable parity error reporting from L2/I$/D$)
|
||||
//;ACTLR[5:4] = 2'h3 - enable parity
|
||||
//;ACTLR[19:18] =2'h3 - always generate and check parity(when MMU disabled).
|
||||
//;Value to be written #0xC0037
|
||||
// MOVW r3, #0x0037
|
||||
.word 0xe3003037 // hardcoded MOVW instruction due to lack of compiler support
|
||||
// MOVT r3, #0x000C
|
||||
.word 0xe340300c // hardcoded MOVW instruction due to lack of compiler support
|
||||
//; read the version_id to determine if d-cache should be disabled
|
||||
LDR r2, = 0xa8e00270 //;Read HW_REVISION_NUMBER, HWIO_HW_REVISION_NUMBER_ADDR
|
||||
LDR r2,[r2]
|
||||
AND r2,r2,#0xf0000000 //;hw_revision mask off bits 28-31
|
||||
//;if HW_revision is 1.0 or older, (revision==0)
|
||||
CMP r2,#0
|
||||
//; Disable d-cache on older QSD8650 (Rev 1.0) silicon
|
||||
orreq r3, r3, #0x4000 //;disable dcache
|
||||
MCR p15, 0, r3, c1, c0, 1 //; WCP15_ACTLR r3
|
||||
|
||||
//;End of error and control setting
|
||||
|
||||
//;----------------------------------------------------------------------
|
||||
//; Unlock ETM and read StickyPD to halt the ETM clocks from running.
|
||||
//; This is required for power saving whether the ETM is used or not.
|
||||
//;----------------------------------------------------------------------
|
||||
|
||||
//;Clear ETMOSLSR[LOCK] bit
|
||||
MOV r1, #0x00000000
|
||||
MCR p14, 1, r1, c1, c0, 4 //; WCP14_ETMOSLAR r1
|
||||
|
||||
//;Clear ETMPDSR[STICKYPD] bit
|
||||
MRC p14, 1, r2, c1, c5, 4 //; RCP14_ETMPDSR r2
|
||||
|
||||
/*
|
||||
#ifdef APPSBL_ETM_ENABLE
|
||||
;----------------------------------------------------------------------
|
||||
; Optionally Enable the ETM (Embedded Trace Macro) which is used for debug
|
||||
;----------------------------------------------------------------------
|
||||
|
||||
; enable ETM clock if disabled
|
||||
MRC p15, 7, r1, c15, c0, 5 ; RCP15_CPMR r1
|
||||
ORR r1, r1, #0x00000008
|
||||
MCR p15, 7, r1, c15, c0, 5 ; WCP15_CPMR r1
|
||||
ISB
|
||||
|
||||
; set trigger event to counter1 being zero
|
||||
MOV r3, #0x00000040
|
||||
MCR p14, 1, r3, c0, c2, 0 ; WCP14_ETMTRIGGER r3
|
||||
|
||||
; clear ETMSR
|
||||
MOV r2, #0x00000000
|
||||
MCR p14, 1, r2, c0, c4, 0 ; WCP14_ETMSR r2
|
||||
|
||||
; clear trace enable single address comparator usage
|
||||
MCR p14, 1, r2, c0, c7, 0 ; WCP14_ETMTECR2 r2
|
||||
|
||||
; set trace enable to always
|
||||
MOV r2, #0x0000006F
|
||||
MCR p14, 1, r2, c0, c8, 0 ; WCP14_ETMTEEVR r2
|
||||
|
||||
; clear trace enable address range comparator usage and exclude nothing
|
||||
MOV r2, #0x01000000
|
||||
MCR p14, 1, r2, c0, c9, 0 ; WCP14_ETMTECR1 r2
|
||||
|
||||
; set view data to always
|
||||
MOV r2, #0x0000006F
|
||||
MCR p14, 1, r2, c0, c12, 0 ; WCP14_ETMVDEVR r2
|
||||
|
||||
; clear view data single address comparator usage
|
||||
MOV r2, #0x00000000
|
||||
MCR p14, 1, r2, c0, c13, 0 ; WCP14_ETMVDCR1 r2
|
||||
|
||||
; clear view data address range comparator usage and exclude nothing
|
||||
MOV r2, #0x00010000
|
||||
MCR p14, 1, r2, c0, c15, 0 ; WCP14_ETMVDCR3 r2
|
||||
|
||||
; set counter1 to 194
|
||||
MOV r2, #0x000000C2
|
||||
MCR p14, 1, r2, c0, c0, 5 ; WCP14_ETMCNTRLDVR1 r2
|
||||
|
||||
; set counter1 to never reload
|
||||
MOV r2, #0x0000406F
|
||||
MCR p14, 1, r2, c0, c8, 5 ; WCP14_ETMCNTRLDEVR1 r2
|
||||
|
||||
; set counter1 to decrement every cycle
|
||||
MOV r2, #0x0000006F
|
||||
MCR p14, 1, r2, c0, c4, 5 ; WCP14_ETMCNTENR1 r2
|
||||
|
||||
; Set trace synchronization frequency 1024 bytes
|
||||
MOV r2, #0x00000400
|
||||
MCR p14, 1, r2, c0, c8, 7 ; WCP14_ETMSYNCFR r2
|
||||
|
||||
; Program etm control register
|
||||
; - Set the CPU to ETM clock ratio to 1:1
|
||||
; - Set the ETM to perform data address tracing
|
||||
MOV r2, #0x00002008
|
||||
MCR p14, 1, r2, c0, c0, 0 ; WCP14_ETMCR r2
|
||||
ISB
|
||||
#endif *//* APPSBL_ETM_ENABLE */
|
||||
|
||||
/*
|
||||
#ifdef APPSBL_VFP_ENABLE
|
||||
;----------------------------------------------------------------------
|
||||
; Perform the following operations if you intend to make use of
|
||||
; the VFP/Neon unit. Note that the FMXR instruction requires a CPU ID
|
||||
; indicating the VFP unit is present (i.e.Cortex-A8). .
|
||||
; Some tools will require full double precision floating point support
|
||||
; which will become available in Scorpion pass 2
|
||||
;----------------------------------------------------------------------
|
||||
; allow full access to CP 10 and 11 space for VFP/NEON use
|
||||
MRC p15, 0, r1, c1, c0, 2 ; Read CP Access Control Register
|
||||
ORR r1, r1, #0x00F00000 ; enable full access for p10,11
|
||||
MCR p15, 0, r1, c1, c0, 2 ; Write CPACR
|
||||
|
||||
;make sure the CPACR is complete before continuing
|
||||
ISB
|
||||
|
||||
; Enable VFP itself (certain OSes may want to dynamically set/clear
|
||||
; the enable bit based on the application being executed
|
||||
MOV r1, #0x40000000
|
||||
FMXR FPEXC, r1
|
||||
#endif *//* APPSBL_VFP_ENABLE */
|
||||
|
||||
/* we have no stack, so just tail-call into the SET_SA routine... */
|
||||
b SET_SA
|
||||
|
||||
.ltorg
|
||||
280
arch/arm/mach-msm/avs.c
Normal file
280
arch/arm/mach-msm/avs.c
Normal file
@@ -0,0 +1,280 @@
|
||||
/*
|
||||
* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "avs.h"
|
||||
|
||||
#define AVSDSCR_INPUT 0x01004860 /* magic # from circuit designer */
|
||||
#define TSCSR_INPUT 0x00000001 /* enable temperature sense */
|
||||
|
||||
#define TEMPRS 16 /* total number of temperature regions */
|
||||
#define GET_TEMPR() (avs_get_tscsr() >> 28) /* scale TSCSR[CTEMP] to regions */
|
||||
|
||||
struct mutex avs_lock;
|
||||
|
||||
static struct avs_state_s
|
||||
{
|
||||
u32 freq_cnt; /* Frequencies supported list */
|
||||
short *avs_v; /* Dyanmically allocated storage for
|
||||
* 2D table of voltages over temp &
|
||||
* freq. Used as a set of 1D tables.
|
||||
* Each table is for a single temp.
|
||||
* For usage see avs_get_voltage
|
||||
*/
|
||||
int (*set_vdd) (int); /* Function Ptr for setting voltage */
|
||||
int changing; /* Clock frequency is changing */
|
||||
u32 freq_idx; /* Current frequency index */
|
||||
int vdd; /* Current ACPU voltage */
|
||||
} avs_state;
|
||||
|
||||
/*
|
||||
* Update the AVS voltage vs frequency table, for current temperature
|
||||
* Adjust based on the AVS delay circuit hardware status
|
||||
*/
|
||||
static void avs_update_voltage_table(short *vdd_table)
|
||||
{
|
||||
u32 avscsr;
|
||||
int cpu;
|
||||
int vu;
|
||||
int l2;
|
||||
int i;
|
||||
u32 cur_freq_idx;
|
||||
short cur_voltage;
|
||||
|
||||
cur_freq_idx = avs_state.freq_idx;
|
||||
cur_voltage = avs_state.vdd;
|
||||
|
||||
avscsr = avs_test_delays();
|
||||
AVSDEBUG("avscsr=%x, avsdscr=%x\n", avscsr, avs_get_avsdscr());
|
||||
|
||||
/*
|
||||
* Read the results for the various unit's AVS delay circuits
|
||||
* 2=> up, 1=>down, 0=>no-change
|
||||
*/
|
||||
cpu = ((avscsr >> 23) & 2) + ((avscsr >> 16) & 1);
|
||||
vu = ((avscsr >> 28) & 2) + ((avscsr >> 21) & 1);
|
||||
l2 = ((avscsr >> 29) & 2) + ((avscsr >> 22) & 1);
|
||||
|
||||
if ((cpu == 3) || (vu == 3) || (l2 == 3)) {
|
||||
printk(KERN_ERR "AVS: Dly Synth O/P error\n");
|
||||
} else if ((cpu == 2) || (l2 == 2) || (vu == 2)) {
|
||||
/*
|
||||
* even if one oscillator asks for up, increase the voltage,
|
||||
* as its an indication we are running outside the
|
||||
* critical acceptable range of v-f combination.
|
||||
*/
|
||||
AVSDEBUG("cpu=%d l2=%d vu=%d\n", cpu, l2, vu);
|
||||
AVSDEBUG("Voltage up at %d\n", cur_freq_idx);
|
||||
|
||||
if (cur_voltage >= VOLTAGE_MAX)
|
||||
printk(KERN_ERR
|
||||
"AVS: Voltage can not get high enough!\n");
|
||||
|
||||
/* Raise the voltage for all frequencies */
|
||||
for (i = 0; i < avs_state.freq_cnt; i++) {
|
||||
vdd_table[i] = cur_voltage + VOLTAGE_STEP;
|
||||
if (vdd_table[i] > VOLTAGE_MAX)
|
||||
vdd_table[i] = VOLTAGE_MAX;
|
||||
}
|
||||
} else if ((cpu == 1) && (l2 == 1) && (vu == 1)) {
|
||||
if ((cur_voltage - VOLTAGE_STEP >= VOLTAGE_MIN) &&
|
||||
(cur_voltage <= vdd_table[cur_freq_idx])) {
|
||||
vdd_table[cur_freq_idx] = cur_voltage - VOLTAGE_STEP;
|
||||
AVSDEBUG("Voltage down for %d and lower levels\n",
|
||||
cur_freq_idx);
|
||||
|
||||
/* clamp to this voltage for all lower levels */
|
||||
for (i = 0; i < cur_freq_idx; i++) {
|
||||
if (vdd_table[i] > vdd_table[cur_freq_idx])
|
||||
vdd_table[i] = vdd_table[cur_freq_idx];
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the voltage for the target performance freq_idx and optionally
|
||||
* use AVS hardware to check the present voltage freq_idx
|
||||
*/
|
||||
static short avs_get_target_voltage(int freq_idx, bool update_table)
|
||||
{
|
||||
unsigned cur_tempr = GET_TEMPR();
|
||||
unsigned temp_index = cur_tempr*avs_state.freq_cnt;
|
||||
|
||||
/* Table of voltages vs frequencies for this temp */
|
||||
short *vdd_table = avs_state.avs_v + temp_index;
|
||||
|
||||
if (update_table)
|
||||
avs_update_voltage_table(vdd_table);
|
||||
|
||||
return vdd_table[freq_idx];
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Set the voltage for the freq_idx and optionally
|
||||
* use AVS hardware to update the voltage
|
||||
*/
|
||||
static int avs_set_target_voltage(int freq_idx, bool update_table)
|
||||
{
|
||||
int rc = 0;
|
||||
int new_voltage = avs_get_target_voltage(freq_idx, update_table);
|
||||
if (avs_state.vdd != new_voltage) {
|
||||
AVSDEBUG("AVS setting V to %d mV @%d\n",
|
||||
new_voltage, freq_idx);
|
||||
rc = avs_state.set_vdd(new_voltage);
|
||||
if (rc)
|
||||
return rc;
|
||||
avs_state.vdd = new_voltage;
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
|
||||
/*
|
||||
* Notify avs of clk frquency transition begin & end
|
||||
*/
|
||||
int avs_adjust_freq(u32 freq_idx, int begin)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
if (!avs_state.set_vdd) {
|
||||
/* AVS not initialized */
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (freq_idx >= avs_state.freq_cnt) {
|
||||
AVSDEBUG("Out of range :%d\n", freq_idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
mutex_lock(&avs_lock);
|
||||
if ((begin && (freq_idx > avs_state.freq_idx)) ||
|
||||
(!begin && (freq_idx < avs_state.freq_idx))) {
|
||||
/* Update voltage before increasing frequency &
|
||||
* after decreasing frequency
|
||||
*/
|
||||
rc = avs_set_target_voltage(freq_idx, 0);
|
||||
if (rc)
|
||||
goto aaf_out;
|
||||
|
||||
avs_state.freq_idx = freq_idx;
|
||||
}
|
||||
avs_state.changing = begin;
|
||||
aaf_out:
|
||||
mutex_unlock(&avs_lock);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
static struct delayed_work avs_work;
|
||||
static struct workqueue_struct *kavs_wq;
|
||||
#define AVS_DELAY ((CONFIG_HZ * 50 + 999) / 1000)
|
||||
|
||||
static void do_avs_timer(struct work_struct *work)
|
||||
{
|
||||
int cur_freq_idx;
|
||||
|
||||
mutex_lock(&avs_lock);
|
||||
if (!avs_state.changing) {
|
||||
/* Only adjust the voltage if clk is stable */
|
||||
cur_freq_idx = avs_state.freq_idx;
|
||||
avs_set_target_voltage(cur_freq_idx, 1);
|
||||
}
|
||||
mutex_unlock(&avs_lock);
|
||||
queue_delayed_work_on(0, kavs_wq, &avs_work, AVS_DELAY);
|
||||
}
|
||||
|
||||
|
||||
static void __init avs_timer_init(void)
|
||||
{
|
||||
INIT_DELAYED_WORK_DEFERRABLE(&avs_work, do_avs_timer);
|
||||
queue_delayed_work_on(0, kavs_wq, &avs_work, AVS_DELAY);
|
||||
}
|
||||
|
||||
static void __exit avs_timer_exit(void)
|
||||
{
|
||||
cancel_delayed_work(&avs_work);
|
||||
}
|
||||
|
||||
static int __init avs_work_init(void)
|
||||
{
|
||||
kavs_wq = create_workqueue("avs");
|
||||
if (!kavs_wq) {
|
||||
printk(KERN_ERR "AVS initialization failed\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
avs_timer_init();
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void __exit avs_work_exit(void)
|
||||
{
|
||||
avs_timer_exit();
|
||||
destroy_workqueue(kavs_wq);
|
||||
}
|
||||
|
||||
int __init avs_init(int (*set_vdd)(int), u32 freq_cnt, u32 freq_idx)
|
||||
{
|
||||
int i;
|
||||
|
||||
mutex_init(&avs_lock);
|
||||
|
||||
if (freq_cnt == 0)
|
||||
return -EINVAL;
|
||||
|
||||
avs_state.freq_cnt = freq_cnt;
|
||||
|
||||
if (freq_idx >= avs_state.freq_cnt)
|
||||
return -EINVAL;
|
||||
|
||||
avs_state.avs_v = kmalloc(TEMPRS * avs_state.freq_cnt *
|
||||
sizeof(avs_state.avs_v[0]), GFP_KERNEL);
|
||||
|
||||
if (avs_state.avs_v == 0)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < TEMPRS*avs_state.freq_cnt; i++)
|
||||
avs_state.avs_v[i] = VOLTAGE_MAX;
|
||||
|
||||
avs_reset_delays(AVSDSCR_INPUT);
|
||||
avs_set_tscsr(TSCSR_INPUT);
|
||||
|
||||
avs_state.set_vdd = set_vdd;
|
||||
avs_state.changing = 0;
|
||||
avs_state.freq_idx = -1;
|
||||
avs_state.vdd = -1;
|
||||
avs_adjust_freq(freq_idx, 0);
|
||||
|
||||
avs_work_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __exit avs_exit()
|
||||
{
|
||||
avs_work_exit();
|
||||
|
||||
kfree(avs_state.avs_v);
|
||||
}
|
||||
|
||||
|
||||
69
arch/arm/mach-msm/avs.h
Normal file
69
arch/arm/mach-msm/avs.h
Normal file
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef AVS_H
|
||||
#define AVS_H
|
||||
|
||||
#define VOLTAGE_MIN 1000 /* mV */
|
||||
#define VOLTAGE_MAX 1250
|
||||
#define VOLTAGE_STEP 25
|
||||
|
||||
int __init avs_init(int (*set_vdd)(int), u32 freq_cnt, u32 freq_idx);
|
||||
void __exit avs_exit(void);
|
||||
|
||||
int avs_adjust_freq(u32 freq_index, int begin);
|
||||
|
||||
/* Routines exported from avs_hw.S */
|
||||
#ifdef CONFIG_MSM_CPU_AVS
|
||||
u32 avs_test_delays(void);
|
||||
#else
|
||||
static inline u32 avs_test_delays(void)
|
||||
{ return 0; }
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MSM_AVS_HW
|
||||
u32 avs_reset_delays(u32 avsdscr);
|
||||
u32 avs_get_avscsr(void);
|
||||
u32 avs_get_avsdscr(void);
|
||||
u32 avs_get_tscsr(void);
|
||||
void avs_set_tscsr(u32 to_tscsr);
|
||||
void avs_disable(void);
|
||||
#else
|
||||
static inline u32 avs_reset_delays(u32 avsdscr)
|
||||
{ return 0; }
|
||||
static inline u32 avs_get_avscsr(void)
|
||||
{ return 0; }
|
||||
static inline u32 avs_get_avsdscr(void)
|
||||
{ return 0; }
|
||||
static inline u32 avs_get_tscsr(void)
|
||||
{ return 0; }
|
||||
static inline void avs_set_tscsr(u32 to_tscsr) {}
|
||||
static inline void avs_disable(void) {}
|
||||
#endif
|
||||
|
||||
/*#define AVSDEBUG(x...) pr_info("AVS: " x);*/
|
||||
#define AVSDEBUG(...)
|
||||
|
||||
#define AVS_DISABLE(cpu) do { \
|
||||
if (get_cpu() == (cpu)) \
|
||||
avs_disable(); \
|
||||
put_cpu(); \
|
||||
} while (0);
|
||||
|
||||
#define AVS_ENABLE(cpu, x) do { \
|
||||
if (get_cpu() == (cpu)) \
|
||||
avs_reset_delays((x)); \
|
||||
put_cpu(); \
|
||||
} while (0);
|
||||
|
||||
#endif /* AVS_H */
|
||||
127
arch/arm/mach-msm/avs_hw.S
Normal file
127
arch/arm/mach-msm/avs_hw.S
Normal file
@@ -0,0 +1,127 @@
|
||||
/*
|
||||
* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
.text
|
||||
|
||||
#ifdef CONFIG_MSM_CPU_AVS
|
||||
.global avs_test_delays
|
||||
avs_test_delays:
|
||||
|
||||
/* Read r1=CPMR and enable Never Sleep for VSLPDLY */
|
||||
mrc p15, 7, r1, c15, c0, 5
|
||||
orr r12, r1, #3, 24
|
||||
mcr p15, 7, r12, c15, c0, 5
|
||||
|
||||
/* Read r2=CPACR and enable full access to CP10 and CP11 space */
|
||||
mrc p15, 0, r2, c1, c0, 2
|
||||
orr r12, r2, #(0xf << 20)
|
||||
mcr p15, 0, r12, c1, c0, 2
|
||||
isb
|
||||
|
||||
/* Read r3=FPEXC and or in FP enable, VFP/ASE enable = FPEXC[30]; */
|
||||
fmrx r3, fpexc
|
||||
orr r12, r3, #1, 2
|
||||
fmxr fpexc, r12
|
||||
|
||||
/*
|
||||
* Do floating-point operations to prime the VFP pipeline. Use
|
||||
* fcpyd d0, d0 as a floating point nop. This avoids changing VFP
|
||||
* state.
|
||||
*/
|
||||
fcpyd d0, d0
|
||||
fcpyd d0, d0
|
||||
fcpyd d0, d0
|
||||
|
||||
/* Read r0=AVSCSR to get status from CPU, VFP, and L2 ring oscillators */
|
||||
mrc p15, 7, r0, c15, c1, 7
|
||||
|
||||
/* Restore FPEXC */
|
||||
fmxr fpexc, r3
|
||||
|
||||
/* Restore CPACR */
|
||||
MCR p15, 0, r2, c1, c0, 2
|
||||
|
||||
/* Restore CPMR */
|
||||
mcr p15, 7, r1, c15, c0, 5
|
||||
isb
|
||||
|
||||
bx lr
|
||||
#endif
|
||||
|
||||
|
||||
.global avs_get_avscsr
|
||||
/* Read r0=AVSCSR to get status from CPU, VFP, and L2 ring oscillators */
|
||||
|
||||
avs_get_avscsr:
|
||||
mrc p15, 7, r0, c15, c1, 7
|
||||
bx lr
|
||||
|
||||
.global avs_get_avsdscr
|
||||
/* Read r0=AVSDSCR to get the AVS Delay Synthesizer control settings */
|
||||
|
||||
avs_get_avsdscr:
|
||||
mrc p15, 7, r0, c15, c0, 6
|
||||
bx lr
|
||||
|
||||
|
||||
|
||||
|
||||
.global avs_get_tscsr
|
||||
/* Read r0=TSCSR to get temperature sensor control and status */
|
||||
|
||||
avs_get_tscsr:
|
||||
mrc p15, 7, r0, c15, c1, 0
|
||||
bx lr
|
||||
|
||||
.global avs_set_tscsr
|
||||
/* Write TSCSR=r0 to set temperature sensor control and status */
|
||||
|
||||
avs_set_tscsr:
|
||||
mcr p15, 7, r0, c15, c1, 0
|
||||
bx lr
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
.global avs_reset_delays
|
||||
avs_reset_delays:
|
||||
|
||||
/* AVSDSCR(dly) to program delay */
|
||||
mcr p15, 7, r0, c15, c0, 6
|
||||
|
||||
/* Read r0=AVSDSCR */
|
||||
mrc p15, 7, r0, c15, c0, 6
|
||||
|
||||
/* AVSCSR(0x61) to enable CPU, V and L2 AVS module */
|
||||
mov r3, #0x61
|
||||
mcr p15, 7, r3, c15, c1, 7
|
||||
|
||||
bx lr
|
||||
|
||||
|
||||
|
||||
.global avs_disable
|
||||
avs_disable:
|
||||
|
||||
/* Clear AVSCSR */
|
||||
mov r0, #0
|
||||
|
||||
/* Write AVSCSR */
|
||||
mcr p15, 7, r0, c15, c1, 7
|
||||
|
||||
bx lr
|
||||
|
||||
.end
|
||||
|
||||
|
||||
2326
arch/arm/mach-msm/bam_dmux.c
Normal file
2326
arch/arm/mach-msm/bam_dmux.c
Normal file
File diff suppressed because it is too large
Load Diff
86
arch/arm/mach-msm/bms-batterydata-desay.c
Normal file
86
arch/arm/mach-msm/bms-batterydata-desay.c
Normal file
@@ -0,0 +1,86 @@
|
||||
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/mfd/pm8xxx/pm8921-bms.h>
|
||||
|
||||
static struct single_row_lut desay_5200_fcc_temp = {
|
||||
.x = {-20, 0, 25, 40},
|
||||
.y = {5690, 5722, 5722, 5727},
|
||||
.cols = 4
|
||||
};
|
||||
|
||||
static struct single_row_lut desay_5200_fcc_sf = {
|
||||
.x = {0},
|
||||
.y = {100},
|
||||
.cols = 1
|
||||
};
|
||||
|
||||
static struct pc_temp_ocv_lut desay_5200_pc_temp_ocv = {
|
||||
.rows = 29,
|
||||
.cols = 4,
|
||||
.temp = {-20, 0, 25, 40},
|
||||
.percent = {100, 95, 90, 85, 80, 75, 70, 65, 60, 55,
|
||||
50, 45, 40, 35, 30, 25, 20, 15, 10, 9, 8,
|
||||
7, 6, 5, 4, 3, 2, 1, 0
|
||||
},
|
||||
.ocv = {
|
||||
{4185, 4184, 4181, 4178},
|
||||
{4103, 4117, 4120, 4119},
|
||||
{4044, 4067, 4074, 4073},
|
||||
{3987, 4019, 4031, 4030},
|
||||
{3941, 3974, 3992, 3992},
|
||||
{3902, 3936, 3958, 3957},
|
||||
{3866, 3901, 3926, 3926},
|
||||
{3835, 3870, 3891, 3896},
|
||||
{3811, 3842, 3855, 3858},
|
||||
{3792, 3818, 3827, 3827},
|
||||
{3776, 3795, 3806, 3806},
|
||||
{3762, 3778, 3789, 3790},
|
||||
{3748, 3765, 3777, 3777},
|
||||
{3735, 3752, 3767, 3765},
|
||||
{3720, 3739, 3756, 3754},
|
||||
{3704, 3726, 3743, 3736},
|
||||
{3685, 3712, 3723, 3716},
|
||||
{3664, 3697, 3695, 3689},
|
||||
{3623, 3672, 3669, 3664},
|
||||
{3611, 3666, 3666, 3661},
|
||||
{3597, 3659, 3662, 3658},
|
||||
{3579, 3648, 3657, 3653},
|
||||
{3559, 3630, 3644, 3639},
|
||||
{3532, 3600, 3612, 3606},
|
||||
{3497, 3558, 3565, 3559},
|
||||
{3450, 3500, 3504, 3498},
|
||||
{3380, 3417, 3421, 3416},
|
||||
{3265, 3287, 3296, 3293},
|
||||
{3000, 3000, 3000, 3000}
|
||||
},
|
||||
};
|
||||
|
||||
static struct sf_lut desay_5200_pc_sf = {
|
||||
.rows = 1,
|
||||
.cols = 1,
|
||||
/* row_entries are cycles here */
|
||||
.row_entries = {0},
|
||||
.percent = {100},
|
||||
.sf = {
|
||||
{100}
|
||||
},
|
||||
};
|
||||
|
||||
struct pm8921_bms_battery_data desay_5200_data = {
|
||||
.fcc = 5200,
|
||||
.fcc_temp_lut = &desay_5200_fcc_temp,
|
||||
.fcc_sf_lut = &desay_5200_fcc_sf,
|
||||
.pc_temp_ocv_lut = &desay_5200_pc_temp_ocv,
|
||||
.pc_sf_lut = &desay_5200_pc_sf,
|
||||
.default_rbatt_mohm = 156,
|
||||
};
|
||||
127
arch/arm/mach-msm/bms-batterydata.c
Normal file
127
arch/arm/mach-msm/bms-batterydata.c
Normal file
@@ -0,0 +1,127 @@
|
||||
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/mfd/pm8xxx/pm8921-bms.h>
|
||||
|
||||
static struct single_row_lut palladium_1500_fcc_temp = {
|
||||
.x = {-30, -20, -10, 0, 10, 25, 40, 60},
|
||||
.y = {1103, 1179, 1284, 1330, 1420, 1511, 1541, 1571},
|
||||
.cols = 8,
|
||||
};
|
||||
|
||||
static struct single_row_lut palladium_1500_fcc_sf = {
|
||||
.x = {100, 200, 300, 400, 500},
|
||||
.y = {97, 93, 93, 90, 87},
|
||||
.cols = 5,
|
||||
};
|
||||
|
||||
static struct sf_lut palladium_1500_pc_sf = {
|
||||
.rows = 10,
|
||||
.cols = 5,
|
||||
/* row_entries are chargecycles */
|
||||
.row_entries = {100, 200, 300, 400, 500},
|
||||
.percent = {100, 90, 80, 70, 60, 50, 40, 30, 20, 10},
|
||||
.sf = {
|
||||
{97, 93, 93, 90, 87},
|
||||
{97, 93, 93, 90, 87},
|
||||
{98, 94, 92, 89, 86},
|
||||
{98, 94, 92, 89, 86},
|
||||
{99, 94, 92, 88, 86},
|
||||
{99, 95, 92, 88, 87},
|
||||
{99, 95, 92, 88, 87},
|
||||
{99, 95, 92, 88, 87},
|
||||
{99, 95, 92, 88, 87},
|
||||
{99, 95, 92, 88, 87}
|
||||
},
|
||||
};
|
||||
|
||||
static struct sf_lut palladium_1500_rbatt_sf = {
|
||||
.rows = 19,
|
||||
.cols = 5,
|
||||
/* row_entries are temperature */
|
||||
.row_entries = {-20, 0, 20, 40, 65},
|
||||
.percent = {100, 95, 90, 85, 80, 75, 70, 65, 60, 55, 50,
|
||||
45, 40, 35, 30, 25, 20, 15, 10
|
||||
},
|
||||
.sf = {
|
||||
{645, 301, 100, 80, 69},
|
||||
{616, 290, 100, 79, 69},
|
||||
{586, 279, 100, 78, 68},
|
||||
{564, 270, 100, 78, 68},
|
||||
{546, 262, 100, 78, 68},
|
||||
{537, 256, 100, 79, 68},
|
||||
{536, 253, 100, 79, 69},
|
||||
{552, 258, 100, 81, 71},
|
||||
{618, 284, 100, 80, 72},
|
||||
{643, 290, 100, 77, 68},
|
||||
{673, 294, 100, 77, 68},
|
||||
{720, 296, 100, 77, 69},
|
||||
{769, 294, 100, 76, 68},
|
||||
{821, 288, 100, 74, 67},
|
||||
{892, 284, 100, 74, 61},
|
||||
{1003, 290, 100, 71, 58},
|
||||
{1192, 307, 100, 70, 58},
|
||||
{1579, 345, 100, 68, 57},
|
||||
{1261, 324, 100, 68, 57},
|
||||
}
|
||||
};
|
||||
static struct pc_temp_ocv_lut palladium_1500_pc_temp_ocv = {
|
||||
.rows = 29,
|
||||
.cols = 8,
|
||||
.temp = {-30, -20, -10, 0, 10, 25, 40, 60},
|
||||
.percent = {100, 95, 90, 85, 80, 75, 70, 65, 60, 55,
|
||||
50, 45, 40, 35, 30, 25, 20, 15, 10, 9,
|
||||
8, 7, 6, 5, 4, 3, 2, 1, 0
|
||||
},
|
||||
.ocv = {
|
||||
{3673, 3814, 3945, 4025, 4106, 4176, 4218, 4260},
|
||||
{3613, 3751, 3880, 3959, 4038, 4107, 4149, 4190},
|
||||
{3573, 3710, 3837, 3916, 3994, 4062, 4103, 4144},
|
||||
{3534, 3670, 3796, 3873, 3951, 4019, 4059, 4099},
|
||||
{3491, 3625, 3749, 3826, 3902, 3969, 4009, 4049},
|
||||
{3464, 3597, 3721, 3796, 3872, 3939, 3978, 4018},
|
||||
{3436, 3568, 3691, 3766, 3841, 3907, 3946, 3985},
|
||||
{3407, 3537, 3659, 3733, 3808, 3873, 3912, 3951},
|
||||
{3377, 3507, 3627, 3701, 3775, 3840, 3878, 3917},
|
||||
{3355, 3484, 3604, 3677, 3751, 3815, 3853, 3891},
|
||||
{3339, 3467, 3586, 3659, 3732, 3796, 3834, 3872},
|
||||
{3324, 3452, 3570, 3643, 3716, 3780, 3818, 3855},
|
||||
{3312, 3440, 3558, 3630, 3703, 3766, 3804, 3842},
|
||||
{3303, 3430, 3548, 3620, 3692, 3756, 3793, 3831},
|
||||
{3297, 3424, 3541, 3614, 3686, 3749, 3787, 3824},
|
||||
{3288, 3414, 3531, 3603, 3675, 3738, 3776, 3813},
|
||||
{3272, 3398, 3514, 3586, 3658, 3720, 3757, 3795},
|
||||
{3240, 3365, 3480, 3551, 3622, 3684, 3721, 3758},
|
||||
{3224, 3348, 3463, 3533, 3604, 3666, 3702, 3739},
|
||||
{3221, 3344, 3459, 3530, 3600, 3662, 3695, 3728},
|
||||
{3216, 3340, 3454, 3525, 3595, 3657, 3686, 3715},
|
||||
{3212, 3335, 3449, 3520, 3590, 3652, 3677, 3703},
|
||||
{3203, 3326, 3440, 3510, 3580, 3642, 3664, 3686},
|
||||
{3185, 3307, 3420, 3490, 3560, 3621, 3639, 3657},
|
||||
{3176, 3298, 3411, 3481, 3550, 3611, 3626, 3640},
|
||||
{3151, 3272, 3384, 3453, 3522, 3583, 3593, 3604},
|
||||
{3106, 3225, 3335, 3446, 3472, 3531, 3538, 3545},
|
||||
{3021, 3217, 3245, 3417, 3429, 3435, 3439, 3442},
|
||||
{3000, 3000, 3000, 3000, 3000, 3000, 3000, 3000}
|
||||
},
|
||||
};
|
||||
|
||||
struct pm8921_bms_battery_data palladium_1500_data = {
|
||||
.fcc = 1500,
|
||||
.fcc_temp_lut = &palladium_1500_fcc_temp,
|
||||
.fcc_sf_lut = &palladium_1500_fcc_sf,
|
||||
.pc_temp_ocv_lut = &palladium_1500_pc_temp_ocv,
|
||||
.pc_sf_lut = &palladium_1500_pc_sf,
|
||||
.rbatt_sf_lut = &palladium_1500_rbatt_sf,
|
||||
.default_rbatt_mohm = 254,
|
||||
.delta_rbatt_mohm = 60,
|
||||
};
|
||||
697
arch/arm/mach-msm/board-8064-camera.c
Normal file
697
arch/arm/mach-msm/board-8064-camera.c
Normal file
@@ -0,0 +1,697 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <mach/board.h>
|
||||
#include <mach/msm_bus_board.h>
|
||||
#include <mach/gpiomux.h>
|
||||
|
||||
#include "devices.h"
|
||||
#include "board-8064.h"
|
||||
|
||||
#ifdef CONFIG_MSM_CAMERA
|
||||
|
||||
static struct gpiomux_setting cam_settings[] = {
|
||||
{
|
||||
.func = GPIOMUX_FUNC_GPIO, /*suspend*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_1, /*active 1*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_GPIO, /*active 2*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_2, /*active 3*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_5, /*active 4*/
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_6, /*active 5*/
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_2, /*active 6*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_3, /*active 7*/
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_GPIO, /*i2c suspend*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_KEEPER,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_9, /*active 9*/
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
{
|
||||
.func = GPIOMUX_FUNC_A, /*active 10*/
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
{
|
||||
.func = GPIOMUX_FUNC_6, /*active 11*/
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
{
|
||||
.func = GPIOMUX_FUNC_4, /*active 12*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config apq8064_cam_common_configs[] = {
|
||||
{
|
||||
.gpio = 1,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[2],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 2,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[12],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 3,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[2],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 4,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[3],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 5,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[1],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 34,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[2],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 107,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[2],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 10,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[9],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[8],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 11,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[10],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[8],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 12,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[11],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[8],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 13,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[11],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[8],
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
#define VFE_CAMIF_TIMER1_GPIO 3
|
||||
#define VFE_CAMIF_TIMER2_GPIO 1
|
||||
|
||||
static struct msm_camera_sensor_flash_src msm_flash_src = {
|
||||
.flash_sr_type = MSM_CAMERA_FLASH_SRC_EXT,
|
||||
._fsrc.ext_driver_src.led_en = VFE_CAMIF_TIMER1_GPIO,
|
||||
._fsrc.ext_driver_src.led_flash_en = VFE_CAMIF_TIMER2_GPIO,
|
||||
._fsrc.ext_driver_src.flash_id = MAM_CAMERA_EXT_LED_FLASH_SC628A,
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config apq8064_cam_2d_configs[] = {
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors cam_init_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors cam_preview_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 27648000,
|
||||
.ib = 110592000,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors cam_video_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 140451840,
|
||||
.ib = 561807360,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 206807040,
|
||||
.ib = 488816640,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors cam_snapshot_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 274423680,
|
||||
.ib = 1097694720,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 540000000,
|
||||
.ib = 1350000000,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors cam_zsl_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 302071680,
|
||||
.ib = 1208286720,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 540000000,
|
||||
.ib = 1350000000,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_paths cam_bus_client_config[] = {
|
||||
{
|
||||
ARRAY_SIZE(cam_init_vectors),
|
||||
cam_init_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(cam_preview_vectors),
|
||||
cam_preview_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(cam_video_vectors),
|
||||
cam_video_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(cam_snapshot_vectors),
|
||||
cam_snapshot_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(cam_zsl_vectors),
|
||||
cam_zsl_vectors,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_scale_pdata cam_bus_client_pdata = {
|
||||
cam_bus_client_config,
|
||||
ARRAY_SIZE(cam_bus_client_config),
|
||||
.name = "msm_camera",
|
||||
};
|
||||
|
||||
static struct msm_camera_device_platform_data msm_camera_csi_device_data[] = {
|
||||
{
|
||||
.csid_core = 0,
|
||||
.is_csiphy = 1,
|
||||
.is_csid = 1,
|
||||
.is_ispif = 1,
|
||||
.is_vpe = 1,
|
||||
.cam_bus_scale_table = &cam_bus_client_pdata,
|
||||
},
|
||||
{
|
||||
.csid_core = 1,
|
||||
.is_csiphy = 1,
|
||||
.is_csid = 1,
|
||||
.is_ispif = 1,
|
||||
.is_vpe = 1,
|
||||
.cam_bus_scale_table = &cam_bus_client_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct camera_vreg_t apq_8064_back_cam_vreg[] = {
|
||||
{"cam_vdig", REG_LDO, 1200000, 1200000, 105000},
|
||||
{"cam_vio", REG_VS, 0, 0, 0},
|
||||
{"cam_vana", REG_LDO, 2800000, 2850000, 85600},
|
||||
{"cam_vaf", REG_LDO, 2800000, 2850000, 300000},
|
||||
};
|
||||
|
||||
static struct camera_vreg_t apq_8064_front_cam_vreg[] = {
|
||||
{"cam_vio", REG_VS, 0, 0, 0},
|
||||
{"cam_vana", REG_LDO, 2800000, 2850000, 85600},
|
||||
{"cam_vdig", REG_LDO, 1200000, 1200000, 105000},
|
||||
{"cam_vaf", REG_LDO, 2800000, 2850000, 300000},
|
||||
};
|
||||
|
||||
#define CAML_RSTN PM8921_GPIO_PM_TO_SYS(28)
|
||||
#define CAMR_RSTN 34
|
||||
|
||||
static struct gpio apq8064_common_cam_gpio[] = {
|
||||
};
|
||||
|
||||
static struct gpio apq8064_back_cam_gpio[] = {
|
||||
{5, GPIOF_DIR_IN, "CAMIF_MCLK"},
|
||||
{CAML_RSTN, GPIOF_DIR_OUT, "CAM_RESET"},
|
||||
};
|
||||
|
||||
static struct msm_gpio_set_tbl apq8064_back_cam_gpio_set_tbl[] = {
|
||||
{CAML_RSTN, GPIOF_OUT_INIT_LOW, 10000},
|
||||
{CAML_RSTN, GPIOF_OUT_INIT_HIGH, 10000},
|
||||
};
|
||||
|
||||
static struct msm_camera_gpio_conf apq8064_back_cam_gpio_conf = {
|
||||
.cam_gpiomux_conf_tbl = apq8064_cam_2d_configs,
|
||||
.cam_gpiomux_conf_tbl_size = ARRAY_SIZE(apq8064_cam_2d_configs),
|
||||
.cam_gpio_common_tbl = apq8064_common_cam_gpio,
|
||||
.cam_gpio_common_tbl_size = ARRAY_SIZE(apq8064_common_cam_gpio),
|
||||
.cam_gpio_req_tbl = apq8064_back_cam_gpio,
|
||||
.cam_gpio_req_tbl_size = ARRAY_SIZE(apq8064_back_cam_gpio),
|
||||
.cam_gpio_set_tbl = apq8064_back_cam_gpio_set_tbl,
|
||||
.cam_gpio_set_tbl_size = ARRAY_SIZE(apq8064_back_cam_gpio_set_tbl),
|
||||
};
|
||||
|
||||
static struct gpio apq8064_front_cam_gpio[] = {
|
||||
{4, GPIOF_DIR_IN, "CAMIF_MCLK"},
|
||||
{12, GPIOF_DIR_IN, "CAMIF_I2C_DATA"},
|
||||
{13, GPIOF_DIR_IN, "CAMIF_I2C_CLK"},
|
||||
{CAMR_RSTN, GPIOF_DIR_OUT, "CAM_RESET"},
|
||||
};
|
||||
|
||||
static struct msm_gpio_set_tbl apq8064_front_cam_gpio_set_tbl[] = {
|
||||
{CAMR_RSTN, GPIOF_OUT_INIT_LOW, 10000},
|
||||
{CAMR_RSTN, GPIOF_OUT_INIT_HIGH, 10000},
|
||||
};
|
||||
|
||||
static struct msm_camera_gpio_conf apq8064_front_cam_gpio_conf = {
|
||||
.cam_gpiomux_conf_tbl = apq8064_cam_2d_configs,
|
||||
.cam_gpiomux_conf_tbl_size = ARRAY_SIZE(apq8064_cam_2d_configs),
|
||||
.cam_gpio_common_tbl = apq8064_common_cam_gpio,
|
||||
.cam_gpio_common_tbl_size = ARRAY_SIZE(apq8064_common_cam_gpio),
|
||||
.cam_gpio_req_tbl = apq8064_front_cam_gpio,
|
||||
.cam_gpio_req_tbl_size = ARRAY_SIZE(apq8064_front_cam_gpio),
|
||||
.cam_gpio_set_tbl = apq8064_front_cam_gpio_set_tbl,
|
||||
.cam_gpio_set_tbl_size = ARRAY_SIZE(apq8064_front_cam_gpio_set_tbl),
|
||||
};
|
||||
|
||||
static struct msm_camera_i2c_conf apq8064_back_cam_i2c_conf = {
|
||||
.use_i2c_mux = 1,
|
||||
.mux_dev = &msm8960_device_i2c_mux_gsbi4,
|
||||
.i2c_mux_mode = MODE_L,
|
||||
};
|
||||
|
||||
static struct i2c_board_info msm_act_main_cam_i2c_info = {
|
||||
I2C_BOARD_INFO("msm_actuator", 0x11),
|
||||
};
|
||||
|
||||
static struct msm_actuator_info msm_act_main_cam_0_info = {
|
||||
.board_info = &msm_act_main_cam_i2c_info,
|
||||
.cam_name = MSM_ACTUATOR_MAIN_CAM_0,
|
||||
.bus_id = APQ_8064_GSBI4_QUP_I2C_BUS_ID,
|
||||
.vcm_pwd = 0,
|
||||
.vcm_enable = 0,
|
||||
};
|
||||
|
||||
static struct i2c_board_info msm_act_main_cam1_i2c_info = {
|
||||
I2C_BOARD_INFO("msm_actuator", 0x18),
|
||||
};
|
||||
|
||||
static struct msm_actuator_info msm_act_main_cam_1_info = {
|
||||
.board_info = &msm_act_main_cam1_i2c_info,
|
||||
.cam_name = MSM_ACTUATOR_MAIN_CAM_1,
|
||||
.bus_id = APQ_8064_GSBI4_QUP_I2C_BUS_ID,
|
||||
.vcm_pwd = 0,
|
||||
.vcm_enable = 0,
|
||||
};
|
||||
|
||||
|
||||
static struct msm_camera_i2c_conf apq8064_front_cam_i2c_conf = {
|
||||
.use_i2c_mux = 1,
|
||||
.mux_dev = &msm8960_device_i2c_mux_gsbi4,
|
||||
.i2c_mux_mode = MODE_L,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_flash_data flash_imx074 = {
|
||||
.flash_type = MSM_CAMERA_FLASH_LED,
|
||||
.flash_src = &msm_flash_src
|
||||
};
|
||||
|
||||
static struct msm_camera_csi_lane_params imx074_csi_lane_params = {
|
||||
.csi_lane_assign = 0xE4,
|
||||
.csi_lane_mask = 0xF,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_platform_info sensor_board_info_imx074 = {
|
||||
.mount_angle = 90,
|
||||
.cam_vreg = apq_8064_back_cam_vreg,
|
||||
.num_vreg = ARRAY_SIZE(apq_8064_back_cam_vreg),
|
||||
.gpio_conf = &apq8064_back_cam_gpio_conf,
|
||||
.i2c_conf = &apq8064_back_cam_i2c_conf,
|
||||
.csi_lane_params = &imx074_csi_lane_params,
|
||||
};
|
||||
|
||||
static struct i2c_board_info imx074_eeprom_i2c_info = {
|
||||
I2C_BOARD_INFO("imx074_eeprom", 0x34 << 1),
|
||||
};
|
||||
|
||||
static struct msm_eeprom_info imx074_eeprom_info = {
|
||||
.board_info = &imx074_eeprom_i2c_info,
|
||||
.bus_id = APQ_8064_GSBI4_QUP_I2C_BUS_ID,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_info msm_camera_sensor_imx074_data = {
|
||||
.sensor_name = "imx074",
|
||||
.pdata = &msm_camera_csi_device_data[0],
|
||||
.flash_data = &flash_imx074,
|
||||
.sensor_platform_info = &sensor_board_info_imx074,
|
||||
.csi_if = 1,
|
||||
.camera_type = BACK_CAMERA_2D,
|
||||
.sensor_type = BAYER_SENSOR,
|
||||
.actuator_info = &msm_act_main_cam_0_info,
|
||||
.eeprom_info = &imx074_eeprom_info,
|
||||
};
|
||||
|
||||
static struct msm_camera_csi_lane_params imx091_csi_lane_params = {
|
||||
.csi_lane_assign = 0xE4,
|
||||
.csi_lane_mask = 0xF,
|
||||
};
|
||||
|
||||
static struct camera_vreg_t apq_8064_imx091_vreg[] = {
|
||||
{"cam_vana", REG_LDO, 2800000, 2850000, 85600},
|
||||
{"cam_vaf", REG_LDO, 2800000, 2850000, 300000},
|
||||
{"cam_vdig", REG_LDO, 1200000, 1200000, 105000},
|
||||
{"cam_vio", REG_VS, 0, 0, 0},
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_flash_data flash_imx091 = {
|
||||
.flash_type = MSM_CAMERA_FLASH_NONE,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_platform_info sensor_board_info_imx091 = {
|
||||
.mount_angle = 0,
|
||||
.cam_vreg = apq_8064_imx091_vreg,
|
||||
.num_vreg = ARRAY_SIZE(apq_8064_imx091_vreg),
|
||||
.gpio_conf = &apq8064_back_cam_gpio_conf,
|
||||
.i2c_conf = &apq8064_back_cam_i2c_conf,
|
||||
.csi_lane_params = &imx091_csi_lane_params,
|
||||
};
|
||||
|
||||
static struct i2c_board_info imx091_eeprom_i2c_info = {
|
||||
I2C_BOARD_INFO("imx091_eeprom", 0x21),
|
||||
};
|
||||
|
||||
static struct msm_eeprom_info imx091_eeprom_info = {
|
||||
.board_info = &imx091_eeprom_i2c_info,
|
||||
.bus_id = APQ_8064_GSBI4_QUP_I2C_BUS_ID,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_info msm_camera_sensor_imx091_data = {
|
||||
.sensor_name = "imx091",
|
||||
.pdata = &msm_camera_csi_device_data[0],
|
||||
.flash_data = &flash_imx091,
|
||||
.sensor_platform_info = &sensor_board_info_imx091,
|
||||
.csi_if = 1,
|
||||
.camera_type = BACK_CAMERA_2D,
|
||||
.sensor_type = BAYER_SENSOR,
|
||||
.actuator_info = &msm_act_main_cam_1_info,
|
||||
.eeprom_info = &imx091_eeprom_info,
|
||||
};
|
||||
|
||||
static struct camera_vreg_t apq_8064_s5k3l1yx_vreg[] = {
|
||||
{"cam_vdig", REG_LDO, 1200000, 1200000, 105000},
|
||||
{"cam_vana", REG_LDO, 2800000, 2850000, 85600},
|
||||
{"cam_vio", REG_VS, 0, 0, 0},
|
||||
{"cam_vaf", REG_LDO, 2800000, 2850000, 300000},
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_flash_data flash_s5k3l1yx = {
|
||||
.flash_type = MSM_CAMERA_FLASH_NONE,
|
||||
};
|
||||
|
||||
static struct msm_camera_csi_lane_params s5k3l1yx_csi_lane_params = {
|
||||
.csi_lane_assign = 0xE4,
|
||||
.csi_lane_mask = 0xF,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_platform_info sensor_board_info_s5k3l1yx = {
|
||||
.mount_angle = 90,
|
||||
.cam_vreg = apq_8064_s5k3l1yx_vreg,
|
||||
.num_vreg = ARRAY_SIZE(apq_8064_s5k3l1yx_vreg),
|
||||
.gpio_conf = &apq8064_back_cam_gpio_conf,
|
||||
.i2c_conf = &apq8064_back_cam_i2c_conf,
|
||||
.csi_lane_params = &s5k3l1yx_csi_lane_params,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_info msm_camera_sensor_s5k3l1yx_data = {
|
||||
.sensor_name = "s5k3l1yx",
|
||||
.pdata = &msm_camera_csi_device_data[0],
|
||||
.flash_data = &flash_s5k3l1yx,
|
||||
.sensor_platform_info = &sensor_board_info_s5k3l1yx,
|
||||
.csi_if = 1,
|
||||
.camera_type = BACK_CAMERA_2D,
|
||||
.sensor_type = BAYER_SENSOR,
|
||||
};
|
||||
|
||||
static struct camera_vreg_t apq_8064_mt9m114_vreg[] = {
|
||||
{"cam_vio", REG_VS, 0, 0, 0},
|
||||
{"cam_vdig", REG_LDO, 1200000, 1200000, 105000},
|
||||
{"cam_vana", REG_LDO, 2800000, 2850000, 85600},
|
||||
{"cam_vaf", REG_LDO, 2800000, 2850000, 300000},
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_flash_data flash_mt9m114 = {
|
||||
.flash_type = MSM_CAMERA_FLASH_NONE
|
||||
};
|
||||
|
||||
static struct msm_camera_csi_lane_params mt9m114_csi_lane_params = {
|
||||
.csi_lane_assign = 0xE4,
|
||||
.csi_lane_mask = 0x1,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_platform_info sensor_board_info_mt9m114 = {
|
||||
.mount_angle = 90,
|
||||
.cam_vreg = apq_8064_mt9m114_vreg,
|
||||
.num_vreg = ARRAY_SIZE(apq_8064_mt9m114_vreg),
|
||||
.gpio_conf = &apq8064_front_cam_gpio_conf,
|
||||
.i2c_conf = &apq8064_front_cam_i2c_conf,
|
||||
.csi_lane_params = &mt9m114_csi_lane_params,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_info msm_camera_sensor_mt9m114_data = {
|
||||
.sensor_name = "mt9m114",
|
||||
.pdata = &msm_camera_csi_device_data[1],
|
||||
.flash_data = &flash_mt9m114,
|
||||
.sensor_platform_info = &sensor_board_info_mt9m114,
|
||||
.csi_if = 1,
|
||||
.camera_type = FRONT_CAMERA_2D,
|
||||
.sensor_type = YUV_SENSOR,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_flash_data flash_ov2720 = {
|
||||
.flash_type = MSM_CAMERA_FLASH_NONE,
|
||||
};
|
||||
|
||||
static struct msm_camera_csi_lane_params ov2720_csi_lane_params = {
|
||||
.csi_lane_assign = 0xE4,
|
||||
.csi_lane_mask = 0x3,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_platform_info sensor_board_info_ov2720 = {
|
||||
.mount_angle = 0,
|
||||
.cam_vreg = apq_8064_front_cam_vreg,
|
||||
.num_vreg = ARRAY_SIZE(apq_8064_front_cam_vreg),
|
||||
.gpio_conf = &apq8064_front_cam_gpio_conf,
|
||||
.i2c_conf = &apq8064_front_cam_i2c_conf,
|
||||
.csi_lane_params = &ov2720_csi_lane_params,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_info msm_camera_sensor_ov2720_data = {
|
||||
.sensor_name = "ov2720",
|
||||
.pdata = &msm_camera_csi_device_data[1],
|
||||
.flash_data = &flash_ov2720,
|
||||
.sensor_platform_info = &sensor_board_info_ov2720,
|
||||
.csi_if = 1,
|
||||
.camera_type = FRONT_CAMERA_2D,
|
||||
.sensor_type = BAYER_SENSOR,
|
||||
};
|
||||
|
||||
static struct platform_device msm_camera_server = {
|
||||
.name = "msm_cam_server",
|
||||
.id = 0,
|
||||
};
|
||||
|
||||
void __init apq8064_init_cam(void)
|
||||
{
|
||||
msm_gpiomux_install(apq8064_cam_common_configs,
|
||||
ARRAY_SIZE(apq8064_cam_common_configs));
|
||||
|
||||
if (machine_is_apq8064_cdp()) {
|
||||
sensor_board_info_imx074.mount_angle = 0;
|
||||
sensor_board_info_mt9m114.mount_angle = 0;
|
||||
} else if (machine_is_apq8064_liquid())
|
||||
sensor_board_info_imx074.mount_angle = 180;
|
||||
|
||||
platform_device_register(&msm_camera_server);
|
||||
platform_device_register(&msm8960_device_i2c_mux_gsbi4);
|
||||
platform_device_register(&msm8960_device_csiphy0);
|
||||
platform_device_register(&msm8960_device_csiphy1);
|
||||
platform_device_register(&msm8960_device_csid0);
|
||||
platform_device_register(&msm8960_device_csid1);
|
||||
platform_device_register(&msm8960_device_ispif);
|
||||
platform_device_register(&msm8960_device_vfe);
|
||||
platform_device_register(&msm8960_device_vpe);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_I2C
|
||||
static struct i2c_board_info apq8064_camera_i2c_boardinfo[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("imx074", 0x1A),
|
||||
.platform_data = &msm_camera_sensor_imx074_data,
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("mt9m114", 0x48),
|
||||
.platform_data = &msm_camera_sensor_mt9m114_data,
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("ov2720", 0x6C),
|
||||
.platform_data = &msm_camera_sensor_ov2720_data,
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("sc628a", 0x6E),
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("imx091", 0x34),
|
||||
.platform_data = &msm_camera_sensor_imx091_data,
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("s5k3l1yx", 0x20),
|
||||
.platform_data = &msm_camera_sensor_s5k3l1yx_data,
|
||||
},
|
||||
};
|
||||
|
||||
struct msm_camera_board_info apq8064_camera_board_info = {
|
||||
.board_info = apq8064_camera_i2c_boardinfo,
|
||||
.num_i2c_board_info = ARRAY_SIZE(apq8064_camera_i2c_boardinfo),
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
995
arch/arm/mach-msm/board-8064-display.c
Normal file
995
arch/arm/mach-msm/board-8064-display.c
Normal file
@@ -0,0 +1,995 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/ion.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <mach/msm_memtypes.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/gpiomux.h>
|
||||
#include <mach/ion.h>
|
||||
#include <mach/msm_bus_board.h>
|
||||
#include <mach/socinfo.h>
|
||||
|
||||
#include "devices.h"
|
||||
#include "board-8064.h"
|
||||
|
||||
#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
|
||||
/* prim = 1366 x 768 x 3(bpp) x 3(pages) */
|
||||
#define MSM_FB_PRIM_BUF_SIZE roundup(1920 * 1088 * 4 * 3, 0x10000)
|
||||
#else
|
||||
/* prim = 1366 x 768 x 3(bpp) x 2(pages) */
|
||||
#define MSM_FB_PRIM_BUF_SIZE roundup(1920 * 1088 * 4 * 2, 0x10000)
|
||||
#endif
|
||||
|
||||
#define MSM_FB_SIZE roundup(MSM_FB_PRIM_BUF_SIZE, 4096)
|
||||
|
||||
#ifdef CONFIG_FB_MSM_OVERLAY0_WRITEBACK
|
||||
#define MSM_FB_OVERLAY0_WRITEBACK_SIZE roundup((1376 * 768 * 3 * 2), 4096)
|
||||
#else
|
||||
#define MSM_FB_OVERLAY0_WRITEBACK_SIZE (0)
|
||||
#endif /* CONFIG_FB_MSM_OVERLAY0_WRITEBACK */
|
||||
|
||||
#ifdef CONFIG_FB_MSM_OVERLAY1_WRITEBACK
|
||||
#define MSM_FB_OVERLAY1_WRITEBACK_SIZE roundup((1920 * 1088 * 3 * 2), 4096)
|
||||
#else
|
||||
#define MSM_FB_OVERLAY1_WRITEBACK_SIZE (0)
|
||||
#endif /* CONFIG_FB_MSM_OVERLAY1_WRITEBACK */
|
||||
|
||||
|
||||
static struct resource msm_fb_resources[] = {
|
||||
{
|
||||
.flags = IORESOURCE_DMA,
|
||||
}
|
||||
};
|
||||
|
||||
#define LVDS_CHIMEI_PANEL_NAME "lvds_chimei_wxga"
|
||||
#define MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME "mipi_video_toshiba_wsvga"
|
||||
#define MIPI_VIDEO_CHIMEI_WXGA_PANEL_NAME "mipi_video_chimei_wxga"
|
||||
#define HDMI_PANEL_NAME "hdmi_msm"
|
||||
#define TVOUT_PANEL_NAME "tvout_msm"
|
||||
|
||||
#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
|
||||
static unsigned char hdmi_is_primary = 1;
|
||||
#else
|
||||
static unsigned char hdmi_is_primary;
|
||||
#endif
|
||||
|
||||
unsigned char apq8064_hdmi_as_primary_selected(void)
|
||||
{
|
||||
return hdmi_is_primary;
|
||||
}
|
||||
|
||||
static void set_mdp_clocks_for_wuxga(void);
|
||||
|
||||
static int msm_fb_detect_panel(const char *name)
|
||||
{
|
||||
u32 version;
|
||||
if (machine_is_apq8064_liquid()) {
|
||||
version = socinfo_get_platform_version();
|
||||
if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
|
||||
(SOCINFO_VERSION_MINOR(version) == 1)) {
|
||||
if (!strncmp(name, MIPI_VIDEO_CHIMEI_WXGA_PANEL_NAME,
|
||||
strnlen(MIPI_VIDEO_CHIMEI_WXGA_PANEL_NAME,
|
||||
PANEL_NAME_MAX_LEN)))
|
||||
return 0;
|
||||
} else {
|
||||
if (!strncmp(name, LVDS_CHIMEI_PANEL_NAME,
|
||||
strnlen(LVDS_CHIMEI_PANEL_NAME,
|
||||
PANEL_NAME_MAX_LEN)))
|
||||
return 0;
|
||||
}
|
||||
} else if (machine_is_apq8064_mtp()) {
|
||||
if (!strncmp(name, MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
|
||||
strnlen(MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
|
||||
PANEL_NAME_MAX_LEN)))
|
||||
return 0;
|
||||
} else if (machine_is_apq8064_cdp() ||
|
||||
machine_is_mpq8064_dtv()) {
|
||||
if (!strncmp(name, LVDS_CHIMEI_PANEL_NAME,
|
||||
strnlen(LVDS_CHIMEI_PANEL_NAME,
|
||||
PANEL_NAME_MAX_LEN)))
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!strncmp(name, HDMI_PANEL_NAME,
|
||||
strnlen(HDMI_PANEL_NAME,
|
||||
PANEL_NAME_MAX_LEN))) {
|
||||
if (apq8064_hdmi_as_primary_selected())
|
||||
set_mdp_clocks_for_wuxga();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static struct msm_fb_platform_data msm_fb_pdata = {
|
||||
.detect_client = msm_fb_detect_panel,
|
||||
};
|
||||
|
||||
static struct platform_device msm_fb_device = {
|
||||
.name = "msm_fb",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(msm_fb_resources),
|
||||
.resource = msm_fb_resources,
|
||||
.dev.platform_data = &msm_fb_pdata,
|
||||
};
|
||||
|
||||
void __init apq8064_allocate_fb_region(void)
|
||||
{
|
||||
void *addr;
|
||||
unsigned long size;
|
||||
|
||||
size = MSM_FB_SIZE;
|
||||
addr = alloc_bootmem_align(size, 0x1000);
|
||||
msm_fb_resources[0].start = __pa(addr);
|
||||
msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
|
||||
pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
|
||||
size, addr, __pa(addr));
|
||||
}
|
||||
|
||||
#define MDP_VSYNC_GPIO 0
|
||||
|
||||
static struct msm_bus_vectors mdp_init_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors mdp_ui_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 216000000 * 2,
|
||||
.ib = 270000000 * 2,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors mdp_vga_vectors[] = {
|
||||
/* VGA and less video */
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 216000000 * 2,
|
||||
.ib = 270000000 * 2,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors mdp_720p_vectors[] = {
|
||||
/* 720p and less video */
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 230400000 * 2,
|
||||
.ib = 288000000 * 2,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors mdp_1080p_vectors[] = {
|
||||
/* 1080p and less video */
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 334080000 * 2,
|
||||
.ib = 417600000 * 2,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_paths mdp_bus_scale_usecases[] = {
|
||||
{
|
||||
ARRAY_SIZE(mdp_init_vectors),
|
||||
mdp_init_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(mdp_ui_vectors),
|
||||
mdp_ui_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(mdp_ui_vectors),
|
||||
mdp_ui_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(mdp_vga_vectors),
|
||||
mdp_vga_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(mdp_720p_vectors),
|
||||
mdp_720p_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(mdp_1080p_vectors),
|
||||
mdp_1080p_vectors,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_scale_pdata mdp_bus_scale_pdata = {
|
||||
mdp_bus_scale_usecases,
|
||||
ARRAY_SIZE(mdp_bus_scale_usecases),
|
||||
.name = "mdp",
|
||||
};
|
||||
|
||||
static int mdp_core_clk_rate_table[] = {
|
||||
59080000,
|
||||
128000000,
|
||||
160000000,
|
||||
200000000,
|
||||
};
|
||||
|
||||
static struct msm_panel_common_pdata mdp_pdata = {
|
||||
.gpio = MDP_VSYNC_GPIO,
|
||||
.mdp_core_clk_rate = 59080000,
|
||||
.mdp_core_clk_table = mdp_core_clk_rate_table,
|
||||
.num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
|
||||
.mdp_bus_scale_table = &mdp_bus_scale_pdata,
|
||||
.mdp_rev = MDP_REV_44,
|
||||
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
|
||||
.mem_hid = BIT(ION_CP_MM_HEAP_ID),
|
||||
#else
|
||||
.mem_hid = MEMTYPE_EBI1,
|
||||
#endif
|
||||
};
|
||||
|
||||
void __init apq8064_mdp_writeback(struct memtype_reserve* reserve_table)
|
||||
{
|
||||
mdp_pdata.ov0_wb_size = MSM_FB_OVERLAY0_WRITEBACK_SIZE;
|
||||
mdp_pdata.ov1_wb_size = MSM_FB_OVERLAY1_WRITEBACK_SIZE;
|
||||
#if defined(CONFIG_ANDROID_PMEM) && !defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
|
||||
reserve_table[mdp_pdata.mem_hid].size +=
|
||||
mdp_pdata.ov0_wb_size;
|
||||
reserve_table[mdp_pdata.mem_hid].size +=
|
||||
mdp_pdata.ov1_wb_size;
|
||||
#endif
|
||||
}
|
||||
|
||||
static struct resource hdmi_msm_resources[] = {
|
||||
{
|
||||
.name = "hdmi_msm_qfprom_addr",
|
||||
.start = 0x00700000,
|
||||
.end = 0x007060FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = "hdmi_msm_hdmi_addr",
|
||||
.start = 0x04A00000,
|
||||
.end = 0x04A00FFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = "hdmi_msm_irq",
|
||||
.start = HDMI_IRQ,
|
||||
.end = HDMI_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static int hdmi_enable_5v(int on);
|
||||
static int hdmi_core_power(int on, int show);
|
||||
static int hdmi_cec_power(int on);
|
||||
|
||||
static struct msm_hdmi_platform_data hdmi_msm_data = {
|
||||
.irq = HDMI_IRQ,
|
||||
.enable_5v = hdmi_enable_5v,
|
||||
.core_power = hdmi_core_power,
|
||||
.cec_power = hdmi_cec_power,
|
||||
};
|
||||
|
||||
static struct platform_device hdmi_msm_device = {
|
||||
.name = "hdmi_msm",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(hdmi_msm_resources),
|
||||
.resource = hdmi_msm_resources,
|
||||
.dev.platform_data = &hdmi_msm_data,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FB_MSM_WRITEBACK_MSM_PANEL
|
||||
static struct platform_device wfd_panel_device = {
|
||||
.name = "wfd_panel",
|
||||
.id = 0,
|
||||
.dev.platform_data = NULL,
|
||||
};
|
||||
|
||||
static struct platform_device wfd_device = {
|
||||
.name = "msm_wfd",
|
||||
.id = -1,
|
||||
};
|
||||
#endif
|
||||
|
||||
/* HDMI related GPIOs */
|
||||
#define HDMI_CEC_VAR_GPIO 69
|
||||
#define HDMI_DDC_CLK_GPIO 70
|
||||
#define HDMI_DDC_DATA_GPIO 71
|
||||
#define HDMI_HPD_GPIO 72
|
||||
|
||||
static bool dsi_power_on;
|
||||
static int mipi_dsi_panel_power(int on)
|
||||
{
|
||||
static struct regulator *reg_lvs7, *reg_l2, *reg_l11, *reg_ext_3p3v;
|
||||
static int gpio36, gpio25, gpio26, mpp3;
|
||||
int rc;
|
||||
|
||||
pr_debug("%s: on=%d\n", __func__, on);
|
||||
|
||||
if (!dsi_power_on) {
|
||||
reg_lvs7 = regulator_get(&msm_mipi_dsi1_device.dev,
|
||||
"dsi1_vddio");
|
||||
if (IS_ERR_OR_NULL(reg_lvs7)) {
|
||||
pr_err("could not get 8921_lvs7, rc = %ld\n",
|
||||
PTR_ERR(reg_lvs7));
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
reg_l2 = regulator_get(&msm_mipi_dsi1_device.dev,
|
||||
"dsi1_pll_vdda");
|
||||
if (IS_ERR_OR_NULL(reg_l2)) {
|
||||
pr_err("could not get 8921_l2, rc = %ld\n",
|
||||
PTR_ERR(reg_l2));
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
rc = regulator_set_voltage(reg_l2, 1200000, 1200000);
|
||||
if (rc) {
|
||||
pr_err("set_voltage l2 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
reg_l11 = regulator_get(&msm_mipi_dsi1_device.dev,
|
||||
"dsi1_avdd");
|
||||
if (IS_ERR(reg_l11)) {
|
||||
pr_err("could not get 8921_l11, rc = %ld\n",
|
||||
PTR_ERR(reg_l11));
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_set_voltage(reg_l11, 3000000, 3000000);
|
||||
if (rc) {
|
||||
pr_err("set_voltage l11 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (machine_is_apq8064_liquid()) {
|
||||
reg_ext_3p3v = regulator_get(&msm_mipi_dsi1_device.dev,
|
||||
"dsi1_vccs_3p3v");
|
||||
if (IS_ERR_OR_NULL(reg_ext_3p3v)) {
|
||||
pr_err("could not get reg_ext_3p3v, rc = %ld\n",
|
||||
PTR_ERR(reg_ext_3p3v));
|
||||
reg_ext_3p3v = NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
mpp3 = PM8921_MPP_PM_TO_SYS(3);
|
||||
rc = gpio_request(mpp3, "backlight_en");
|
||||
if (rc) {
|
||||
pr_err("request mpp3 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
gpio25 = PM8921_GPIO_PM_TO_SYS(25);
|
||||
rc = gpio_request(gpio25, "disp_rst_n");
|
||||
if (rc) {
|
||||
pr_err("request gpio 25 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
gpio26 = PM8921_GPIO_PM_TO_SYS(26);
|
||||
rc = gpio_request(gpio26, "pwm_backlight_ctrl");
|
||||
if (rc) {
|
||||
pr_err("request gpio 26 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
gpio36 = PM8921_GPIO_PM_TO_SYS(36); /* lcd1_pwr_en_n */
|
||||
rc = gpio_request(gpio36, "lcd1_pwr_en_n");
|
||||
if (rc) {
|
||||
pr_err("request gpio 36 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
dsi_power_on = true;
|
||||
}
|
||||
|
||||
if (on) {
|
||||
rc = regulator_enable(reg_lvs7);
|
||||
if (rc) {
|
||||
pr_err("enable lvs7 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
rc = regulator_set_optimum_mode(reg_l11, 110000);
|
||||
if (rc < 0) {
|
||||
pr_err("set_optimum_mode l11 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
rc = regulator_enable(reg_l11);
|
||||
if (rc) {
|
||||
pr_err("enable l11 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
rc = regulator_set_optimum_mode(reg_l2, 100000);
|
||||
if (rc < 0) {
|
||||
pr_err("set_optimum_mode l2 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
rc = regulator_enable(reg_l2);
|
||||
if (rc) {
|
||||
pr_err("enable l2 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (machine_is_apq8064_liquid()) {
|
||||
rc = regulator_enable(reg_ext_3p3v);
|
||||
if (rc) {
|
||||
pr_err("enable reg_ext_3p3v failed, rc=%d\n",
|
||||
rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
gpio_set_value_cansleep(mpp3, 1);
|
||||
}
|
||||
|
||||
gpio_set_value_cansleep(gpio36, 0);
|
||||
gpio_set_value_cansleep(gpio25, 1);
|
||||
} else {
|
||||
gpio_set_value_cansleep(gpio25, 0);
|
||||
gpio_set_value_cansleep(gpio36, 1);
|
||||
|
||||
if (machine_is_apq8064_liquid()) {
|
||||
gpio_set_value_cansleep(mpp3, 0);
|
||||
|
||||
rc = regulator_disable(reg_ext_3p3v);
|
||||
if (rc) {
|
||||
pr_err("disable reg_ext_3p3v failed, rc=%d\n",
|
||||
rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
rc = regulator_disable(reg_lvs7);
|
||||
if (rc) {
|
||||
pr_err("disable reg_lvs7 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_disable(reg_l2);
|
||||
if (rc) {
|
||||
pr_err("disable reg_l2 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct mipi_dsi_platform_data mipi_dsi_pdata = {
|
||||
.dsi_power_save = mipi_dsi_panel_power,
|
||||
};
|
||||
|
||||
static bool lvds_power_on;
|
||||
static int lvds_panel_power(int on)
|
||||
{
|
||||
static struct regulator *reg_lvs7, *reg_l2, *reg_ext_3p3v;
|
||||
static int gpio36, gpio26, mpp3;
|
||||
int rc;
|
||||
|
||||
pr_debug("%s: on=%d\n", __func__, on);
|
||||
|
||||
if (!lvds_power_on) {
|
||||
reg_lvs7 = regulator_get(&msm_lvds_device.dev,
|
||||
"lvds_vdda");
|
||||
if (IS_ERR_OR_NULL(reg_lvs7)) {
|
||||
pr_err("could not get 8921_lvs7, rc = %ld\n",
|
||||
PTR_ERR(reg_lvs7));
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
reg_l2 = regulator_get(&msm_lvds_device.dev,
|
||||
"lvds_pll_vdda");
|
||||
if (IS_ERR_OR_NULL(reg_l2)) {
|
||||
pr_err("could not get 8921_l2, rc = %ld\n",
|
||||
PTR_ERR(reg_l2));
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
rc = regulator_set_voltage(reg_l2, 1200000, 1200000);
|
||||
if (rc) {
|
||||
pr_err("set_voltage l2 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
reg_ext_3p3v = regulator_get(&msm_lvds_device.dev,
|
||||
"lvds_vccs_3p3v");
|
||||
if (IS_ERR_OR_NULL(reg_ext_3p3v)) {
|
||||
pr_err("could not get reg_ext_3p3v, rc = %ld\n",
|
||||
PTR_ERR(reg_ext_3p3v));
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
gpio26 = PM8921_GPIO_PM_TO_SYS(26);
|
||||
rc = gpio_request(gpio26, "pwm_backlight_ctrl");
|
||||
if (rc) {
|
||||
pr_err("request gpio 26 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
gpio36 = PM8921_GPIO_PM_TO_SYS(36); /* lcd1_pwr_en_n */
|
||||
rc = gpio_request(gpio36, "lcd1_pwr_en_n");
|
||||
if (rc) {
|
||||
pr_err("request gpio 36 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
mpp3 = PM8921_MPP_PM_TO_SYS(3);
|
||||
rc = gpio_request(mpp3, "backlight_en");
|
||||
if (rc) {
|
||||
pr_err("request mpp3 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
lvds_power_on = true;
|
||||
}
|
||||
|
||||
if (on) {
|
||||
rc = regulator_enable(reg_lvs7);
|
||||
if (rc) {
|
||||
pr_err("enable lvs7 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
rc = regulator_set_optimum_mode(reg_l2, 100000);
|
||||
if (rc < 0) {
|
||||
pr_err("set_optimum_mode l2 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
rc = regulator_enable(reg_l2);
|
||||
if (rc) {
|
||||
pr_err("enable l2 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
rc = regulator_enable(reg_ext_3p3v);
|
||||
if (rc) {
|
||||
pr_err("enable reg_ext_3p3v failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
gpio_set_value_cansleep(gpio36, 0);
|
||||
gpio_set_value_cansleep(mpp3, 1);
|
||||
} else {
|
||||
gpio_set_value_cansleep(mpp3, 0);
|
||||
gpio_set_value_cansleep(gpio36, 1);
|
||||
|
||||
rc = regulator_disable(reg_lvs7);
|
||||
if (rc) {
|
||||
pr_err("disable reg_lvs7 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_disable(reg_l2);
|
||||
if (rc) {
|
||||
pr_err("disable reg_l2 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_disable(reg_ext_3p3v);
|
||||
if (rc) {
|
||||
pr_err("disable reg_ext_3p3v failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lvds_pixel_remap(void)
|
||||
{
|
||||
if (machine_is_apq8064_cdp() ||
|
||||
machine_is_apq8064_liquid()) {
|
||||
u32 ver = socinfo_get_version();
|
||||
if ((SOCINFO_VERSION_MAJOR(ver) == 1) &&
|
||||
(SOCINFO_VERSION_MINOR(ver) == 0))
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct lcdc_platform_data lvds_pdata = {
|
||||
.lcdc_power_save = lvds_panel_power,
|
||||
.lvds_pixel_remap = lvds_pixel_remap
|
||||
};
|
||||
|
||||
#define LPM_CHANNEL 2
|
||||
static int lvds_chimei_gpio[] = {LPM_CHANNEL};
|
||||
|
||||
static struct lvds_panel_platform_data lvds_chimei_pdata = {
|
||||
.gpio = lvds_chimei_gpio,
|
||||
};
|
||||
|
||||
static struct platform_device lvds_chimei_panel_device = {
|
||||
.name = "lvds_chimei_wxga",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &lvds_chimei_pdata,
|
||||
}
|
||||
};
|
||||
|
||||
static int dsi2lvds_gpio[2] = {
|
||||
LPM_CHANNEL,/* Backlight PWM-ID=0 for PMIC-GPIO#24 */
|
||||
0x1F08 /* DSI2LVDS Bridge GPIO Output, mask=0x1f, out=0x08 */
|
||||
};
|
||||
static struct msm_panel_common_pdata mipi_dsi2lvds_pdata = {
|
||||
.gpio_num = dsi2lvds_gpio,
|
||||
};
|
||||
|
||||
static struct platform_device mipi_dsi2lvds_bridge_device = {
|
||||
.name = "mipi_tc358764",
|
||||
.id = 0,
|
||||
.dev.platform_data = &mipi_dsi2lvds_pdata,
|
||||
};
|
||||
|
||||
static int toshiba_gpio[] = {LPM_CHANNEL};
|
||||
static struct mipi_dsi_panel_platform_data toshiba_pdata = {
|
||||
.gpio = toshiba_gpio,
|
||||
};
|
||||
|
||||
static struct platform_device mipi_dsi_toshiba_panel_device = {
|
||||
.name = "mipi_toshiba",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &toshiba_pdata,
|
||||
}
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors dtv_bus_init_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors dtv_bus_def_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 566092800 * 2,
|
||||
.ib = 707616000 * 2,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_paths dtv_bus_scale_usecases[] = {
|
||||
{
|
||||
ARRAY_SIZE(dtv_bus_init_vectors),
|
||||
dtv_bus_init_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(dtv_bus_def_vectors),
|
||||
dtv_bus_def_vectors,
|
||||
},
|
||||
};
|
||||
static struct msm_bus_scale_pdata dtv_bus_scale_pdata = {
|
||||
dtv_bus_scale_usecases,
|
||||
ARRAY_SIZE(dtv_bus_scale_usecases),
|
||||
.name = "dtv",
|
||||
};
|
||||
|
||||
static struct lcdc_platform_data dtv_pdata = {
|
||||
.bus_scale_table = &dtv_bus_scale_pdata,
|
||||
};
|
||||
|
||||
static int hdmi_enable_5v(int on)
|
||||
{
|
||||
/* TBD: PM8921 regulator instead of 8901 */
|
||||
static struct regulator *reg_8921_hdmi_mvs; /* HDMI_5V */
|
||||
static int prev_on;
|
||||
int rc;
|
||||
|
||||
if (on == prev_on)
|
||||
return 0;
|
||||
|
||||
if (!reg_8921_hdmi_mvs) {
|
||||
reg_8921_hdmi_mvs = regulator_get(&hdmi_msm_device.dev,
|
||||
"hdmi_mvs");
|
||||
if (IS_ERR(reg_8921_hdmi_mvs)) {
|
||||
pr_err("could not get reg_8921_hdmi_mvs, rc = %ld\n",
|
||||
PTR_ERR(reg_8921_hdmi_mvs));
|
||||
reg_8921_hdmi_mvs = NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
if (on) {
|
||||
rc = regulator_enable(reg_8921_hdmi_mvs);
|
||||
if (rc) {
|
||||
pr_err("'%s' regulator enable failed, rc=%d\n",
|
||||
"8921_hdmi_mvs", rc);
|
||||
return rc;
|
||||
}
|
||||
pr_debug("%s(on): success\n", __func__);
|
||||
} else {
|
||||
rc = regulator_disable(reg_8921_hdmi_mvs);
|
||||
if (rc)
|
||||
pr_warning("'%s' regulator disable failed, rc=%d\n",
|
||||
"8921_hdmi_mvs", rc);
|
||||
pr_debug("%s(off): success\n", __func__);
|
||||
}
|
||||
|
||||
prev_on = on;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hdmi_core_power(int on, int show)
|
||||
{
|
||||
static struct regulator *reg_8921_lvs7, *reg_8921_s4, *reg_ext_3p3v;
|
||||
static int prev_on;
|
||||
int rc;
|
||||
int pmic_gpio14 = PM8921_GPIO_PM_TO_SYS(14);
|
||||
|
||||
if (on == prev_on)
|
||||
return 0;
|
||||
|
||||
/* TBD: PM8921 regulator instead of 8901 */
|
||||
if (!reg_ext_3p3v) {
|
||||
reg_ext_3p3v = regulator_get(&hdmi_msm_device.dev,
|
||||
"hdmi_mux_vdd");
|
||||
if (IS_ERR_OR_NULL(reg_ext_3p3v)) {
|
||||
pr_err("could not get reg_ext_3p3v, rc = %ld\n",
|
||||
PTR_ERR(reg_ext_3p3v));
|
||||
reg_ext_3p3v = NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
if (!reg_8921_lvs7) {
|
||||
reg_8921_lvs7 = regulator_get(&hdmi_msm_device.dev,
|
||||
"hdmi_vdda");
|
||||
if (IS_ERR(reg_8921_lvs7)) {
|
||||
pr_err("could not get reg_8921_lvs7, rc = %ld\n",
|
||||
PTR_ERR(reg_8921_lvs7));
|
||||
reg_8921_lvs7 = NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
if (!reg_8921_s4) {
|
||||
reg_8921_s4 = regulator_get(&hdmi_msm_device.dev,
|
||||
"hdmi_lvl_tsl");
|
||||
if (IS_ERR(reg_8921_s4)) {
|
||||
pr_err("could not get reg_8921_s4, rc = %ld\n",
|
||||
PTR_ERR(reg_8921_s4));
|
||||
reg_8921_s4 = NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_set_voltage(reg_8921_s4, 1800000, 1800000);
|
||||
if (rc) {
|
||||
pr_err("set_voltage failed for 8921_s4, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
if (on) {
|
||||
/*
|
||||
* Configure 3P3V_BOOST_EN as GPIO, 8mA drive strength,
|
||||
* pull none, out-high
|
||||
*/
|
||||
rc = regulator_set_optimum_mode(reg_ext_3p3v, 290000);
|
||||
if (rc < 0) {
|
||||
pr_err("set_optimum_mode ext_3p3v failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rc = regulator_enable(reg_ext_3p3v);
|
||||
if (rc) {
|
||||
pr_err("enable reg_ext_3p3v failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_enable(reg_8921_lvs7);
|
||||
if (rc) {
|
||||
pr_err("'%s' regulator enable failed, rc=%d\n",
|
||||
"hdmi_vdda", rc);
|
||||
return rc;
|
||||
}
|
||||
rc = regulator_enable(reg_8921_s4);
|
||||
if (rc) {
|
||||
pr_err("'%s' regulator enable failed, rc=%d\n",
|
||||
"hdmi_lvl_tsl", rc);
|
||||
return rc;
|
||||
}
|
||||
rc = gpio_request(HDMI_DDC_CLK_GPIO, "HDMI_DDC_CLK");
|
||||
if (rc) {
|
||||
pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
|
||||
"HDMI_DDC_CLK", HDMI_DDC_CLK_GPIO, rc);
|
||||
goto error1;
|
||||
}
|
||||
rc = gpio_request(HDMI_DDC_DATA_GPIO, "HDMI_DDC_DATA");
|
||||
if (rc) {
|
||||
pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
|
||||
"HDMI_DDC_DATA", HDMI_DDC_DATA_GPIO, rc);
|
||||
goto error2;
|
||||
}
|
||||
rc = gpio_request(HDMI_HPD_GPIO, "HDMI_HPD");
|
||||
if (rc) {
|
||||
pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
|
||||
"HDMI_HPD", HDMI_HPD_GPIO, rc);
|
||||
goto error3;
|
||||
}
|
||||
if (machine_is_apq8064_liquid()) {
|
||||
rc = gpio_request(pmic_gpio14, "PMIC_HDMI_MUX_SEL");
|
||||
if (rc) {
|
||||
pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
|
||||
"PMIC_HDMI_MUX_SEL", 14, rc);
|
||||
goto error4;
|
||||
}
|
||||
gpio_set_value_cansleep(pmic_gpio14, 0);
|
||||
}
|
||||
pr_debug("%s(on): success\n", __func__);
|
||||
} else {
|
||||
gpio_free(HDMI_DDC_CLK_GPIO);
|
||||
gpio_free(HDMI_DDC_DATA_GPIO);
|
||||
gpio_free(HDMI_HPD_GPIO);
|
||||
|
||||
if (machine_is_apq8064_liquid()) {
|
||||
gpio_set_value_cansleep(pmic_gpio14, 1);
|
||||
gpio_free(pmic_gpio14);
|
||||
}
|
||||
|
||||
rc = regulator_disable(reg_ext_3p3v);
|
||||
if (rc) {
|
||||
pr_err("disable reg_ext_3p3v failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_disable(reg_8921_lvs7);
|
||||
if (rc) {
|
||||
pr_err("disable reg_8921_l23 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_disable(reg_8921_s4);
|
||||
if (rc) {
|
||||
pr_err("disable reg_8921_s4 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
pr_debug("%s(off): success\n", __func__);
|
||||
}
|
||||
|
||||
prev_on = on;
|
||||
|
||||
return 0;
|
||||
|
||||
error4:
|
||||
gpio_free(HDMI_HPD_GPIO);
|
||||
error3:
|
||||
gpio_free(HDMI_DDC_DATA_GPIO);
|
||||
error2:
|
||||
gpio_free(HDMI_DDC_CLK_GPIO);
|
||||
error1:
|
||||
regulator_disable(reg_8921_lvs7);
|
||||
regulator_disable(reg_8921_s4);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int hdmi_cec_power(int on)
|
||||
{
|
||||
static int prev_on;
|
||||
int rc;
|
||||
|
||||
if (on == prev_on)
|
||||
return 0;
|
||||
|
||||
if (on) {
|
||||
rc = gpio_request(HDMI_CEC_VAR_GPIO, "HDMI_CEC_VAR");
|
||||
if (rc) {
|
||||
pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
|
||||
"HDMI_CEC_VAR", HDMI_CEC_VAR_GPIO, rc);
|
||||
goto error;
|
||||
}
|
||||
pr_debug("%s(on): success\n", __func__);
|
||||
} else {
|
||||
gpio_free(HDMI_CEC_VAR_GPIO);
|
||||
pr_debug("%s(off): success\n", __func__);
|
||||
}
|
||||
|
||||
prev_on = on;
|
||||
|
||||
return 0;
|
||||
error:
|
||||
return rc;
|
||||
}
|
||||
|
||||
void __init apq8064_init_fb(void)
|
||||
{
|
||||
platform_device_register(&msm_fb_device);
|
||||
platform_device_register(&lvds_chimei_panel_device);
|
||||
|
||||
#ifdef CONFIG_FB_MSM_WRITEBACK_MSM_PANEL
|
||||
platform_device_register(&wfd_panel_device);
|
||||
platform_device_register(&wfd_device);
|
||||
#endif
|
||||
|
||||
if (machine_is_apq8064_liquid())
|
||||
platform_device_register(&mipi_dsi2lvds_bridge_device);
|
||||
if (machine_is_apq8064_mtp())
|
||||
platform_device_register(&mipi_dsi_toshiba_panel_device);
|
||||
|
||||
msm_fb_register_device("mdp", &mdp_pdata);
|
||||
msm_fb_register_device("lvds", &lvds_pdata);
|
||||
msm_fb_register_device("mipi_dsi", &mipi_dsi_pdata);
|
||||
platform_device_register(&hdmi_msm_device);
|
||||
msm_fb_register_device("dtv", &dtv_pdata);
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MDP clocks to high frequency to avoid DSI underflow
|
||||
* when using high resolution 1200x1920 WUXGA panels
|
||||
*/
|
||||
static void set_mdp_clocks_for_wuxga(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
mdp_ui_vectors[0].ab = 2000000000;
|
||||
mdp_ui_vectors[0].ib = 2000000000;
|
||||
mdp_vga_vectors[0].ab = 2000000000;
|
||||
mdp_vga_vectors[0].ib = 2000000000;
|
||||
mdp_720p_vectors[0].ab = 2000000000;
|
||||
mdp_720p_vectors[0].ib = 2000000000;
|
||||
mdp_1080p_vectors[0].ab = 2000000000;
|
||||
mdp_1080p_vectors[0].ib = 2000000000;
|
||||
|
||||
mdp_pdata.mdp_core_clk_rate = 200000000;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mdp_core_clk_rate_table); i++)
|
||||
mdp_core_clk_rate_table[i] = 200000000;
|
||||
|
||||
if (apq8064_hdmi_as_primary_selected()) {
|
||||
dtv_bus_def_vectors[0].ab = 2000000000;
|
||||
dtv_bus_def_vectors[0].ib = 2000000000;
|
||||
}
|
||||
}
|
||||
|
||||
void __init apq8064_set_display_params(char *prim_panel, char *ext_panel)
|
||||
{
|
||||
/*
|
||||
* For certain MPQ boards, HDMI should be set as primary display
|
||||
* by default, with the flexibility to specify any other panel
|
||||
* as a primary panel through boot parameters.
|
||||
*/
|
||||
if (machine_is_mpq8064_hrd() || machine_is_mpq8064_cdp()) {
|
||||
pr_debug("HDMI is the primary display by default for MPQ\n");
|
||||
if (!strnlen(prim_panel, PANEL_NAME_MAX_LEN))
|
||||
strlcpy(msm_fb_pdata.prim_panel_name, HDMI_PANEL_NAME,
|
||||
PANEL_NAME_MAX_LEN);
|
||||
}
|
||||
|
||||
if (strnlen(prim_panel, PANEL_NAME_MAX_LEN)) {
|
||||
strlcpy(msm_fb_pdata.prim_panel_name, prim_panel,
|
||||
PANEL_NAME_MAX_LEN);
|
||||
pr_debug("msm_fb_pdata.prim_panel_name %s\n",
|
||||
msm_fb_pdata.prim_panel_name);
|
||||
|
||||
if (!strncmp((char *)msm_fb_pdata.prim_panel_name,
|
||||
HDMI_PANEL_NAME, strnlen(HDMI_PANEL_NAME,
|
||||
PANEL_NAME_MAX_LEN))) {
|
||||
pr_debug("HDMI is the primary display by"
|
||||
" boot parameter\n");
|
||||
hdmi_is_primary = 1;
|
||||
set_mdp_clocks_for_wuxga();
|
||||
}
|
||||
}
|
||||
if (strnlen(ext_panel, PANEL_NAME_MAX_LEN)) {
|
||||
strlcpy(msm_fb_pdata.ext_panel_name, ext_panel,
|
||||
PANEL_NAME_MAX_LEN);
|
||||
pr_debug("msm_fb_pdata.ext_panel_name %s\n",
|
||||
msm_fb_pdata.ext_panel_name);
|
||||
}
|
||||
}
|
||||
1262
arch/arm/mach-msm/board-8064-gpiomux.c
Normal file
1262
arch/arm/mach-msm/board-8064-gpiomux.c
Normal file
File diff suppressed because it is too large
Load Diff
251
arch/arm/mach-msm/board-8064-gpu.c
Normal file
251
arch/arm/mach-msm/board-8064-gpu.c
Normal file
@@ -0,0 +1,251 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/msm_kgsl.h>
|
||||
#include <mach/msm_bus_board.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/msm_dcvs.h>
|
||||
|
||||
#include "devices.h"
|
||||
#include "board-8064.h"
|
||||
|
||||
#ifdef CONFIG_MSM_DCVS
|
||||
static struct msm_dcvs_freq_entry grp3d_freq[] = {
|
||||
{0, 0, 333932},
|
||||
{0, 0, 497532},
|
||||
{0, 0, 707610},
|
||||
{0, 0, 844545},
|
||||
};
|
||||
|
||||
static struct msm_dcvs_core_info grp3d_core_info = {
|
||||
.freq_tbl = &grp3d_freq[0],
|
||||
.core_param = {
|
||||
.max_time_us = 100000,
|
||||
.num_freq = ARRAY_SIZE(grp3d_freq),
|
||||
},
|
||||
.algo_param = {
|
||||
.slack_time_us = 39000,
|
||||
.disable_pc_threshold = 86000,
|
||||
.ss_window_size = 1000000,
|
||||
.ss_util_pct = 95,
|
||||
.em_max_util_pct = 97,
|
||||
.ss_iobusy_conv = 100,
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_MSM_DCVS */
|
||||
|
||||
#ifdef CONFIG_MSM_BUS_SCALING
|
||||
static struct msm_bus_vectors grp3d_init_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_GRAPHICS_3D,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_GRAPHICS_3D_PORT1,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors grp3d_low_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_GRAPHICS_3D,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = KGSL_CONVERT_TO_MBPS(1000),
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_GRAPHICS_3D_PORT1,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = KGSL_CONVERT_TO_MBPS(1000),
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors grp3d_nominal_low_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_GRAPHICS_3D,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = KGSL_CONVERT_TO_MBPS(2000),
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_GRAPHICS_3D_PORT1,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = KGSL_CONVERT_TO_MBPS(2000),
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors grp3d_nominal_high_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_GRAPHICS_3D,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = KGSL_CONVERT_TO_MBPS(3200),
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_GRAPHICS_3D_PORT1,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = KGSL_CONVERT_TO_MBPS(3200),
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors grp3d_max_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_GRAPHICS_3D,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = KGSL_CONVERT_TO_MBPS(4264),
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_GRAPHICS_3D_PORT1,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = KGSL_CONVERT_TO_MBPS(4264),
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_paths grp3d_bus_scale_usecases[] = {
|
||||
{
|
||||
ARRAY_SIZE(grp3d_init_vectors),
|
||||
grp3d_init_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(grp3d_low_vectors),
|
||||
grp3d_low_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(grp3d_nominal_low_vectors),
|
||||
grp3d_nominal_low_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(grp3d_nominal_high_vectors),
|
||||
grp3d_nominal_high_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(grp3d_max_vectors),
|
||||
grp3d_max_vectors,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_scale_pdata grp3d_bus_scale_pdata = {
|
||||
grp3d_bus_scale_usecases,
|
||||
ARRAY_SIZE(grp3d_bus_scale_usecases),
|
||||
.name = "grp3d",
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct resource kgsl_3d0_resources[] = {
|
||||
{
|
||||
.name = KGSL_3D0_REG_MEMORY,
|
||||
.start = 0x04300000, /* GFX3D address */
|
||||
.end = 0x0431ffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = KGSL_3D0_IRQ,
|
||||
.start = GFX3D_IRQ,
|
||||
.end = GFX3D_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct kgsl_iommu_ctx kgsl_3d0_iommu0_ctxs[] = {
|
||||
{ "gfx3d_user", 0 },
|
||||
{ "gfx3d_priv", 1 },
|
||||
};
|
||||
|
||||
static const struct kgsl_iommu_ctx kgsl_3d0_iommu1_ctxs[] = {
|
||||
{ "gfx3d1_user", 0 },
|
||||
{ "gfx3d1_priv", 1 },
|
||||
};
|
||||
|
||||
static struct kgsl_device_iommu_data kgsl_3d0_iommu_data[] = {
|
||||
{
|
||||
.iommu_ctxs = kgsl_3d0_iommu0_ctxs,
|
||||
.iommu_ctx_count = ARRAY_SIZE(kgsl_3d0_iommu0_ctxs),
|
||||
.physstart = 0x07C00000,
|
||||
.physend = 0x07C00000 + SZ_1M - 1,
|
||||
},
|
||||
{
|
||||
.iommu_ctxs = kgsl_3d0_iommu1_ctxs,
|
||||
.iommu_ctx_count = ARRAY_SIZE(kgsl_3d0_iommu1_ctxs),
|
||||
.physstart = 0x07D00000,
|
||||
.physend = 0x07D00000 + SZ_1M - 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
|
||||
.pwrlevel = {
|
||||
{
|
||||
.gpu_freq = 400000000,
|
||||
.bus_freq = 4,
|
||||
.io_fraction = 0,
|
||||
},
|
||||
{
|
||||
.gpu_freq = 325000000,
|
||||
.bus_freq = 3,
|
||||
.io_fraction = 33,
|
||||
},
|
||||
{
|
||||
.gpu_freq = 200000000,
|
||||
.bus_freq = 2,
|
||||
.io_fraction = 100,
|
||||
},
|
||||
{
|
||||
.gpu_freq = 128000000,
|
||||
.bus_freq = 1,
|
||||
.io_fraction = 100,
|
||||
},
|
||||
{
|
||||
.gpu_freq = 27000000,
|
||||
.bus_freq = 0,
|
||||
},
|
||||
},
|
||||
.init_level = 1,
|
||||
.num_levels = 5,
|
||||
.set_grp_async = NULL,
|
||||
.idle_timeout = HZ/10,
|
||||
.nap_allowed = true,
|
||||
.clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM_IFACE,
|
||||
#ifdef CONFIG_MSM_BUS_SCALING
|
||||
.bus_scale_table = &grp3d_bus_scale_pdata,
|
||||
#endif
|
||||
.iommu_data = kgsl_3d0_iommu_data,
|
||||
.iommu_count = ARRAY_SIZE(kgsl_3d0_iommu_data),
|
||||
#ifdef CONFIG_MSM_DCVS
|
||||
.core_info = &grp3d_core_info,
|
||||
#endif
|
||||
};
|
||||
|
||||
struct platform_device device_kgsl_3d0 = {
|
||||
.name = "kgsl-3d0",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(kgsl_3d0_resources),
|
||||
.resource = kgsl_3d0_resources,
|
||||
.dev = {
|
||||
.platform_data = &kgsl_3d0_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
void __init apq8064_init_gpu(void)
|
||||
{
|
||||
platform_device_register(&device_kgsl_3d0);
|
||||
}
|
||||
444
arch/arm/mach-msm/board-8064-pmic.c
Normal file
444
arch/arm/mach-msm/board-8064-pmic.c
Normal file
@@ -0,0 +1,444 @@
|
||||
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/mfd/pm8xxx/pm8921.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/leds-pm8xxx.h>
|
||||
#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/mmc.h>
|
||||
#include <mach/msm_bus_board.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/gpiomux.h>
|
||||
#include <mach/restart.h>
|
||||
#include "devices.h"
|
||||
#include "board-8064.h"
|
||||
|
||||
struct pm8xxx_gpio_init {
|
||||
unsigned gpio;
|
||||
struct pm_gpio config;
|
||||
};
|
||||
|
||||
struct pm8xxx_mpp_init {
|
||||
unsigned mpp;
|
||||
struct pm8xxx_mpp_config_data config;
|
||||
};
|
||||
|
||||
#define PM8921_GPIO_INIT(_gpio, _dir, _buf, _val, _pull, _vin, _out_strength, \
|
||||
_func, _inv, _disable) \
|
||||
{ \
|
||||
.gpio = PM8921_GPIO_PM_TO_SYS(_gpio), \
|
||||
.config = { \
|
||||
.direction = _dir, \
|
||||
.output_buffer = _buf, \
|
||||
.output_value = _val, \
|
||||
.pull = _pull, \
|
||||
.vin_sel = _vin, \
|
||||
.out_strength = _out_strength, \
|
||||
.function = _func, \
|
||||
.inv_int_pol = _inv, \
|
||||
.disable_pin = _disable, \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PM8921_MPP_INIT(_mpp, _type, _level, _control) \
|
||||
{ \
|
||||
.mpp = PM8921_MPP_PM_TO_SYS(_mpp), \
|
||||
.config = { \
|
||||
.type = PM8XXX_MPP_TYPE_##_type, \
|
||||
.level = _level, \
|
||||
.control = PM8XXX_MPP_##_control, \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PM8821_MPP_INIT(_mpp, _type, _level, _control) \
|
||||
{ \
|
||||
.mpp = PM8821_MPP_PM_TO_SYS(_mpp), \
|
||||
.config = { \
|
||||
.type = PM8XXX_MPP_TYPE_##_type, \
|
||||
.level = _level, \
|
||||
.control = PM8XXX_MPP_##_control, \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PM8921_GPIO_DISABLE(_gpio) \
|
||||
PM8921_GPIO_INIT(_gpio, PM_GPIO_DIR_IN, 0, 0, 0, PM_GPIO_VIN_S4, \
|
||||
0, 0, 0, 1)
|
||||
|
||||
#define PM8921_GPIO_OUTPUT(_gpio, _val, _strength) \
|
||||
PM8921_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT, PM_GPIO_OUT_BUF_CMOS, _val, \
|
||||
PM_GPIO_PULL_NO, PM_GPIO_VIN_S4, \
|
||||
PM_GPIO_STRENGTH_##_strength, \
|
||||
PM_GPIO_FUNC_NORMAL, 0, 0)
|
||||
|
||||
#define PM8921_GPIO_OUTPUT_BUFCONF(_gpio, _val, _strength, _bufconf) \
|
||||
PM8921_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT,\
|
||||
PM_GPIO_OUT_BUF_##_bufconf, _val, \
|
||||
PM_GPIO_PULL_NO, PM_GPIO_VIN_S4, \
|
||||
PM_GPIO_STRENGTH_##_strength, \
|
||||
PM_GPIO_FUNC_NORMAL, 0, 0)
|
||||
|
||||
#define PM8921_GPIO_INPUT(_gpio, _pull) \
|
||||
PM8921_GPIO_INIT(_gpio, PM_GPIO_DIR_IN, PM_GPIO_OUT_BUF_CMOS, 0, \
|
||||
_pull, PM_GPIO_VIN_S4, \
|
||||
PM_GPIO_STRENGTH_NO, \
|
||||
PM_GPIO_FUNC_NORMAL, 0, 0)
|
||||
|
||||
#define PM8921_GPIO_OUTPUT_FUNC(_gpio, _val, _func) \
|
||||
PM8921_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT, PM_GPIO_OUT_BUF_CMOS, _val, \
|
||||
PM_GPIO_PULL_NO, PM_GPIO_VIN_S4, \
|
||||
PM_GPIO_STRENGTH_HIGH, \
|
||||
_func, 0, 0)
|
||||
|
||||
#define PM8921_GPIO_OUTPUT_VIN(_gpio, _val, _vin) \
|
||||
PM8921_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT, PM_GPIO_OUT_BUF_CMOS, _val, \
|
||||
PM_GPIO_PULL_NO, _vin, \
|
||||
PM_GPIO_STRENGTH_HIGH, \
|
||||
PM_GPIO_FUNC_NORMAL, 0, 0)
|
||||
|
||||
/* Initial PM8921 GPIO configurations */
|
||||
static struct pm8xxx_gpio_init pm8921_gpios[] __initdata = {
|
||||
PM8921_GPIO_OUTPUT(14, 1, HIGH), /* HDMI Mux Selector */
|
||||
PM8921_GPIO_OUTPUT(23, 0, HIGH), /* touchscreen power FET */
|
||||
PM8921_GPIO_OUTPUT_BUFCONF(25, 0, LOW, CMOS), /* DISP_RESET_N */
|
||||
PM8921_GPIO_OUTPUT_FUNC(26, 0, PM_GPIO_FUNC_2), /* Bl: Off, PWM mode */
|
||||
PM8921_GPIO_OUTPUT_VIN(30, 1, PM_GPIO_VIN_VPH), /* SMB349 susp line */
|
||||
PM8921_GPIO_OUTPUT_BUFCONF(36, 1, LOW, OPEN_DRAIN),
|
||||
PM8921_GPIO_OUTPUT_FUNC(44, 0, PM_GPIO_FUNC_2),
|
||||
PM8921_GPIO_OUTPUT(33, 0, HIGH),
|
||||
PM8921_GPIO_OUTPUT(20, 0, HIGH),
|
||||
PM8921_GPIO_INPUT(35, PM_GPIO_PULL_UP_30),
|
||||
PM8921_GPIO_INPUT(38, PM_GPIO_PULL_UP_30),
|
||||
/* TABLA CODEC RESET */
|
||||
PM8921_GPIO_OUTPUT(34, 1, MED),
|
||||
PM8921_GPIO_OUTPUT(13, 0, HIGH), /* PCIE_CLK_PWR_EN */
|
||||
};
|
||||
|
||||
static struct pm8xxx_gpio_init pm8921_mtp_kp_gpios[] __initdata = {
|
||||
PM8921_GPIO_INPUT(3, PM_GPIO_PULL_UP_30),
|
||||
PM8921_GPIO_INPUT(4, PM_GPIO_PULL_UP_30),
|
||||
};
|
||||
|
||||
static struct pm8xxx_gpio_init pm8921_cdp_kp_gpios[] __initdata = {
|
||||
PM8921_GPIO_INPUT(27, PM_GPIO_PULL_UP_30),
|
||||
PM8921_GPIO_INPUT(42, PM_GPIO_PULL_UP_30),
|
||||
PM8921_GPIO_INPUT(17, PM_GPIO_PULL_UP_1P5), /* SD_WP */
|
||||
};
|
||||
|
||||
/* Initial PM8XXX MPP configurations */
|
||||
static struct pm8xxx_mpp_init pm8xxx_mpps[] __initdata = {
|
||||
PM8921_MPP_INIT(3, D_OUTPUT, PM8921_MPP_DIG_LEVEL_VPH, DOUT_CTRL_LOW),
|
||||
PM8921_MPP_INIT(8, D_OUTPUT, PM8921_MPP_DIG_LEVEL_S4, DOUT_CTRL_LOW),
|
||||
/*MPP9 is used to detect docking station connection/removal on Liquid*/
|
||||
PM8921_MPP_INIT(9, D_INPUT, PM8921_MPP_DIG_LEVEL_S4, DIN_TO_INT),
|
||||
/* PCIE_RESET_N */
|
||||
PM8921_MPP_INIT(1, D_OUTPUT, PM8921_MPP_DIG_LEVEL_VPH, DOUT_CTRL_HIGH),
|
||||
};
|
||||
|
||||
void __init apq8064_pm8xxx_gpio_mpp_init(void)
|
||||
{
|
||||
int i, rc;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pm8921_gpios); i++) {
|
||||
rc = pm8xxx_gpio_config(pm8921_gpios[i].gpio,
|
||||
&pm8921_gpios[i].config);
|
||||
if (rc) {
|
||||
pr_err("%s: pm8xxx_gpio_config: rc=%d\n", __func__, rc);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (machine_is_apq8064_cdp() || machine_is_apq8064_liquid())
|
||||
for (i = 0; i < ARRAY_SIZE(pm8921_cdp_kp_gpios); i++) {
|
||||
rc = pm8xxx_gpio_config(pm8921_cdp_kp_gpios[i].gpio,
|
||||
&pm8921_cdp_kp_gpios[i].config);
|
||||
if (rc) {
|
||||
pr_err("%s: pm8xxx_gpio_config: rc=%d\n",
|
||||
__func__, rc);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (machine_is_apq8064_mtp())
|
||||
for (i = 0; i < ARRAY_SIZE(pm8921_mtp_kp_gpios); i++) {
|
||||
rc = pm8xxx_gpio_config(pm8921_mtp_kp_gpios[i].gpio,
|
||||
&pm8921_mtp_kp_gpios[i].config);
|
||||
if (rc) {
|
||||
pr_err("%s: pm8xxx_gpio_config: rc=%d\n",
|
||||
__func__, rc);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pm8xxx_mpps); i++) {
|
||||
rc = pm8xxx_mpp_config(pm8xxx_mpps[i].mpp,
|
||||
&pm8xxx_mpps[i].config);
|
||||
if (rc) {
|
||||
pr_err("%s: pm8xxx_mpp_config: rc=%d\n", __func__, rc);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static struct pm8xxx_pwrkey_platform_data apq8064_pm8921_pwrkey_pdata = {
|
||||
.pull_up = 1,
|
||||
.kpd_trigger_delay_us = 15625,
|
||||
.wakeup = 1,
|
||||
};
|
||||
|
||||
static struct pm8xxx_misc_platform_data apq8064_pm8921_misc_pdata = {
|
||||
.priority = 0,
|
||||
};
|
||||
|
||||
#define PM8921_LC_LED_MAX_CURRENT 4 /* I = 4mA */
|
||||
#define PM8921_LC_LED_LOW_CURRENT 1 /* I = 1mA */
|
||||
#define PM8XXX_LED_PWM_PERIOD 1000
|
||||
#define PM8XXX_LED_PWM_DUTY_MS 20
|
||||
/**
|
||||
* PM8XXX_PWM_CHANNEL_NONE shall be used when LED shall not be
|
||||
* driven using PWM feature.
|
||||
*/
|
||||
#define PM8XXX_PWM_CHANNEL_NONE -1
|
||||
|
||||
static struct led_info pm8921_led_info[] = {
|
||||
[0] = {
|
||||
.name = "led:red",
|
||||
.default_trigger = "ac-online",
|
||||
},
|
||||
};
|
||||
|
||||
static struct led_platform_data pm8921_led_core_pdata = {
|
||||
.num_leds = ARRAY_SIZE(pm8921_led_info),
|
||||
.leds = pm8921_led_info,
|
||||
};
|
||||
|
||||
static int pm8921_led0_pwm_duty_pcts[56] = {
|
||||
1, 4, 8, 12, 16, 20, 24, 28, 32, 36,
|
||||
40, 44, 46, 52, 56, 60, 64, 68, 72, 76,
|
||||
80, 84, 88, 92, 96, 100, 100, 100, 98, 95,
|
||||
92, 88, 84, 82, 78, 74, 70, 66, 62, 58,
|
||||
58, 54, 50, 48, 42, 38, 34, 30, 26, 22,
|
||||
14, 10, 6, 4, 1
|
||||
};
|
||||
|
||||
static struct pm8xxx_pwm_duty_cycles pm8921_led0_pwm_duty_cycles = {
|
||||
.duty_pcts = (int *)&pm8921_led0_pwm_duty_pcts,
|
||||
.num_duty_pcts = ARRAY_SIZE(pm8921_led0_pwm_duty_pcts),
|
||||
.duty_ms = PM8XXX_LED_PWM_DUTY_MS,
|
||||
.start_idx = 0,
|
||||
};
|
||||
|
||||
static struct pm8xxx_led_config pm8921_led_configs[] = {
|
||||
[0] = {
|
||||
.id = PM8XXX_ID_LED_0,
|
||||
.mode = PM8XXX_LED_MODE_PWM2,
|
||||
.max_current = PM8921_LC_LED_MAX_CURRENT,
|
||||
.pwm_channel = 5,
|
||||
.pwm_period_us = PM8XXX_LED_PWM_PERIOD,
|
||||
.pwm_duty_cycles = &pm8921_led0_pwm_duty_cycles,
|
||||
},
|
||||
};
|
||||
|
||||
static struct pm8xxx_led_platform_data apq8064_pm8921_leds_pdata = {
|
||||
.led_core = &pm8921_led_core_pdata,
|
||||
.configs = pm8921_led_configs,
|
||||
.num_configs = ARRAY_SIZE(pm8921_led_configs),
|
||||
};
|
||||
|
||||
static struct pm8xxx_adc_amux apq8064_pm8921_adc_channels_data[] = {
|
||||
{"vcoin", CHANNEL_VCOIN, CHAN_PATH_SCALING2, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"vbat", CHANNEL_VBAT, CHAN_PATH_SCALING2, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"dcin", CHANNEL_DCIN, CHAN_PATH_SCALING4, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"ichg", CHANNEL_ICHG, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"vph_pwr", CHANNEL_VPH_PWR, CHAN_PATH_SCALING2, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"ibat", CHANNEL_IBAT, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"batt_therm", CHANNEL_BATT_THERM, CHAN_PATH_SCALING1, AMUX_RSV2,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_BATT_THERM},
|
||||
{"batt_id", CHANNEL_BATT_ID, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"usbin", CHANNEL_USBIN, CHAN_PATH_SCALING3, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"pmic_therm", CHANNEL_DIE_TEMP, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_PMIC_THERM},
|
||||
{"625mv", CHANNEL_625MV, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"125v", CHANNEL_125V, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"chg_temp", CHANNEL_CHG_TEMP, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"xo_therm", CHANNEL_MUXOFF, CHAN_PATH_SCALING1, AMUX_RSV0,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_XOTHERM},
|
||||
};
|
||||
|
||||
static struct pm8xxx_adc_properties apq8064_pm8921_adc_data = {
|
||||
.adc_vdd_reference = 1800, /* milli-voltage for this adc */
|
||||
.bitresolution = 15,
|
||||
.bipolar = 0,
|
||||
};
|
||||
|
||||
static struct pm8xxx_adc_platform_data apq8064_pm8921_adc_pdata = {
|
||||
.adc_channel = apq8064_pm8921_adc_channels_data,
|
||||
.adc_num_board_channel = ARRAY_SIZE(apq8064_pm8921_adc_channels_data),
|
||||
.adc_prop = &apq8064_pm8921_adc_data,
|
||||
.adc_mpp_base = PM8921_MPP_PM_TO_SYS(1),
|
||||
};
|
||||
|
||||
static struct pm8xxx_mpp_platform_data
|
||||
apq8064_pm8921_mpp_pdata __devinitdata = {
|
||||
.mpp_base = PM8921_MPP_PM_TO_SYS(1),
|
||||
};
|
||||
|
||||
static struct pm8xxx_gpio_platform_data
|
||||
apq8064_pm8921_gpio_pdata __devinitdata = {
|
||||
.gpio_base = PM8921_GPIO_PM_TO_SYS(1),
|
||||
};
|
||||
|
||||
static struct pm8xxx_irq_platform_data
|
||||
apq8064_pm8921_irq_pdata __devinitdata = {
|
||||
.irq_base = PM8921_IRQ_BASE,
|
||||
.devirq = MSM_GPIO_TO_INT(74),
|
||||
.irq_trigger_flag = IRQF_TRIGGER_LOW,
|
||||
.dev_id = 0,
|
||||
};
|
||||
|
||||
static struct pm8xxx_rtc_platform_data
|
||||
apq8064_pm8921_rtc_pdata = {
|
||||
.rtc_write_enable = false,
|
||||
.rtc_alarm_powerup = false,
|
||||
};
|
||||
|
||||
static int apq8064_pm8921_therm_mitigation[] = {
|
||||
1100,
|
||||
700,
|
||||
600,
|
||||
325,
|
||||
};
|
||||
|
||||
#define MAX_VOLTAGE_MV 4200
|
||||
static struct pm8921_charger_platform_data
|
||||
apq8064_pm8921_chg_pdata __devinitdata = {
|
||||
.safety_time = 180,
|
||||
.update_time = 60000,
|
||||
.max_voltage = MAX_VOLTAGE_MV,
|
||||
.min_voltage = 3200,
|
||||
.resume_voltage_delta = 100,
|
||||
.term_current = 100,
|
||||
.cool_temp = 10,
|
||||
.warm_temp = 40,
|
||||
.temp_check_period = 1,
|
||||
.max_bat_chg_current = 1100,
|
||||
.cool_bat_chg_current = 350,
|
||||
.warm_bat_chg_current = 350,
|
||||
.cool_bat_voltage = 4100,
|
||||
.warm_bat_voltage = 4100,
|
||||
.thermal_mitigation = apq8064_pm8921_therm_mitigation,
|
||||
.thermal_levels = ARRAY_SIZE(apq8064_pm8921_therm_mitigation),
|
||||
};
|
||||
|
||||
static struct pm8xxx_ccadc_platform_data
|
||||
apq8064_pm8xxx_ccadc_pdata = {
|
||||
.r_sense = 10,
|
||||
};
|
||||
|
||||
static struct pm8921_bms_platform_data
|
||||
apq8064_pm8921_bms_pdata __devinitdata = {
|
||||
.battery_type = BATT_UNKNOWN,
|
||||
.r_sense = 10,
|
||||
.i_test = 2500,
|
||||
.v_failure = 3000,
|
||||
.calib_delay_ms = 600000,
|
||||
.max_voltage_uv = MAX_VOLTAGE_MV * 1000,
|
||||
};
|
||||
|
||||
static struct pm8921_platform_data
|
||||
apq8064_pm8921_platform_data __devinitdata = {
|
||||
.regulator_pdatas = msm8064_pm8921_regulator_pdata,
|
||||
.irq_pdata = &apq8064_pm8921_irq_pdata,
|
||||
.gpio_pdata = &apq8064_pm8921_gpio_pdata,
|
||||
.mpp_pdata = &apq8064_pm8921_mpp_pdata,
|
||||
.rtc_pdata = &apq8064_pm8921_rtc_pdata,
|
||||
.pwrkey_pdata = &apq8064_pm8921_pwrkey_pdata,
|
||||
.misc_pdata = &apq8064_pm8921_misc_pdata,
|
||||
.leds_pdata = &apq8064_pm8921_leds_pdata,
|
||||
.adc_pdata = &apq8064_pm8921_adc_pdata,
|
||||
.charger_pdata = &apq8064_pm8921_chg_pdata,
|
||||
.bms_pdata = &apq8064_pm8921_bms_pdata,
|
||||
.ccadc_pdata = &apq8064_pm8xxx_ccadc_pdata,
|
||||
};
|
||||
|
||||
static struct pm8xxx_irq_platform_data
|
||||
apq8064_pm8821_irq_pdata __devinitdata = {
|
||||
.irq_base = PM8821_IRQ_BASE,
|
||||
.devirq = PM8821_SEC_IRQ_N,
|
||||
.irq_trigger_flag = IRQF_TRIGGER_HIGH,
|
||||
.dev_id = 1,
|
||||
};
|
||||
|
||||
static struct pm8xxx_mpp_platform_data
|
||||
apq8064_pm8821_mpp_pdata __devinitdata = {
|
||||
.mpp_base = PM8821_MPP_PM_TO_SYS(1),
|
||||
};
|
||||
|
||||
static struct pm8821_platform_data
|
||||
apq8064_pm8821_platform_data __devinitdata = {
|
||||
.irq_pdata = &apq8064_pm8821_irq_pdata,
|
||||
.mpp_pdata = &apq8064_pm8821_mpp_pdata,
|
||||
};
|
||||
|
||||
static struct msm_ssbi_platform_data apq8064_ssbi_pm8921_pdata __devinitdata = {
|
||||
.controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
|
||||
.slave = {
|
||||
.name = "pm8921-core",
|
||||
.platform_data = &apq8064_pm8921_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_ssbi_platform_data apq8064_ssbi_pm8821_pdata __devinitdata = {
|
||||
.controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
|
||||
.slave = {
|
||||
.name = "pm8821-core",
|
||||
.platform_data = &apq8064_pm8821_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
void __init apq8064_init_pmic(void)
|
||||
{
|
||||
pmic_reset_irq = PM8921_IRQ_BASE + PM8921_RESOUT_IRQ;
|
||||
|
||||
apq8064_device_ssbi_pmic1.dev.platform_data =
|
||||
&apq8064_ssbi_pm8921_pdata;
|
||||
apq8064_device_ssbi_pmic2.dev.platform_data =
|
||||
&apq8064_ssbi_pm8821_pdata;
|
||||
apq8064_pm8921_platform_data.num_regulators =
|
||||
msm8064_pm8921_regulator_pdata_len;
|
||||
|
||||
if (machine_is_apq8064_rumi3()) {
|
||||
apq8064_pm8921_irq_pdata.devirq = 0;
|
||||
apq8064_pm8821_irq_pdata.devirq = 0;
|
||||
} else if (machine_is_apq8064_mtp()) {
|
||||
apq8064_pm8921_bms_pdata.battery_type = BATT_PALLADIUM;
|
||||
} else if (machine_is_apq8064_liquid()) {
|
||||
apq8064_pm8921_bms_pdata.battery_type = BATT_DESAY;
|
||||
}
|
||||
}
|
||||
615
arch/arm/mach-msm/board-8064-regulator.c
Normal file
615
arch/arm/mach-msm/board-8064-regulator.c
Normal file
@@ -0,0 +1,615 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/regulator/pm8xxx-regulator.h>
|
||||
|
||||
#include "board-8064.h"
|
||||
|
||||
#define VREG_CONSUMERS(_id) \
|
||||
static struct regulator_consumer_supply vreg_consumers_##_id[]
|
||||
|
||||
/*
|
||||
* Consumer specific regulator names:
|
||||
* regulator name consumer dev_name
|
||||
*/
|
||||
VREG_CONSUMERS(L1) = {
|
||||
REGULATOR_SUPPLY("8921_l1", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L2) = {
|
||||
REGULATOR_SUPPLY("8921_l2", NULL),
|
||||
REGULATOR_SUPPLY("mipi_csi_vdd", "msm_csid.0"),
|
||||
REGULATOR_SUPPLY("mipi_csi_vdd", "msm_csid.1"),
|
||||
REGULATOR_SUPPLY("mipi_csi_vdd", "msm_csid.2"),
|
||||
REGULATOR_SUPPLY("lvds_pll_vdda", "lvds.0"),
|
||||
REGULATOR_SUPPLY("dsi1_pll_vdda", "mipi_dsi.1"),
|
||||
};
|
||||
VREG_CONSUMERS(L3) = {
|
||||
REGULATOR_SUPPLY("8921_l3", NULL),
|
||||
REGULATOR_SUPPLY("HSUSB_3p3", "msm_otg"),
|
||||
REGULATOR_SUPPLY("HSUSB_3p3", "msm_ehci_host.0"),
|
||||
REGULATOR_SUPPLY("HSUSB_3p3", "msm_ehci_host.1"),
|
||||
};
|
||||
VREG_CONSUMERS(L4) = {
|
||||
REGULATOR_SUPPLY("8921_l4", NULL),
|
||||
REGULATOR_SUPPLY("HSUSB_1p8", "msm_otg"),
|
||||
REGULATOR_SUPPLY("iris_vddxo", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(L5) = {
|
||||
REGULATOR_SUPPLY("8921_l5", NULL),
|
||||
REGULATOR_SUPPLY("sdc_vdd", "msm_sdcc.1"),
|
||||
};
|
||||
VREG_CONSUMERS(L6) = {
|
||||
REGULATOR_SUPPLY("8921_l6", NULL),
|
||||
REGULATOR_SUPPLY("sdc_vdd", "msm_sdcc.3"),
|
||||
};
|
||||
VREG_CONSUMERS(L7) = {
|
||||
REGULATOR_SUPPLY("8921_l7", NULL),
|
||||
REGULATOR_SUPPLY("sdc_vdd_io", "msm_sdcc.3"),
|
||||
};
|
||||
VREG_CONSUMERS(L8) = {
|
||||
REGULATOR_SUPPLY("8921_l8", NULL),
|
||||
REGULATOR_SUPPLY("cam_vana", "4-001a"),
|
||||
REGULATOR_SUPPLY("cam_vana", "4-0048"),
|
||||
REGULATOR_SUPPLY("cam_vana", "4-006c"),
|
||||
REGULATOR_SUPPLY("cam_vana", "4-0034"),
|
||||
REGULATOR_SUPPLY("cam_vana", "4-0020"),
|
||||
};
|
||||
VREG_CONSUMERS(L9) = {
|
||||
REGULATOR_SUPPLY("8921_l9", NULL),
|
||||
REGULATOR_SUPPLY("vdd", "3-0024"),
|
||||
};
|
||||
VREG_CONSUMERS(L10) = {
|
||||
REGULATOR_SUPPLY("8921_l10", NULL),
|
||||
REGULATOR_SUPPLY("iris_vddpa", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(L11) = {
|
||||
REGULATOR_SUPPLY("8921_l11", NULL),
|
||||
REGULATOR_SUPPLY("dsi1_avdd", "mipi_dsi.1"),
|
||||
};
|
||||
VREG_CONSUMERS(L12) = {
|
||||
REGULATOR_SUPPLY("cam_vdig", "4-001a"),
|
||||
REGULATOR_SUPPLY("cam_vdig", "4-0048"),
|
||||
REGULATOR_SUPPLY("cam_vdig", "4-006c"),
|
||||
REGULATOR_SUPPLY("cam_vdig", "4-0034"),
|
||||
REGULATOR_SUPPLY("cam_vdig", "4-0020"),
|
||||
REGULATOR_SUPPLY("8921_l12", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L14) = {
|
||||
REGULATOR_SUPPLY("8921_l14", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L15) = {
|
||||
REGULATOR_SUPPLY("8921_l15", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L16) = {
|
||||
REGULATOR_SUPPLY("8921_l16", NULL),
|
||||
REGULATOR_SUPPLY("cam_vaf", "4-001a"),
|
||||
REGULATOR_SUPPLY("cam_vaf", "4-0048"),
|
||||
REGULATOR_SUPPLY("cam_vaf", "4-006c"),
|
||||
REGULATOR_SUPPLY("cam_vaf", "4-0034"),
|
||||
REGULATOR_SUPPLY("cam_vaf", "4-0020"),
|
||||
};
|
||||
VREG_CONSUMERS(L17) = {
|
||||
REGULATOR_SUPPLY("8921_l17", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L18) = {
|
||||
REGULATOR_SUPPLY("8921_l18", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L21) = {
|
||||
REGULATOR_SUPPLY("8921_l21", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L22) = {
|
||||
REGULATOR_SUPPLY("8921_l22", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L23) = {
|
||||
REGULATOR_SUPPLY("8921_l23", NULL),
|
||||
REGULATOR_SUPPLY("pll_vdd", "pil_qdsp6v4.1"),
|
||||
REGULATOR_SUPPLY("pll_vdd", "pil_qdsp6v4.2"),
|
||||
REGULATOR_SUPPLY("HSUSB_1p8", "msm_ehci_host.0"),
|
||||
REGULATOR_SUPPLY("HSUSB_1p8", "msm_ehci_host.1"),
|
||||
};
|
||||
VREG_CONSUMERS(L24) = {
|
||||
REGULATOR_SUPPLY("8921_l24", NULL),
|
||||
REGULATOR_SUPPLY("riva_vddmx", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(L25) = {
|
||||
REGULATOR_SUPPLY("8921_l25", NULL),
|
||||
REGULATOR_SUPPLY("VDDD_CDC_D", "tabla-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_A_1P2V", "tabla-slim"),
|
||||
REGULATOR_SUPPLY("VDDD_CDC_D", "tabla2x-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_A_1P2V", "tabla2x-slim"),
|
||||
};
|
||||
VREG_CONSUMERS(L26) = {
|
||||
REGULATOR_SUPPLY("8921_l26", NULL),
|
||||
REGULATOR_SUPPLY("core_vdd", "pil_qdsp6v4.0"),
|
||||
};
|
||||
VREG_CONSUMERS(L27) = {
|
||||
REGULATOR_SUPPLY("8921_l27", NULL),
|
||||
REGULATOR_SUPPLY("core_vdd", "pil_qdsp6v4.2"),
|
||||
};
|
||||
VREG_CONSUMERS(L28) = {
|
||||
REGULATOR_SUPPLY("8921_l28", NULL),
|
||||
REGULATOR_SUPPLY("core_vdd", "pil_qdsp6v4.1"),
|
||||
};
|
||||
VREG_CONSUMERS(L29) = {
|
||||
REGULATOR_SUPPLY("8921_l29", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(S1) = {
|
||||
REGULATOR_SUPPLY("8921_s1", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(S2) = {
|
||||
REGULATOR_SUPPLY("8921_s2", NULL),
|
||||
REGULATOR_SUPPLY("iris_vddrfa", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(S3) = {
|
||||
REGULATOR_SUPPLY("8921_s3", NULL),
|
||||
REGULATOR_SUPPLY("HSUSB_VDDCX", "msm_otg"),
|
||||
REGULATOR_SUPPLY("HSUSB_VDDCX", "msm_ehci_host.0"),
|
||||
REGULATOR_SUPPLY("HSUSB_VDDCX", "msm_ehci_host.1"),
|
||||
REGULATOR_SUPPLY("HSIC_VDDCX", "msm_hsic_host"),
|
||||
REGULATOR_SUPPLY("riva_vddcx", "wcnss_wlan.0"),
|
||||
REGULATOR_SUPPLY("vp_pcie", "msm_pcie"),
|
||||
REGULATOR_SUPPLY("vptx_pcie", "msm_pcie"),
|
||||
};
|
||||
VREG_CONSUMERS(S4) = {
|
||||
REGULATOR_SUPPLY("8921_s4", NULL),
|
||||
REGULATOR_SUPPLY("sdc_vdd_io", "msm_sdcc.1"),
|
||||
REGULATOR_SUPPLY("VDDIO_CDC", "tabla-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDD_CP", "tabla-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_TX", "tabla-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_RX", "tabla-slim"),
|
||||
REGULATOR_SUPPLY("VDDIO_CDC", "tabla2x-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDD_CP", "tabla2x-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_TX", "tabla2x-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_RX", "tabla2x-slim"),
|
||||
REGULATOR_SUPPLY("riva_vddpx", "wcnss_wlan.0"),
|
||||
REGULATOR_SUPPLY("vcc_i2c", "3-005b"),
|
||||
REGULATOR_SUPPLY("vcc_i2c", "3-0024"),
|
||||
REGULATOR_SUPPLY("vddp", "0-0048"),
|
||||
REGULATOR_SUPPLY("hdmi_lvl_tsl", "hdmi_msm.0"),
|
||||
};
|
||||
VREG_CONSUMERS(S5) = {
|
||||
REGULATOR_SUPPLY("8921_s5", NULL),
|
||||
REGULATOR_SUPPLY("krait0", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(S6) = {
|
||||
REGULATOR_SUPPLY("8921_s6", NULL),
|
||||
REGULATOR_SUPPLY("krait1", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(S7) = {
|
||||
REGULATOR_SUPPLY("8921_s7", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(S8) = {
|
||||
REGULATOR_SUPPLY("8921_s8", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(LVS1) = {
|
||||
REGULATOR_SUPPLY("8921_lvs1", NULL),
|
||||
REGULATOR_SUPPLY("iris_vddio", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(LVS2) = {
|
||||
REGULATOR_SUPPLY("8921_lvs2", NULL),
|
||||
REGULATOR_SUPPLY("iris_vdddig", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(LVS3) = {
|
||||
REGULATOR_SUPPLY("8921_lvs3", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(LVS4) = {
|
||||
REGULATOR_SUPPLY("8921_lvs4", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(LVS5) = {
|
||||
REGULATOR_SUPPLY("8921_lvs5", NULL),
|
||||
REGULATOR_SUPPLY("cam_vio", "4-001a"),
|
||||
REGULATOR_SUPPLY("cam_vio", "4-0048"),
|
||||
REGULATOR_SUPPLY("cam_vio", "4-006c"),
|
||||
REGULATOR_SUPPLY("cam_vio", "4-0034"),
|
||||
REGULATOR_SUPPLY("cam_vio", "4-0020"),
|
||||
};
|
||||
VREG_CONSUMERS(LVS6) = {
|
||||
REGULATOR_SUPPLY("8921_lvs6", NULL),
|
||||
REGULATOR_SUPPLY("vdd_pcie_vph", "msm_pcie"),
|
||||
};
|
||||
VREG_CONSUMERS(LVS7) = {
|
||||
REGULATOR_SUPPLY("8921_lvs7", NULL),
|
||||
REGULATOR_SUPPLY("pll_vdd", "pil_riva"),
|
||||
REGULATOR_SUPPLY("lvds_vdda", "lvds.0"),
|
||||
REGULATOR_SUPPLY("dsi1_vddio", "mipi_dsi.1"),
|
||||
REGULATOR_SUPPLY("hdmi_vdda", "hdmi_msm.0"),
|
||||
};
|
||||
VREG_CONSUMERS(USB_OTG) = {
|
||||
REGULATOR_SUPPLY("8921_usb_otg", NULL),
|
||||
REGULATOR_SUPPLY("vbus_otg", "msm_otg"),
|
||||
};
|
||||
VREG_CONSUMERS(HDMI_MVS) = {
|
||||
REGULATOR_SUPPLY("8921_hdmi_mvs", NULL),
|
||||
REGULATOR_SUPPLY("hdmi_mvs", "hdmi_msm.0"),
|
||||
};
|
||||
VREG_CONSUMERS(NCP) = {
|
||||
REGULATOR_SUPPLY("8921_ncp", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(8821_S0) = {
|
||||
REGULATOR_SUPPLY("8821_s0", NULL),
|
||||
REGULATOR_SUPPLY("krait2", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(8821_S1) = {
|
||||
REGULATOR_SUPPLY("8821_s1", NULL),
|
||||
REGULATOR_SUPPLY("krait3", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(EXT_5V) = {
|
||||
REGULATOR_SUPPLY("ext_5v", NULL),
|
||||
REGULATOR_SUPPLY("ext_ddr3", NULL),
|
||||
REGULATOR_SUPPLY("vbus", "msm_ehci_host.0"),
|
||||
};
|
||||
VREG_CONSUMERS(EXT_MPP8) = {
|
||||
REGULATOR_SUPPLY("ext_mpp8", NULL),
|
||||
REGULATOR_SUPPLY("vbus", "msm_ehci_host.1"),
|
||||
};
|
||||
VREG_CONSUMERS(EXT_3P3V) = {
|
||||
REGULATOR_SUPPLY("ext_3p3v", NULL),
|
||||
REGULATOR_SUPPLY("vdd_io", "spi0.2"),
|
||||
REGULATOR_SUPPLY("mhl_ext_3p3v", "msm_otg"),
|
||||
REGULATOR_SUPPLY("lvds_vccs_3p3v", "lvds.0"),
|
||||
REGULATOR_SUPPLY("dsi1_vccs_3p3v", "mipi_dsi.1"),
|
||||
REGULATOR_SUPPLY("hdmi_mux_vdd", "hdmi_msm.0"),
|
||||
REGULATOR_SUPPLY("pcie_ext_3p3v", "msm_pcie"),
|
||||
};
|
||||
VREG_CONSUMERS(EXT_TS_SW) = {
|
||||
REGULATOR_SUPPLY("ext_ts_sw", NULL),
|
||||
REGULATOR_SUPPLY("vdd_ana", "3-005b"),
|
||||
};
|
||||
VREG_CONSUMERS(AVC_1P2V) = {
|
||||
REGULATOR_SUPPLY("avc_1p2v", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(AVC_1P8V) = {
|
||||
REGULATOR_SUPPLY("avc_1p8v", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(AVC_2P2V) = {
|
||||
REGULATOR_SUPPLY("avc_2p2v", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(AVC_5V) = {
|
||||
REGULATOR_SUPPLY("avc_5v", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(AVC_3P3V) = {
|
||||
REGULATOR_SUPPLY("avc_3p3v", NULL),
|
||||
};
|
||||
|
||||
#define PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, _modes, _ops, \
|
||||
_apply_uV, _pull_down, _always_on, _supply_regulator, \
|
||||
_system_uA, _enable_time, _reg_id) \
|
||||
{ \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_modes_mask = _modes, \
|
||||
.valid_ops_mask = _ops, \
|
||||
.min_uV = _min_uV, \
|
||||
.max_uV = _max_uV, \
|
||||
.input_uV = _max_uV, \
|
||||
.apply_uV = _apply_uV, \
|
||||
.always_on = _always_on, \
|
||||
.name = _name, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id), \
|
||||
.consumer_supplies = vreg_consumers_##_id, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.id = _reg_id, \
|
||||
.pull_down_enable = _pull_down, \
|
||||
.system_uA = _system_uA, \
|
||||
.enable_time = _enable_time, \
|
||||
}
|
||||
|
||||
#define PM8XXX_LDO(_id, _name, _always_on, _pull_down, _min_uV, _max_uV, \
|
||||
_enable_time, _supply_regulator, _system_uA, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE | \
|
||||
REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
|
||||
REGULATOR_CHANGE_DRMS, 0, _pull_down, _always_on, \
|
||||
_supply_regulator, _system_uA, _enable_time, _reg_id)
|
||||
|
||||
#define PM8XXX_NLDO1200(_id, _name, _always_on, _pull_down, _min_uV, \
|
||||
_max_uV, _enable_time, _supply_regulator, _system_uA, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE | \
|
||||
REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
|
||||
REGULATOR_CHANGE_DRMS, 0, _pull_down, _always_on, \
|
||||
_supply_regulator, _system_uA, _enable_time, _reg_id)
|
||||
|
||||
#define PM8XXX_SMPS(_id, _name, _always_on, _pull_down, _min_uV, _max_uV, \
|
||||
_enable_time, _supply_regulator, _system_uA, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE | \
|
||||
REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
|
||||
REGULATOR_CHANGE_DRMS, 0, _pull_down, _always_on, \
|
||||
_supply_regulator, _system_uA, _enable_time, _reg_id)
|
||||
|
||||
#define PM8XXX_FTSMPS(_id, _name, _always_on, _pull_down, _min_uV, _max_uV, \
|
||||
_enable_time, _supply_regulator, _system_uA, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL, \
|
||||
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS \
|
||||
| REGULATOR_CHANGE_MODE, 0, _pull_down, _always_on, \
|
||||
_supply_regulator, _system_uA, _enable_time, _reg_id)
|
||||
|
||||
#define PM8XXX_VS(_id, _name, _always_on, _pull_down, _enable_time, \
|
||||
_supply_regulator, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, \
|
||||
_pull_down, _always_on, _supply_regulator, 0, _enable_time, \
|
||||
_reg_id)
|
||||
|
||||
#define PM8XXX_VS300(_id, _name, _always_on, _pull_down, _enable_time, \
|
||||
_supply_regulator, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, \
|
||||
_pull_down, _always_on, _supply_regulator, 0, _enable_time, \
|
||||
_reg_id)
|
||||
|
||||
#define PM8XXX_NCP(_id, _name, _always_on, _min_uV, _max_uV, _enable_time, \
|
||||
_supply_regulator, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, 0, \
|
||||
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, 0, 0, \
|
||||
_always_on, _supply_regulator, 0, _enable_time, _reg_id)
|
||||
|
||||
/* Pin control initialization */
|
||||
#define PM8XXX_PC(_id, _name, _always_on, _pin_fn, _pin_ctrl, \
|
||||
_supply_regulator, _reg_id) \
|
||||
{ \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS, \
|
||||
.always_on = _always_on, \
|
||||
.name = _name, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id##_PC), \
|
||||
.consumer_supplies = vreg_consumers_##_id##_PC, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.id = _reg_id, \
|
||||
.pin_fn = PM8XXX_VREG_PIN_FN_##_pin_fn, \
|
||||
.pin_ctrl = _pin_ctrl, \
|
||||
}
|
||||
|
||||
#define GPIO_VREG(_id, _reg_name, _gpio_label, _gpio, _supply_regulator) \
|
||||
[GPIO_VREG_ID_##_id] = { \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id), \
|
||||
.consumer_supplies = vreg_consumers_##_id, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.regulator_name = _reg_name, \
|
||||
.gpio_label = _gpio_label, \
|
||||
.gpio = _gpio, \
|
||||
}
|
||||
|
||||
#define SAW_VREG_INIT(_id, _name, _min_uV, _max_uV) \
|
||||
{ \
|
||||
.constraints = { \
|
||||
.name = _name, \
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, \
|
||||
.min_uV = _min_uV, \
|
||||
.max_uV = _max_uV, \
|
||||
}, \
|
||||
.num_consumer_supplies = ARRAY_SIZE(vreg_consumers_##_id), \
|
||||
.consumer_supplies = vreg_consumers_##_id, \
|
||||
}
|
||||
|
||||
#define RPM_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, _default_uV, \
|
||||
_peak_uA, _avg_uA, _pull_down, _pin_ctrl, _freq, _pin_fn, \
|
||||
_force_mode, _sleep_set_force_mode, _power_mode, _state, \
|
||||
_sleep_selectable, _always_on, _supply_regulator, _system_uA) \
|
||||
{ \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_modes_mask = _modes, \
|
||||
.valid_ops_mask = _ops, \
|
||||
.min_uV = _min_uV, \
|
||||
.max_uV = _max_uV, \
|
||||
.input_uV = _min_uV, \
|
||||
.apply_uV = _apply_uV, \
|
||||
.always_on = _always_on, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id), \
|
||||
.consumer_supplies = vreg_consumers_##_id, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.id = RPM_VREG_ID_PM8921_##_id, \
|
||||
.default_uV = _default_uV, \
|
||||
.peak_uA = _peak_uA, \
|
||||
.avg_uA = _avg_uA, \
|
||||
.pull_down_enable = _pull_down, \
|
||||
.pin_ctrl = _pin_ctrl, \
|
||||
.freq = RPM_VREG_FREQ_##_freq, \
|
||||
.pin_fn = _pin_fn, \
|
||||
.force_mode = _force_mode, \
|
||||
.sleep_set_force_mode = _sleep_set_force_mode, \
|
||||
.power_mode = _power_mode, \
|
||||
.state = _state, \
|
||||
.sleep_selectable = _sleep_selectable, \
|
||||
.system_uA = _system_uA, \
|
||||
}
|
||||
|
||||
#define RPM_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
|
||||
_supply_regulator, _system_uA, _init_peak_uA) \
|
||||
RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
|
||||
| REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
|
||||
| REGULATOR_CHANGE_DRMS, 0, _max_uV, _init_peak_uA, 0, _pd, \
|
||||
RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8960_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8960_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8960_NONE, RPM_VREG_POWER_MODE_8960_PWM, \
|
||||
RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
|
||||
_supply_regulator, _system_uA)
|
||||
|
||||
#define RPM_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
|
||||
_supply_regulator, _system_uA, _freq, _force_mode, \
|
||||
_sleep_set_force_mode) \
|
||||
RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
|
||||
| REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
|
||||
| REGULATOR_CHANGE_DRMS, 0, _max_uV, _system_uA, 0, _pd, \
|
||||
RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_8960_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8960_##_force_mode, \
|
||||
RPM_VREG_FORCE_MODE_8960_##_sleep_set_force_mode, \
|
||||
RPM_VREG_POWER_MODE_8960_PWM, RPM_VREG_STATE_OFF, \
|
||||
_sleep_selectable, _always_on, _supply_regulator, _system_uA)
|
||||
|
||||
#define RPM_VS(_id, _always_on, _pd, _sleep_selectable, _supply_regulator) \
|
||||
RPM_INIT(_id, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, 0, 1000, 1000, _pd, \
|
||||
RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8960_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8960_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8960_NONE, RPM_VREG_POWER_MODE_8960_PWM, \
|
||||
RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
|
||||
_supply_regulator, 0)
|
||||
|
||||
#define RPM_NCP(_id, _always_on, _sleep_selectable, _min_uV, _max_uV, \
|
||||
_supply_regulator, _freq) \
|
||||
RPM_INIT(_id, _min_uV, _max_uV, 0, REGULATOR_CHANGE_VOLTAGE \
|
||||
| REGULATOR_CHANGE_STATUS, 0, _max_uV, 1000, 1000, 0, \
|
||||
RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_8960_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8960_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8960_NONE, RPM_VREG_POWER_MODE_8960_PWM, \
|
||||
RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
|
||||
_supply_regulator, 0)
|
||||
|
||||
/* Pin control initialization */
|
||||
#define RPM_PC_INIT(_id, _always_on, _pin_fn, _pin_ctrl, _supply_regulator) \
|
||||
{ \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS, \
|
||||
.always_on = _always_on, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id##_PC), \
|
||||
.consumer_supplies = vreg_consumers_##_id##_PC, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.id = RPM_VREG_ID_PM8921_##_id##_PC, \
|
||||
.pin_fn = RPM_VREG_PIN_FN_8960_##_pin_fn, \
|
||||
.pin_ctrl = _pin_ctrl, \
|
||||
}
|
||||
|
||||
/* GPIO regulator constraints */
|
||||
struct gpio_regulator_platform_data
|
||||
apq8064_gpio_regulator_pdata[] __devinitdata = {
|
||||
/* ID vreg_name gpio_label gpio supply */
|
||||
GPIO_VREG(EXT_5V, "ext_5v", "ext_5v_en", PM8921_MPP_PM_TO_SYS(7), NULL),
|
||||
GPIO_VREG(EXT_3P3V, "ext_3p3v", "ext_3p3v_en",
|
||||
APQ8064_EXT_3P3V_REG_EN_GPIO, NULL),
|
||||
GPIO_VREG(EXT_TS_SW, "ext_ts_sw", "ext_ts_sw_en",
|
||||
PM8921_GPIO_PM_TO_SYS(23), "ext_3p3v"),
|
||||
GPIO_VREG(EXT_MPP8, "ext_mpp8", "ext_mpp8_en",
|
||||
PM8921_MPP_PM_TO_SYS(8), NULL),
|
||||
};
|
||||
|
||||
struct gpio_regulator_platform_data
|
||||
mpq8064_gpio_regulator_pdata[] __devinitdata = {
|
||||
GPIO_VREG(AVC_1P2V, "avc_1p2v", "avc_1p2v_en", SX150X_GPIO(4, 2), NULL),
|
||||
GPIO_VREG(AVC_1P8V, "avc_1p8v", "avc_1p8v_en", SX150X_GPIO(4, 4), NULL),
|
||||
GPIO_VREG(AVC_2P2V, "avc_2p2v", "avc_2p2v_en",
|
||||
SX150X_GPIO(4, 14), NULL),
|
||||
GPIO_VREG(AVC_5V, "avc_5v", "avc_5v_en", SX150X_GPIO(4, 3), NULL),
|
||||
GPIO_VREG(AVC_3P3V, "avc_3p3v", "avc_3p3v_en",
|
||||
SX150X_GPIO(4, 15), "avc_5v"),
|
||||
};
|
||||
|
||||
/* SAW regulator constraints */
|
||||
struct regulator_init_data msm8064_saw_regulator_pdata_8921_s5 =
|
||||
/* ID vreg_name min_uV max_uV */
|
||||
SAW_VREG_INIT(S5, "8921_s5", 850000, 1300000);
|
||||
struct regulator_init_data msm8064_saw_regulator_pdata_8921_s6 =
|
||||
SAW_VREG_INIT(S6, "8921_s6", 850000, 1300000);
|
||||
|
||||
struct regulator_init_data msm8064_saw_regulator_pdata_8821_s0 =
|
||||
/* ID vreg_name min_uV max_uV */
|
||||
SAW_VREG_INIT(8821_S0, "8821_s0", 850000, 1300000);
|
||||
struct regulator_init_data msm8064_saw_regulator_pdata_8821_s1 =
|
||||
SAW_VREG_INIT(8821_S1, "8821_s1", 850000, 1300000);
|
||||
|
||||
/* PM8921 regulator constraints */
|
||||
struct pm8xxx_regulator_platform_data
|
||||
msm8064_pm8921_regulator_pdata[] __devinitdata = {
|
||||
/*
|
||||
* ID name always_on pd min_uV max_uV en_t supply
|
||||
* system_uA reg_ID
|
||||
*/
|
||||
PM8XXX_NLDO1200(L26, "8921_l26", 0, 1, 375000, 1050000, 200, "8921_s7",
|
||||
0, 1),
|
||||
|
||||
/* ID name always_on pd en_t supply reg_ID */
|
||||
PM8XXX_VS300(USB_OTG, "8921_usb_otg", 0, 0, 0, "ext_5v", 2),
|
||||
PM8XXX_VS300(HDMI_MVS, "8921_hdmi_mvs", 0, 1, 0, "ext_5v", 3),
|
||||
};
|
||||
|
||||
static struct rpm_regulator_init_data
|
||||
apq8064_rpm_regulator_init_data[] __devinitdata = {
|
||||
/* ID a_on pd ss min_uV max_uV supply sys_uA freq fm ss_fm */
|
||||
RPM_SMPS(S1, 1, 1, 0, 1225000, 1225000, NULL, 100000, 3p20, NONE, NONE),
|
||||
RPM_SMPS(S2, 0, 1, 0, 1300000, 1300000, NULL, 0, 1p60, NONE, NONE),
|
||||
RPM_SMPS(S3, 0, 1, 1, 500000, 1150000, NULL, 100000, 4p80, NONE, NONE),
|
||||
RPM_SMPS(S4, 1, 1, 0, 1800000, 1800000, NULL, 100000, 1p60, AUTO, AUTO),
|
||||
RPM_SMPS(S7, 0, 1, 0, 1300000, 1300000, NULL, 100000, 3p20, NONE, NONE),
|
||||
RPM_SMPS(S8, 0, 1, 0, 2200000, 2200000, NULL, 0, 1p60, NONE, NONE),
|
||||
|
||||
/* ID a_on pd ss min_uV max_uV supply sys_uA init_ip */
|
||||
RPM_LDO(L1, 1, 1, 0, 1100000, 1100000, "8921_s4", 0, 1000),
|
||||
RPM_LDO(L2, 0, 1, 0, 1200000, 1200000, "8921_s4", 0, 0),
|
||||
RPM_LDO(L3, 0, 1, 0, 3075000, 3075000, NULL, 0, 0),
|
||||
RPM_LDO(L4, 1, 1, 0, 1800000, 1800000, NULL, 0, 10000),
|
||||
RPM_LDO(L5, 0, 1, 0, 2950000, 2950000, NULL, 0, 0),
|
||||
RPM_LDO(L6, 0, 1, 0, 2950000, 2950000, NULL, 0, 0),
|
||||
RPM_LDO(L7, 0, 1, 0, 1850000, 2950000, NULL, 0, 0),
|
||||
RPM_LDO(L8, 0, 1, 0, 2800000, 2800000, NULL, 0, 0),
|
||||
RPM_LDO(L9, 0, 1, 0, 3000000, 3000000, NULL, 0, 0),
|
||||
RPM_LDO(L10, 0, 1, 0, 2900000, 2900000, NULL, 0, 0),
|
||||
RPM_LDO(L11, 0, 1, 0, 3000000, 3000000, NULL, 0, 0),
|
||||
RPM_LDO(L12, 0, 1, 0, 1200000, 1200000, "8921_s4", 0, 0),
|
||||
RPM_LDO(L14, 0, 1, 0, 1800000, 1800000, NULL, 0, 0),
|
||||
RPM_LDO(L15, 0, 1, 0, 1800000, 2950000, NULL, 0, 0),
|
||||
RPM_LDO(L16, 0, 1, 0, 2800000, 2800000, NULL, 0, 0),
|
||||
RPM_LDO(L17, 0, 1, 0, 2000000, 2000000, NULL, 0, 0),
|
||||
RPM_LDO(L18, 0, 1, 0, 1300000, 1800000, "8921_s4", 0, 0),
|
||||
RPM_LDO(L21, 0, 1, 0, 1050000, 1050000, NULL, 0, 0),
|
||||
RPM_LDO(L22, 0, 1, 0, 2600000, 2600000, NULL, 0, 0),
|
||||
RPM_LDO(L23, 0, 1, 0, 1800000, 1800000, NULL, 0, 0),
|
||||
RPM_LDO(L24, 0, 1, 1, 750000, 1150000, "8921_s1", 10000, 10000),
|
||||
RPM_LDO(L25, 1, 1, 0, 1250000, 1250000, "8921_s1", 10000, 10000),
|
||||
RPM_LDO(L27, 0, 1, 0, 1100000, 1100000, "8921_s7", 0, 0),
|
||||
RPM_LDO(L28, 0, 1, 0, 1050000, 1050000, "8921_s7", 0, 0),
|
||||
RPM_LDO(L29, 0, 1, 0, 2000000, 2000000, NULL, 0, 0),
|
||||
|
||||
/* ID a_on pd ss supply */
|
||||
RPM_VS(LVS1, 0, 1, 0, "8921_s4"),
|
||||
RPM_VS(LVS2, 0, 1, 0, "8921_s1"),
|
||||
RPM_VS(LVS3, 0, 1, 0, "8921_s4"),
|
||||
RPM_VS(LVS4, 0, 1, 0, "8921_s4"),
|
||||
RPM_VS(LVS5, 0, 1, 0, "8921_s4"),
|
||||
RPM_VS(LVS6, 0, 1, 0, "8921_s4"),
|
||||
RPM_VS(LVS7, 0, 1, 1, "8921_s4"),
|
||||
|
||||
/* ID a_on ss min_uV max_uV supply freq */
|
||||
RPM_NCP(NCP, 0, 0, 1800000, 1800000, "8921_l6", 1p60),
|
||||
};
|
||||
|
||||
int msm8064_pm8921_regulator_pdata_len __devinitdata =
|
||||
ARRAY_SIZE(msm8064_pm8921_regulator_pdata);
|
||||
|
||||
struct rpm_regulator_platform_data apq8064_rpm_regulator_pdata __devinitdata = {
|
||||
.init_data = apq8064_rpm_regulator_init_data,
|
||||
.num_regulators = ARRAY_SIZE(apq8064_rpm_regulator_init_data),
|
||||
.version = RPM_VREG_VERSION_8960,
|
||||
.vreg_id_vdd_mem = RPM_VREG_ID_PM8921_L24,
|
||||
.vreg_id_vdd_dig = RPM_VREG_ID_PM8921_S3,
|
||||
};
|
||||
394
arch/arm/mach-msm/board-8064-storage.c
Normal file
394
arch/arm/mach-msm/board-8064-storage.c
Normal file
@@ -0,0 +1,394 @@
|
||||
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/mmc.h>
|
||||
#include <mach/msm_bus_board.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/gpiomux.h>
|
||||
#include "devices.h"
|
||||
#include "board-8064.h"
|
||||
#include "board-storage-common-a.h"
|
||||
|
||||
|
||||
/* APQ8064 has 4 SDCC controllers */
|
||||
enum sdcc_controllers {
|
||||
SDCC1,
|
||||
SDCC2,
|
||||
SDCC3,
|
||||
SDCC4,
|
||||
MAX_SDCC_CONTROLLER
|
||||
};
|
||||
|
||||
/* All SDCC controllers require VDD/VCC voltage */
|
||||
static struct msm_mmc_reg_data mmc_vdd_reg_data[MAX_SDCC_CONTROLLER] = {
|
||||
/* SDCC1 : eMMC card connected */
|
||||
[SDCC1] = {
|
||||
.name = "sdc_vdd",
|
||||
.high_vol_level = 2950000,
|
||||
.low_vol_level = 2950000,
|
||||
.always_on = 1,
|
||||
.lpm_sup = 1,
|
||||
.lpm_uA = 9000,
|
||||
.hpm_uA = 200000, /* 200mA */
|
||||
},
|
||||
/* SDCC3 : External card slot connected */
|
||||
[SDCC3] = {
|
||||
.name = "sdc_vdd",
|
||||
.high_vol_level = 2950000,
|
||||
.low_vol_level = 2950000,
|
||||
.hpm_uA = 800000, /* 800mA */
|
||||
}
|
||||
};
|
||||
|
||||
/* SDCC controllers may require voting for VDD IO voltage */
|
||||
static struct msm_mmc_reg_data mmc_vdd_io_reg_data[MAX_SDCC_CONTROLLER] = {
|
||||
/* SDCC1 : eMMC card connected */
|
||||
[SDCC1] = {
|
||||
.name = "sdc_vdd_io",
|
||||
.always_on = 1,
|
||||
.high_vol_level = 1800000,
|
||||
.low_vol_level = 1800000,
|
||||
.hpm_uA = 200000, /* 200mA */
|
||||
},
|
||||
/* SDCC3 : External card slot connected */
|
||||
[SDCC3] = {
|
||||
.name = "sdc_vdd_io",
|
||||
.high_vol_level = 2950000,
|
||||
.low_vol_level = 1850000,
|
||||
.always_on = 1,
|
||||
.lpm_sup = 1,
|
||||
/* Max. Active current required is 16 mA */
|
||||
.hpm_uA = 16000,
|
||||
/*
|
||||
* Sleep current required is ~300 uA. But min. vote can be
|
||||
* in terms of mA (min. 1 mA). So let's vote for 2 mA
|
||||
* during sleep.
|
||||
*/
|
||||
.lpm_uA = 2000,
|
||||
}
|
||||
};
|
||||
|
||||
static struct msm_mmc_slot_reg_data mmc_slot_vreg_data[MAX_SDCC_CONTROLLER] = {
|
||||
/* SDCC1 : eMMC card connected */
|
||||
[SDCC1] = {
|
||||
.vdd_data = &mmc_vdd_reg_data[SDCC1],
|
||||
.vdd_io_data = &mmc_vdd_io_reg_data[SDCC1],
|
||||
},
|
||||
/* SDCC3 : External card slot connected */
|
||||
[SDCC3] = {
|
||||
.vdd_data = &mmc_vdd_reg_data[SDCC3],
|
||||
.vdd_io_data = &mmc_vdd_io_reg_data[SDCC3],
|
||||
}
|
||||
};
|
||||
|
||||
/* SDC1 pad data */
|
||||
static struct msm_mmc_pad_drv sdc1_pad_drv_on_cfg[] = {
|
||||
{TLMM_HDRV_SDC1_CLK, GPIO_CFG_16MA},
|
||||
{TLMM_HDRV_SDC1_CMD, GPIO_CFG_10MA},
|
||||
{TLMM_HDRV_SDC1_DATA, GPIO_CFG_10MA}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_drv sdc1_pad_drv_off_cfg[] = {
|
||||
{TLMM_HDRV_SDC1_CLK, GPIO_CFG_2MA},
|
||||
{TLMM_HDRV_SDC1_CMD, GPIO_CFG_2MA},
|
||||
{TLMM_HDRV_SDC1_DATA, GPIO_CFG_2MA}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull sdc1_pad_pull_on_cfg[] = {
|
||||
{TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL},
|
||||
{TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP},
|
||||
{TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull sdc1_pad_pull_off_cfg[] = {
|
||||
{TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL},
|
||||
{TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP},
|
||||
{TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP}
|
||||
};
|
||||
|
||||
/* SDC3 pad data */
|
||||
static struct msm_mmc_pad_drv sdc3_pad_drv_on_cfg[] = {
|
||||
{TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA},
|
||||
{TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA},
|
||||
{TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_drv sdc3_pad_drv_off_cfg[] = {
|
||||
{TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA},
|
||||
{TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA},
|
||||
{TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull sdc3_pad_pull_on_cfg[] = {
|
||||
{TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL},
|
||||
{TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
|
||||
{TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull sdc3_pad_pull_off_cfg[] = {
|
||||
{TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL},
|
||||
{TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
|
||||
{TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull_data mmc_pad_pull_data[MAX_SDCC_CONTROLLER] = {
|
||||
[SDCC1] = {
|
||||
.on = sdc1_pad_pull_on_cfg,
|
||||
.off = sdc1_pad_pull_off_cfg,
|
||||
.size = ARRAY_SIZE(sdc1_pad_pull_on_cfg)
|
||||
},
|
||||
[SDCC3] = {
|
||||
.on = sdc3_pad_pull_on_cfg,
|
||||
.off = sdc3_pad_pull_off_cfg,
|
||||
.size = ARRAY_SIZE(sdc3_pad_pull_on_cfg)
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_drv_data mmc_pad_drv_data[MAX_SDCC_CONTROLLER] = {
|
||||
[SDCC1] = {
|
||||
.on = sdc1_pad_drv_on_cfg,
|
||||
.off = sdc1_pad_drv_off_cfg,
|
||||
.size = ARRAY_SIZE(sdc1_pad_drv_on_cfg)
|
||||
},
|
||||
[SDCC3] = {
|
||||
.on = sdc3_pad_drv_on_cfg,
|
||||
.off = sdc3_pad_drv_off_cfg,
|
||||
.size = ARRAY_SIZE(sdc3_pad_drv_on_cfg)
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_data mmc_pad_data[MAX_SDCC_CONTROLLER] = {
|
||||
[SDCC1] = {
|
||||
.pull = &mmc_pad_pull_data[SDCC1],
|
||||
.drv = &mmc_pad_drv_data[SDCC1]
|
||||
},
|
||||
[SDCC3] = {
|
||||
.pull = &mmc_pad_pull_data[SDCC3],
|
||||
.drv = &mmc_pad_drv_data[SDCC3]
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_mmc_gpio sdc2_gpio[] = {
|
||||
{59, "sdc2_clk"},
|
||||
{57, "sdc2_cmd"},
|
||||
{62, "sdc2_dat_0"},
|
||||
{61, "sdc2_dat_1"},
|
||||
{60, "sdc2_dat_2"},
|
||||
{58, "sdc2_dat_3"},
|
||||
};
|
||||
|
||||
static struct msm_mmc_gpio sdc4_gpio[] = {
|
||||
{68, "sdc4_clk"},
|
||||
{67, "sdc4_cmd"},
|
||||
{66, "sdc4_dat_0"},
|
||||
{65, "sdc4_dat_1"},
|
||||
{64, "sdc4_dat_2"},
|
||||
{63, "sdc4_dat_3"},
|
||||
};
|
||||
|
||||
static struct msm_mmc_gpio_data mmc_gpio_data[MAX_SDCC_CONTROLLER] = {
|
||||
[SDCC2] = {
|
||||
.gpio = sdc2_gpio,
|
||||
.size = ARRAY_SIZE(sdc2_gpio),
|
||||
},
|
||||
[SDCC4] = {
|
||||
.gpio = sdc4_gpio,
|
||||
.size = ARRAY_SIZE(sdc4_gpio),
|
||||
}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pin_data mmc_slot_pin_data[MAX_SDCC_CONTROLLER] = {
|
||||
[SDCC1] = {
|
||||
.pad_data = &mmc_pad_data[SDCC1],
|
||||
},
|
||||
[SDCC2] = {
|
||||
.is_gpio = 1,
|
||||
.gpio_data = &mmc_gpio_data[SDCC2],
|
||||
},
|
||||
[SDCC3] = {
|
||||
.pad_data = &mmc_pad_data[SDCC3],
|
||||
},
|
||||
[SDCC4] = {
|
||||
.is_gpio = 1,
|
||||
.gpio_data = &mmc_gpio_data[SDCC4],
|
||||
},
|
||||
};
|
||||
|
||||
#define MSM_MPM_PIN_SDC1_DAT1 17
|
||||
#define MSM_MPM_PIN_SDC3_DAT1 21
|
||||
|
||||
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
|
||||
static unsigned int sdc1_sup_clk_rates[] = {
|
||||
400000, 24000000, 48000000, 96000000
|
||||
};
|
||||
|
||||
static struct mmc_platform_data sdc1_data = {
|
||||
.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
|
||||
#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
|
||||
.mmc_bus_width = MMC_CAP_8_BIT_DATA,
|
||||
#else
|
||||
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
|
||||
#endif
|
||||
.sup_clk_table = sdc1_sup_clk_rates,
|
||||
.sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates),
|
||||
.pclk_src_dfab = 1,
|
||||
.nonremovable = 1,
|
||||
.pin_data = &mmc_slot_pin_data[SDCC1],
|
||||
.vreg_data = &mmc_slot_vreg_data[SDCC1],
|
||||
.uhs_caps = MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50,
|
||||
.mpm_sdiowakeup_int = MSM_MPM_PIN_SDC1_DAT1,
|
||||
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
|
||||
};
|
||||
static struct mmc_platform_data *apq8064_sdc1_pdata = &sdc1_data;
|
||||
#else
|
||||
static struct mmc_platform_data *apq8064_sdc1_pdata;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
|
||||
static unsigned int sdc2_sup_clk_rates[] = {
|
||||
400000, 24000000, 48000000
|
||||
};
|
||||
|
||||
static struct mmc_platform_data sdc2_data = {
|
||||
.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
|
||||
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
|
||||
.sup_clk_table = sdc2_sup_clk_rates,
|
||||
.sup_clk_cnt = ARRAY_SIZE(sdc2_sup_clk_rates),
|
||||
.pclk_src_dfab = 1,
|
||||
.pin_data = &mmc_slot_pin_data[SDCC2],
|
||||
.sdiowakeup_irq = MSM_GPIO_TO_INT(61),
|
||||
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
|
||||
};
|
||||
static struct mmc_platform_data *apq8064_sdc2_pdata = &sdc2_data;
|
||||
#else
|
||||
static struct mmc_platform_data *apq8064_sdc2_pdata;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
|
||||
static unsigned int sdc3_sup_clk_rates[] = {
|
||||
400000, 24000000, 48000000, 96000000, 192000000
|
||||
};
|
||||
|
||||
static struct mmc_platform_data sdc3_data = {
|
||||
.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
|
||||
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
|
||||
.sup_clk_table = sdc3_sup_clk_rates,
|
||||
.sup_clk_cnt = ARRAY_SIZE(sdc3_sup_clk_rates),
|
||||
.pclk_src_dfab = 1,
|
||||
.pin_data = &mmc_slot_pin_data[SDCC3],
|
||||
.vreg_data = &mmc_slot_vreg_data[SDCC3],
|
||||
.wpswitch_gpio = PM8921_GPIO_PM_TO_SYS(17),
|
||||
.wpswitch_polarity = 1,
|
||||
.status_gpio = 26,
|
||||
.status_irq = MSM_GPIO_TO_INT(26),
|
||||
.irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
|
||||
.is_status_gpio_active_low = 1,
|
||||
.xpc_cap = 1,
|
||||
.uhs_caps = (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
|
||||
MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 |
|
||||
MMC_CAP_UHS_SDR104 | MMC_CAP_MAX_CURRENT_800),
|
||||
.mpm_sdiowakeup_int = MSM_MPM_PIN_SDC3_DAT1,
|
||||
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
|
||||
};
|
||||
static struct mmc_platform_data *apq8064_sdc3_pdata = &sdc3_data;
|
||||
#else
|
||||
static struct mmc_platform_data *apq8064_sdc3_pdata;
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
|
||||
static unsigned int sdc4_sup_clk_rates[] = {
|
||||
400000, 24000000, 48000000
|
||||
};
|
||||
|
||||
static struct mmc_platform_data sdc4_data = {
|
||||
.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
|
||||
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
|
||||
.sup_clk_table = sdc4_sup_clk_rates,
|
||||
.sup_clk_cnt = ARRAY_SIZE(sdc4_sup_clk_rates),
|
||||
.pclk_src_dfab = 1,
|
||||
.pin_data = &mmc_slot_pin_data[SDCC4],
|
||||
.sdiowakeup_irq = MSM_GPIO_TO_INT(65),
|
||||
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
|
||||
};
|
||||
static struct mmc_platform_data *apq8064_sdc4_pdata = &sdc4_data;
|
||||
#else
|
||||
static struct mmc_platform_data *apq8064_sdc4_pdata;
|
||||
#endif
|
||||
|
||||
void __init apq8064_init_mmc(void)
|
||||
{
|
||||
if ((machine_is_apq8064_rumi3()) || machine_is_apq8064_sim()) {
|
||||
if (apq8064_sdc1_pdata) {
|
||||
if (machine_is_apq8064_sim())
|
||||
apq8064_sdc1_pdata->disable_bam = true;
|
||||
apq8064_sdc1_pdata->disable_runtime_pm = true;
|
||||
apq8064_sdc1_pdata->disable_cmd23 = true;
|
||||
}
|
||||
if (apq8064_sdc3_pdata) {
|
||||
if (machine_is_apq8064_sim())
|
||||
apq8064_sdc3_pdata->disable_bam = true;
|
||||
apq8064_sdc3_pdata->disable_runtime_pm = true;
|
||||
apq8064_sdc3_pdata->disable_cmd23 = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (apq8064_sdc1_pdata)
|
||||
apq8064_add_sdcc(1, apq8064_sdc1_pdata);
|
||||
|
||||
if (apq8064_sdc2_pdata)
|
||||
apq8064_add_sdcc(2, apq8064_sdc2_pdata);
|
||||
|
||||
if (apq8064_sdc3_pdata) {
|
||||
if (!machine_is_apq8064_cdp()) {
|
||||
apq8064_sdc3_pdata->wpswitch_gpio = 0;
|
||||
apq8064_sdc3_pdata->wpswitch_polarity = 0;
|
||||
}
|
||||
if (machine_is_mpq8064_cdp() || machine_is_mpq8064_hrd() ||
|
||||
machine_is_mpq8064_dtv()) {
|
||||
int rc;
|
||||
struct pm_gpio sd_card_det_init_cfg = {
|
||||
.direction = PM_GPIO_DIR_IN,
|
||||
.output_buffer = PM_GPIO_OUT_BUF_CMOS,
|
||||
.pull = PM_GPIO_PULL_UP_30,
|
||||
.vin_sel = PM_GPIO_VIN_S4,
|
||||
.out_strength = PM_GPIO_STRENGTH_NO,
|
||||
.function = PM_GPIO_FUNC_NORMAL,
|
||||
};
|
||||
|
||||
apq8064_sdc3_pdata->status_gpio =
|
||||
PM8921_GPIO_PM_TO_SYS(31);
|
||||
apq8064_sdc3_pdata->status_irq =
|
||||
PM8921_GPIO_IRQ(PM8921_IRQ_BASE, 31);
|
||||
rc = pm8xxx_gpio_config(apq8064_sdc3_pdata->status_gpio,
|
||||
&sd_card_det_init_cfg);
|
||||
if (rc) {
|
||||
pr_info("%s: SD_CARD_DET GPIO%d config "
|
||||
"failed(%d)\n", __func__,
|
||||
apq8064_sdc3_pdata->status_gpio, rc);
|
||||
apq8064_sdc3_pdata->status_gpio = 0;
|
||||
apq8064_sdc3_pdata->status_irq = 0;
|
||||
}
|
||||
}
|
||||
apq8064_add_sdcc(3, apq8064_sdc3_pdata);
|
||||
}
|
||||
|
||||
if (apq8064_sdc4_pdata)
|
||||
apq8064_add_sdcc(4, apq8064_sdc4_pdata);
|
||||
}
|
||||
3071
arch/arm/mach-msm/board-8064.c
Normal file
3071
arch/arm/mach-msm/board-8064.c
Normal file
File diff suppressed because it is too large
Load Diff
147
arch/arm/mach-msm/board-8064.h
Normal file
147
arch/arm/mach-msm/board-8064.h
Normal file
@@ -0,0 +1,147 @@
|
||||
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_MSM_BOARD_APQ8064_H
|
||||
#define __ARCH_ARM_MACH_MSM_BOARD_APQ8064_H
|
||||
|
||||
#include <linux/regulator/msm-gpio-regulator.h>
|
||||
#include <linux/mfd/pm8xxx/pm8921.h>
|
||||
#include <linux/mfd/pm8xxx/pm8821.h>
|
||||
#include <mach/msm_memtypes.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/rpm-regulator.h>
|
||||
#include <mach/msm_rtb.h>
|
||||
#include <mach/msm_cache_dump.h>
|
||||
|
||||
/* Macros assume PMIC GPIOs and MPPs start at 1 */
|
||||
#define PM8921_GPIO_BASE NR_GPIO_IRQS
|
||||
#define PM8921_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio - 1 + PM8921_GPIO_BASE)
|
||||
#define PM8921_MPP_BASE (PM8921_GPIO_BASE + PM8921_NR_GPIOS)
|
||||
#define PM8921_MPP_PM_TO_SYS(pm_mpp) (pm_mpp - 1 + PM8921_MPP_BASE)
|
||||
#define PM8921_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
|
||||
|
||||
#define PM8821_MPP_BASE (PM8921_MPP_BASE + PM8921_NR_MPPS)
|
||||
#define PM8821_MPP_PM_TO_SYS(pm_mpp) (pm_mpp - 1 + PM8821_MPP_BASE)
|
||||
#define PM8821_IRQ_BASE (PM8921_IRQ_BASE + PM8921_NR_IRQS)
|
||||
|
||||
#define TABLA_INTERRUPT_BASE (PM8821_IRQ_BASE + PM8821_NR_IRQS)
|
||||
|
||||
extern struct pm8xxx_regulator_platform_data
|
||||
msm8064_pm8921_regulator_pdata[] __devinitdata;
|
||||
|
||||
extern int msm8064_pm8921_regulator_pdata_len __devinitdata;
|
||||
|
||||
#define GPIO_VREG_ID_EXT_5V 0
|
||||
#define GPIO_VREG_ID_EXT_3P3V 1
|
||||
#define GPIO_VREG_ID_EXT_TS_SW 2
|
||||
#define GPIO_VREG_ID_EXT_MPP8 3
|
||||
|
||||
#define GPIO_VREG_ID_AVC_1P2V 0
|
||||
#define GPIO_VREG_ID_AVC_1P8V 1
|
||||
#define GPIO_VREG_ID_AVC_2P2V 2
|
||||
#define GPIO_VREG_ID_AVC_5V 3
|
||||
#define GPIO_VREG_ID_AVC_3P3V 4
|
||||
|
||||
#define APQ8064_EXT_3P3V_REG_EN_GPIO 77
|
||||
|
||||
extern struct gpio_regulator_platform_data
|
||||
apq8064_gpio_regulator_pdata[] __devinitdata;
|
||||
|
||||
extern struct gpio_regulator_platform_data
|
||||
mpq8064_gpio_regulator_pdata[] __devinitdata;
|
||||
|
||||
extern struct rpm_regulator_platform_data
|
||||
apq8064_rpm_regulator_pdata __devinitdata;
|
||||
|
||||
extern struct regulator_init_data msm8064_saw_regulator_pdata_8921_s5;
|
||||
extern struct regulator_init_data msm8064_saw_regulator_pdata_8921_s6;
|
||||
extern struct regulator_init_data msm8064_saw_regulator_pdata_8821_s0;
|
||||
extern struct regulator_init_data msm8064_saw_regulator_pdata_8821_s1;
|
||||
|
||||
struct mmc_platform_data;
|
||||
int __init apq8064_add_sdcc(unsigned int controller,
|
||||
struct mmc_platform_data *plat);
|
||||
|
||||
void apq8064_init_mmc(void);
|
||||
void apq8064_init_gpiomux(void);
|
||||
void apq8064_init_pmic(void);
|
||||
|
||||
extern struct msm_camera_board_info apq8064_camera_board_info;
|
||||
void apq8064_init_cam(void);
|
||||
|
||||
#define APQ_8064_GSBI1_QUP_I2C_BUS_ID 0
|
||||
#define APQ_8064_GSBI3_QUP_I2C_BUS_ID 3
|
||||
#define APQ_8064_GSBI4_QUP_I2C_BUS_ID 4
|
||||
#define APQ_8064_GSBI5_QUP_I2C_BUS_ID 5
|
||||
|
||||
unsigned char apq8064_hdmi_as_primary_selected(void);
|
||||
void apq8064_init_fb(void);
|
||||
void apq8064_allocate_fb_region(void);
|
||||
void apq8064_mdp_writeback(struct memtype_reserve *reserve_table);
|
||||
void __init apq8064_set_display_params(char *prim_panel, char *ext_panel);
|
||||
|
||||
void apq8064_init_gpu(void);
|
||||
void apq8064_pm8xxx_gpio_mpp_init(void);
|
||||
|
||||
#define PLATFORM_IS_MPQ8064() \
|
||||
(machine_is_mpq8064_hrd() || \
|
||||
machine_is_mpq8064_dtv() || \
|
||||
machine_is_mpq8064_cdp() \
|
||||
)
|
||||
|
||||
|
||||
#define GPIO_EXPANDER_IRQ_BASE (TABLA_INTERRUPT_BASE + \
|
||||
NR_TABLA_IRQS)
|
||||
#define GPIO_EXPANDER_GPIO_BASE (PM8821_MPP_BASE + PM8821_NR_MPPS)
|
||||
|
||||
#define GPIO_EPM_EXPANDER_BASE GPIO_EXPANDER_GPIO_BASE
|
||||
#define SX150X_EPM_NR_GPIOS 16
|
||||
#define SX150X_EPM_NR_IRQS 8
|
||||
|
||||
#define SX150X_EXP1_GPIO_BASE (GPIO_EPM_EXPANDER_BASE + \
|
||||
SX150X_EPM_NR_GPIOS)
|
||||
#define SX150X_EXP1_IRQ_BASE (GPIO_EXPANDER_IRQ_BASE + \
|
||||
SX150X_EPM_NR_IRQS)
|
||||
#define SX150X_EXP1_NR_IRQS 16
|
||||
#define SX150X_EXP1_NR_GPIOS 16
|
||||
|
||||
#define SX150X_EXP2_GPIO_BASE (SX150X_EXP1_GPIO_BASE + \
|
||||
SX150X_EXP1_NR_GPIOS)
|
||||
#define SX150X_EXP2_IRQ_BASE (SX150X_EXP1_IRQ_BASE + SX150X_EXP1_NR_IRQS)
|
||||
#define SX150X_EXP2_NR_IRQS 8
|
||||
#define SX150X_EXP2_NR_GPIOS 8
|
||||
|
||||
#define SX150X_EXP3_GPIO_BASE (SX150X_EXP2_GPIO_BASE + \
|
||||
SX150X_EXP2_NR_GPIOS)
|
||||
#define SX150X_EXP3_IRQ_BASE (SX150X_EXP2_IRQ_BASE + SX150X_EXP2_NR_IRQS)
|
||||
#define SX150X_EXP3_NR_IRQS 8
|
||||
#define SX150X_EXP3_NR_GPIOS 8
|
||||
|
||||
#define SX150X_EXP4_GPIO_BASE (SX150X_EXP3_GPIO_BASE + \
|
||||
SX150X_EXP3_NR_GPIOS)
|
||||
#define SX150X_EXP4_IRQ_BASE (SX150X_EXP3_IRQ_BASE + SX150X_EXP3_NR_IRQS)
|
||||
#define SX150X_EXP4_NR_IRQS 16
|
||||
#define SX150X_EXP4_NR_GPIOS 16
|
||||
|
||||
#define SX150X_GPIO(_expander, _pin) (SX150X_EXP##_expander##_GPIO_BASE + _pin)
|
||||
|
||||
enum {
|
||||
SX150X_EPM,
|
||||
SX150X_EXP1,
|
||||
SX150X_EXP2,
|
||||
SX150X_EXP3,
|
||||
SX150X_EXP4,
|
||||
};
|
||||
|
||||
extern struct msm_rtb_platform_data apq8064_rtb_pdata;
|
||||
extern struct msm_cache_dump_platform_data apq8064_cache_dump_pdata;
|
||||
#endif
|
||||
636
arch/arm/mach-msm/board-8930-camera.c
Normal file
636
arch/arm/mach-msm/board-8930-camera.c
Normal file
@@ -0,0 +1,636 @@
|
||||
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/msm_bus_board.h>
|
||||
#include <mach/gpiomux.h>
|
||||
#include "devices.h"
|
||||
#include "board-8930.h"
|
||||
|
||||
#ifdef CONFIG_MSM_CAMERA
|
||||
|
||||
#if (defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)) && \
|
||||
defined(CONFIG_I2C)
|
||||
|
||||
static struct i2c_board_info cam_expander_i2c_info[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("sx1508q", 0x22),
|
||||
.platform_data = &msm8930_sx150x_data[SX150X_CAM]
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_cam_expander_info cam_expander_info[] = {
|
||||
{
|
||||
cam_expander_i2c_info,
|
||||
MSM_8930_GSBI4_QUP_I2C_BUS_ID,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct gpiomux_setting cam_settings[] = {
|
||||
{
|
||||
.func = GPIOMUX_FUNC_GPIO, /*suspend*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_1, /*active 1*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_GPIO, /*active 2*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_1, /*active 3*/
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_5, /*active 4*/
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_6, /*active 5*/
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_2, /*active 6*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_3, /*active 7*/
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_GPIO, /*i2c suspend*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_KEEPER,
|
||||
},
|
||||
{
|
||||
.func = GPIOMUX_FUNC_2, /*active 9*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
|
||||
};
|
||||
|
||||
|
||||
static struct msm_gpiomux_config msm8930_cam_common_configs[] = {
|
||||
{
|
||||
.gpio = 2,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[2],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 3,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[1],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 4,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[9],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 5,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[1],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 76,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[2],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 107,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[2],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 54,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[2],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config msm8930_cam_2d_configs[] = {
|
||||
{
|
||||
.gpio = 18,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[3],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[8],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 19,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[3],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[8],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 20,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[3],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[8],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 21,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[3],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[8],
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
#define VFE_CAMIF_TIMER1_GPIO 2
|
||||
#define VFE_CAMIF_TIMER2_GPIO 3
|
||||
#define VFE_CAMIF_TIMER3_GPIO_INT 4
|
||||
static struct msm_camera_sensor_strobe_flash_data strobe_flash_xenon = {
|
||||
.flash_trigger = VFE_CAMIF_TIMER2_GPIO,
|
||||
.flash_charge = VFE_CAMIF_TIMER1_GPIO,
|
||||
.flash_charge_done = VFE_CAMIF_TIMER3_GPIO_INT,
|
||||
.flash_recharge_duration = 50000,
|
||||
.irq = MSM_GPIO_TO_INT(VFE_CAMIF_TIMER3_GPIO_INT),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MSM_CAMERA_FLASH
|
||||
static struct msm_camera_sensor_flash_src msm_flash_src = {
|
||||
.flash_sr_type = MSM_CAMERA_FLASH_SRC_EXT,
|
||||
._fsrc.ext_driver_src.led_en = VFE_CAMIF_TIMER1_GPIO,
|
||||
._fsrc.ext_driver_src.led_flash_en = VFE_CAMIF_TIMER2_GPIO,
|
||||
._fsrc.ext_driver_src.flash_id = MAM_CAMERA_EXT_LED_FLASH_TPS61310,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct msm_bus_vectors cam_init_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors cam_preview_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 27648000,
|
||||
.ib = 110592000,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors cam_video_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 140451840,
|
||||
.ib = 561807360,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 206807040,
|
||||
.ib = 488816640,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors cam_snapshot_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 274423680,
|
||||
.ib = 1097694720,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 540000000,
|
||||
.ib = 1350000000,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors cam_zsl_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 302071680,
|
||||
.ib = 1208286720,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 540000000,
|
||||
.ib = 1350000000,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_paths cam_bus_client_config[] = {
|
||||
{
|
||||
ARRAY_SIZE(cam_init_vectors),
|
||||
cam_init_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(cam_preview_vectors),
|
||||
cam_preview_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(cam_video_vectors),
|
||||
cam_video_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(cam_snapshot_vectors),
|
||||
cam_snapshot_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(cam_zsl_vectors),
|
||||
cam_zsl_vectors,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_scale_pdata cam_bus_client_pdata = {
|
||||
cam_bus_client_config,
|
||||
ARRAY_SIZE(cam_bus_client_config),
|
||||
.name = "msm_camera",
|
||||
};
|
||||
|
||||
static struct msm_camera_device_platform_data msm_camera_csi_device_data[] = {
|
||||
{
|
||||
.csid_core = 0,
|
||||
.is_csiphy = 1,
|
||||
.is_csid = 1,
|
||||
.is_ispif = 1,
|
||||
.is_vpe = 1,
|
||||
.cam_bus_scale_table = &cam_bus_client_pdata,
|
||||
},
|
||||
{
|
||||
.csid_core = 1,
|
||||
.is_csiphy = 1,
|
||||
.is_csid = 1,
|
||||
.is_ispif = 1,
|
||||
.is_vpe = 1,
|
||||
.cam_bus_scale_table = &cam_bus_client_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct camera_vreg_t msm_8930_back_cam_vreg[] = {
|
||||
{"cam_vdig", REG_LDO, 1200000, 1200000, 105000},
|
||||
{"cam_vio", REG_VS, 0, 0, 0},
|
||||
{"cam_vana", REG_LDO, 2800000, 2850000, 85600},
|
||||
{"cam_vaf", REG_LDO, 2800000, 2850000, 300000},
|
||||
};
|
||||
|
||||
static struct camera_vreg_t msm_8930_front_cam_vreg[] = {
|
||||
{"cam_vio", REG_VS, 0, 0, 0},
|
||||
{"cam_vana", REG_LDO, 2800000, 2850000, 85600},
|
||||
{"cam_vdig", REG_LDO, 1200000, 1200000, 105000},
|
||||
};
|
||||
|
||||
static struct gpio msm8930_common_cam_gpio[] = {
|
||||
{20, GPIOF_DIR_IN, "CAMIF_I2C_DATA"},
|
||||
{21, GPIOF_DIR_IN, "CAMIF_I2C_CLK"},
|
||||
};
|
||||
|
||||
static struct gpio msm8930_front_cam_gpio[] = {
|
||||
{4, GPIOF_DIR_IN, "CAMIF_MCLK"},
|
||||
{76, GPIOF_DIR_OUT, "CAM_RESET"},
|
||||
};
|
||||
|
||||
static struct gpio msm8930_back_cam_gpio[] = {
|
||||
{5, GPIOF_DIR_IN, "CAMIF_MCLK"},
|
||||
{107, GPIOF_DIR_OUT, "CAM_RESET"},
|
||||
{54, GPIOF_DIR_OUT, "CAM_STBY_N"},
|
||||
};
|
||||
|
||||
static struct msm_gpio_set_tbl msm8930_front_cam_gpio_set_tbl[] = {
|
||||
{76, GPIOF_OUT_INIT_LOW, 1000},
|
||||
{76, GPIOF_OUT_INIT_HIGH, 4000},
|
||||
};
|
||||
|
||||
static struct msm_gpio_set_tbl msm8930_back_cam_gpio_set_tbl[] = {
|
||||
{54, GPIOF_OUT_INIT_LOW, 1000},
|
||||
{54, GPIOF_OUT_INIT_HIGH, 4000},
|
||||
{107, GPIOF_OUT_INIT_LOW, 1000},
|
||||
{107, GPIOF_OUT_INIT_HIGH, 4000},
|
||||
};
|
||||
|
||||
static struct msm_camera_gpio_conf msm_8930_front_cam_gpio_conf = {
|
||||
.cam_gpiomux_conf_tbl = msm8930_cam_2d_configs,
|
||||
.cam_gpiomux_conf_tbl_size = ARRAY_SIZE(msm8930_cam_2d_configs),
|
||||
.cam_gpio_common_tbl = msm8930_common_cam_gpio,
|
||||
.cam_gpio_common_tbl_size = ARRAY_SIZE(msm8930_common_cam_gpio),
|
||||
.cam_gpio_req_tbl = msm8930_front_cam_gpio,
|
||||
.cam_gpio_req_tbl_size = ARRAY_SIZE(msm8930_front_cam_gpio),
|
||||
.cam_gpio_set_tbl = msm8930_front_cam_gpio_set_tbl,
|
||||
.cam_gpio_set_tbl_size = ARRAY_SIZE(msm8930_front_cam_gpio_set_tbl),
|
||||
};
|
||||
|
||||
static struct msm_camera_gpio_conf msm_8930_back_cam_gpio_conf = {
|
||||
.cam_gpiomux_conf_tbl = msm8930_cam_2d_configs,
|
||||
.cam_gpiomux_conf_tbl_size = ARRAY_SIZE(msm8930_cam_2d_configs),
|
||||
.cam_gpio_common_tbl = msm8930_common_cam_gpio,
|
||||
.cam_gpio_common_tbl_size = ARRAY_SIZE(msm8930_common_cam_gpio),
|
||||
.cam_gpio_req_tbl = msm8930_back_cam_gpio,
|
||||
.cam_gpio_req_tbl_size = ARRAY_SIZE(msm8930_back_cam_gpio),
|
||||
.cam_gpio_set_tbl = msm8930_back_cam_gpio_set_tbl,
|
||||
.cam_gpio_set_tbl_size = ARRAY_SIZE(msm8930_back_cam_gpio_set_tbl),
|
||||
};
|
||||
|
||||
static struct i2c_board_info msm_act_main_cam_i2c_info = {
|
||||
I2C_BOARD_INFO("msm_actuator", 0x11),
|
||||
};
|
||||
|
||||
static struct msm_actuator_info msm_act_main_cam_0_info = {
|
||||
.board_info = &msm_act_main_cam_i2c_info,
|
||||
.cam_name = MSM_ACTUATOR_MAIN_CAM_0,
|
||||
.bus_id = MSM_8930_GSBI4_QUP_I2C_BUS_ID,
|
||||
.vcm_pwd = 0,
|
||||
.vcm_enable = 0,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_flash_data flash_imx074 = {
|
||||
.flash_type = MSM_CAMERA_FLASH_LED,
|
||||
#ifdef CONFIG_MSM_CAMERA_FLASH
|
||||
.flash_src = &msm_flash_src
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct msm_camera_csi_lane_params imx074_csi_lane_params = {
|
||||
.csi_lane_assign = 0xE4,
|
||||
.csi_lane_mask = 0xF,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_platform_info sensor_board_info_imx074 = {
|
||||
.mount_angle = 90,
|
||||
.cam_vreg = msm_8930_back_cam_vreg,
|
||||
.num_vreg = ARRAY_SIZE(msm_8930_back_cam_vreg),
|
||||
.gpio_conf = &msm_8930_back_cam_gpio_conf,
|
||||
.csi_lane_params = &imx074_csi_lane_params,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_info msm_camera_sensor_imx074_data = {
|
||||
.sensor_name = "imx074",
|
||||
.pdata = &msm_camera_csi_device_data[0],
|
||||
.flash_data = &flash_imx074,
|
||||
.strobe_flash_data = &strobe_flash_xenon,
|
||||
.sensor_platform_info = &sensor_board_info_imx074,
|
||||
.csi_if = 1,
|
||||
.camera_type = BACK_CAMERA_2D,
|
||||
.sensor_type = BAYER_SENSOR,
|
||||
.actuator_info = &msm_act_main_cam_0_info,
|
||||
};
|
||||
|
||||
static struct camera_vreg_t msm_8930_mt9m114_vreg[] = {
|
||||
{"cam_vio", REG_VS, 0, 0, 0},
|
||||
{"cam_vdig", REG_LDO, 1200000, 1200000, 105000},
|
||||
{"cam_vana", REG_LDO, 2800000, 2850000, 85600},
|
||||
{"cam_vaf", REG_LDO, 2800000, 2850000, 300000},
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_flash_data flash_mt9m114 = {
|
||||
.flash_type = MSM_CAMERA_FLASH_NONE
|
||||
};
|
||||
|
||||
static struct msm_camera_csi_lane_params mt9m114_csi_lane_params = {
|
||||
.csi_lane_assign = 0xE4,
|
||||
.csi_lane_mask = 0x1,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_platform_info sensor_board_info_mt9m114 = {
|
||||
.mount_angle = 90,
|
||||
.cam_vreg = msm_8930_mt9m114_vreg,
|
||||
.num_vreg = ARRAY_SIZE(msm_8930_mt9m114_vreg),
|
||||
.gpio_conf = &msm_8930_front_cam_gpio_conf,
|
||||
.csi_lane_params = &mt9m114_csi_lane_params,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_info msm_camera_sensor_mt9m114_data = {
|
||||
.sensor_name = "mt9m114",
|
||||
.pdata = &msm_camera_csi_device_data[1],
|
||||
.flash_data = &flash_mt9m114,
|
||||
.sensor_platform_info = &sensor_board_info_mt9m114,
|
||||
.csi_if = 1,
|
||||
.camera_type = FRONT_CAMERA_2D,
|
||||
.sensor_type = YUV_SENSOR,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_flash_data flash_ov2720 = {
|
||||
.flash_type = MSM_CAMERA_FLASH_NONE,
|
||||
};
|
||||
|
||||
static struct msm_camera_csi_lane_params ov2720_csi_lane_params = {
|
||||
.csi_lane_assign = 0xE4,
|
||||
.csi_lane_mask = 0x3,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_platform_info sensor_board_info_ov2720 = {
|
||||
.mount_angle = 0,
|
||||
.cam_vreg = msm_8930_front_cam_vreg,
|
||||
.num_vreg = ARRAY_SIZE(msm_8930_front_cam_vreg),
|
||||
.gpio_conf = &msm_8930_front_cam_gpio_conf,
|
||||
.csi_lane_params = &ov2720_csi_lane_params,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_info msm_camera_sensor_ov2720_data = {
|
||||
.sensor_name = "ov2720",
|
||||
.pdata = &msm_camera_csi_device_data[1],
|
||||
.flash_data = &flash_ov2720,
|
||||
.sensor_platform_info = &sensor_board_info_ov2720,
|
||||
.csi_if = 1,
|
||||
.camera_type = FRONT_CAMERA_2D,
|
||||
.sensor_type = BAYER_SENSOR,
|
||||
};
|
||||
|
||||
static struct camera_vreg_t msm_8930_s5k3l1yx_vreg[] = {
|
||||
{"cam_vdig", REG_LDO, 1200000, 1200000, 105000},
|
||||
{"cam_vana", REG_LDO, 2800000, 2850000, 85600},
|
||||
{"cam_vio", REG_VS, 0, 0, 0},
|
||||
{"cam_vaf", REG_LDO, 2800000, 2850000, 300000},
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_flash_data flash_s5k3l1yx = {
|
||||
.flash_type = MSM_CAMERA_FLASH_LED,
|
||||
.flash_src = &msm_flash_src
|
||||
};
|
||||
|
||||
static struct msm_camera_csi_lane_params s5k3l1yx_csi_lane_params = {
|
||||
.csi_lane_assign = 0xE4,
|
||||
.csi_lane_mask = 0xF,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_platform_info sensor_board_info_s5k3l1yx = {
|
||||
.mount_angle = 90,
|
||||
.cam_vreg = msm_8930_s5k3l1yx_vreg,
|
||||
.num_vreg = ARRAY_SIZE(msm_8930_s5k3l1yx_vreg),
|
||||
.gpio_conf = &msm_8930_back_cam_gpio_conf,
|
||||
.csi_lane_params = &s5k3l1yx_csi_lane_params,
|
||||
};
|
||||
|
||||
static struct msm_actuator_info msm_act_main_cam_2_info = {
|
||||
.board_info = &msm_act_main_cam_i2c_info,
|
||||
.cam_name = MSM_ACTUATOR_MAIN_CAM_2,
|
||||
.bus_id = MSM_8930_GSBI4_QUP_I2C_BUS_ID,
|
||||
.vcm_pwd = 0,
|
||||
.vcm_enable = 0,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_info msm_camera_sensor_s5k3l1yx_data = {
|
||||
.sensor_name = "s5k3l1yx",
|
||||
.pdata = &msm_camera_csi_device_data[0],
|
||||
.flash_data = &flash_s5k3l1yx,
|
||||
.sensor_platform_info = &sensor_board_info_s5k3l1yx,
|
||||
.csi_if = 1,
|
||||
.camera_type = BACK_CAMERA_2D,
|
||||
.sensor_type = BAYER_SENSOR,
|
||||
.actuator_info = &msm_act_main_cam_2_info,
|
||||
};
|
||||
|
||||
static struct platform_device msm_camera_server = {
|
||||
.name = "msm_cam_server",
|
||||
.id = 0,
|
||||
};
|
||||
|
||||
void __init msm8930_init_cam(void)
|
||||
{
|
||||
msm_gpiomux_install(msm8930_cam_common_configs,
|
||||
ARRAY_SIZE(msm8930_cam_common_configs));
|
||||
|
||||
if (machine_is_msm8930_cdp()) {
|
||||
struct msm_camera_sensor_info *s_info;
|
||||
s_info = &msm_camera_sensor_s5k3l1yx_data;
|
||||
s_info->sensor_platform_info->mount_angle = 0;
|
||||
msm_flash_src._fsrc.ext_driver_src.led_en =
|
||||
GPIO_CAM_GP_LED_EN1;
|
||||
msm_flash_src._fsrc.ext_driver_src.led_flash_en =
|
||||
GPIO_CAM_GP_LED_EN2;
|
||||
#if defined(CONFIG_I2C) && (defined(CONFIG_GPIO_SX150X) || \
|
||||
defined(CONFIG_GPIO_SX150X_MODULE))
|
||||
msm_flash_src._fsrc.ext_driver_src.expander_info =
|
||||
cam_expander_info;
|
||||
#endif
|
||||
}
|
||||
|
||||
platform_device_register(&msm_camera_server);
|
||||
platform_device_register(&msm8960_device_csiphy0);
|
||||
platform_device_register(&msm8960_device_csiphy1);
|
||||
platform_device_register(&msm8960_device_csid0);
|
||||
platform_device_register(&msm8960_device_csid1);
|
||||
platform_device_register(&msm8960_device_ispif);
|
||||
platform_device_register(&msm8960_device_vfe);
|
||||
platform_device_register(&msm8960_device_vpe);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_I2C
|
||||
struct i2c_board_info msm8930_camera_i2c_boardinfo[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("imx074", 0x1A),
|
||||
.platform_data = &msm_camera_sensor_imx074_data,
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("ov2720", 0x6C),
|
||||
.platform_data = &msm_camera_sensor_ov2720_data,
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("mt9m114", 0x48),
|
||||
.platform_data = &msm_camera_sensor_mt9m114_data,
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("s5k3l1yx", 0x20),
|
||||
.platform_data = &msm_camera_sensor_s5k3l1yx_data,
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("tps61310", 0x66),
|
||||
},
|
||||
};
|
||||
|
||||
struct msm_camera_board_info msm8930_camera_board_info = {
|
||||
.board_info = msm8930_camera_i2c_boardinfo,
|
||||
.num_i2c_board_info = ARRAY_SIZE(msm8930_camera_i2c_boardinfo),
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
791
arch/arm/mach-msm/board-8930-display.c
Normal file
791
arch/arm/mach-msm/board-8930-display.c
Normal file
@@ -0,0 +1,791 @@
|
||||
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <mach/msm_bus_board.h>
|
||||
#include <mach/msm_memtypes.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/gpiomux.h>
|
||||
#include <mach/socinfo.h>
|
||||
#include <linux/ion.h>
|
||||
#include <mach/ion.h>
|
||||
|
||||
#include "devices.h"
|
||||
#include "board-8930.h"
|
||||
|
||||
#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
|
||||
#define MSM_FB_PRIM_BUF_SIZE \
|
||||
(roundup((1920 * 1088 * 4), 4096) * 3) /* 4 bpp x 3 pages */
|
||||
#else
|
||||
#define MSM_FB_PRIM_BUF_SIZE \
|
||||
(roundup((1920 * 1088 * 4), 4096) * 2) /* 4 bpp x 2 pages */
|
||||
#endif
|
||||
/* Note: must be multiple of 4096 */
|
||||
#define MSM_FB_SIZE roundup(MSM_FB_PRIM_BUF_SIZE, 4096)
|
||||
|
||||
#ifdef CONFIG_FB_MSM_OVERLAY0_WRITEBACK
|
||||
#define MSM_FB_OVERLAY0_WRITEBACK_SIZE roundup((1376 * 768 * 3 * 2), 4096)
|
||||
#else
|
||||
#define MSM_FB_OVERLAY0_WRITEBACK_SIZE (0)
|
||||
#endif /* CONFIG_FB_MSM_OVERLAY0_WRITEBACK */
|
||||
|
||||
#ifdef CONFIG_FB_MSM_OVERLAY1_WRITEBACK
|
||||
#define MSM_FB_OVERLAY1_WRITEBACK_SIZE roundup((1920 * 1088 * 3 * 2), 4096)
|
||||
#else
|
||||
#define MSM_FB_OVERLAY1_WRITEBACK_SIZE (0)
|
||||
#endif /* CONFIG_FB_MSM_OVERLAY1_WRITEBACK */
|
||||
|
||||
#define MDP_VSYNC_GPIO 0
|
||||
|
||||
#define MIPI_CMD_NOVATEK_QHD_PANEL_NAME "mipi_cmd_novatek_qhd"
|
||||
#define MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME "mipi_video_novatek_qhd"
|
||||
#define MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME "mipi_video_toshiba_wsvga"
|
||||
#define MIPI_VIDEO_CHIMEI_WXGA_PANEL_NAME "mipi_video_chimei_wxga"
|
||||
#define MIPI_VIDEO_SIMULATOR_VGA_PANEL_NAME "mipi_video_simulator_vga"
|
||||
#define MIPI_CMD_RENESAS_FWVGA_PANEL_NAME "mipi_cmd_renesas_fwvga"
|
||||
#define HDMI_PANEL_NAME "hdmi_msm"
|
||||
#define TVOUT_PANEL_NAME "tvout_msm"
|
||||
|
||||
static struct resource msm_fb_resources[] = {
|
||||
{
|
||||
.flags = IORESOURCE_DMA,
|
||||
}
|
||||
};
|
||||
|
||||
static int msm_fb_detect_panel(const char *name)
|
||||
{
|
||||
if (!strncmp(name, MIPI_CMD_NOVATEK_QHD_PANEL_NAME,
|
||||
strnlen(MIPI_CMD_NOVATEK_QHD_PANEL_NAME,
|
||||
PANEL_NAME_MAX_LEN)))
|
||||
return 0;
|
||||
|
||||
#if !defined(CONFIG_FB_MSM_LVDS_MIPI_PANEL_DETECT) && \
|
||||
!defined(CONFIG_FB_MSM_MIPI_PANEL_DETECT)
|
||||
if (!strncmp(name, MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME,
|
||||
strnlen(MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME,
|
||||
PANEL_NAME_MAX_LEN)))
|
||||
return 0;
|
||||
|
||||
if (!strncmp(name, MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
|
||||
strnlen(MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
|
||||
PANEL_NAME_MAX_LEN)))
|
||||
return 0;
|
||||
|
||||
if (!strncmp(name, MIPI_VIDEO_SIMULATOR_VGA_PANEL_NAME,
|
||||
strnlen(MIPI_VIDEO_SIMULATOR_VGA_PANEL_NAME,
|
||||
PANEL_NAME_MAX_LEN)))
|
||||
return 0;
|
||||
|
||||
if (!strncmp(name, MIPI_CMD_RENESAS_FWVGA_PANEL_NAME,
|
||||
strnlen(MIPI_CMD_RENESAS_FWVGA_PANEL_NAME,
|
||||
PANEL_NAME_MAX_LEN)))
|
||||
return 0;
|
||||
#endif
|
||||
|
||||
if (!strncmp(name, HDMI_PANEL_NAME,
|
||||
strnlen(HDMI_PANEL_NAME,
|
||||
PANEL_NAME_MAX_LEN)))
|
||||
return 0;
|
||||
|
||||
if (!strncmp(name, TVOUT_PANEL_NAME,
|
||||
strnlen(TVOUT_PANEL_NAME,
|
||||
PANEL_NAME_MAX_LEN)))
|
||||
return 0;
|
||||
|
||||
pr_warning("%s: not supported '%s'", __func__, name);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static struct msm_fb_platform_data msm_fb_pdata = {
|
||||
.detect_client = msm_fb_detect_panel,
|
||||
};
|
||||
|
||||
static struct platform_device msm_fb_device = {
|
||||
.name = "msm_fb",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(msm_fb_resources),
|
||||
.resource = msm_fb_resources,
|
||||
.dev.platform_data = &msm_fb_pdata,
|
||||
};
|
||||
|
||||
static bool dsi_power_on;
|
||||
|
||||
/*
|
||||
* TODO: When physical 8930/PM8038 hardware becomes
|
||||
* available, replace mipi_dsi_cdp_panel_power with
|
||||
* appropriate function.
|
||||
*/
|
||||
#define DISP_RST_GPIO 58
|
||||
static int mipi_dsi_cdp_panel_power(int on)
|
||||
{
|
||||
static struct regulator *reg_l8, *reg_l23, *reg_l2;
|
||||
int rc;
|
||||
|
||||
pr_debug("%s: state : %d\n", __func__, on);
|
||||
|
||||
if (!dsi_power_on) {
|
||||
|
||||
reg_l8 = regulator_get(&msm_mipi_dsi1_device.dev,
|
||||
"dsi_vdc");
|
||||
if (IS_ERR(reg_l8)) {
|
||||
pr_err("could not get 8038_l8, rc = %ld\n",
|
||||
PTR_ERR(reg_l8));
|
||||
return -ENODEV;
|
||||
}
|
||||
reg_l23 = regulator_get(&msm_mipi_dsi1_device.dev,
|
||||
"dsi_vddio");
|
||||
if (IS_ERR(reg_l23)) {
|
||||
pr_err("could not get 8038_l23, rc = %ld\n",
|
||||
PTR_ERR(reg_l23));
|
||||
return -ENODEV;
|
||||
}
|
||||
reg_l2 = regulator_get(&msm_mipi_dsi1_device.dev,
|
||||
"dsi_vdda");
|
||||
if (IS_ERR(reg_l2)) {
|
||||
pr_err("could not get 8038_l2, rc = %ld\n",
|
||||
PTR_ERR(reg_l2));
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_set_voltage(reg_l8, 2800000, 3000000);
|
||||
if (rc) {
|
||||
pr_err("set_voltage l8 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
rc = regulator_set_voltage(reg_l23, 1800000, 1800000);
|
||||
if (rc) {
|
||||
pr_err("set_voltage l23 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
rc = regulator_set_voltage(reg_l2, 1200000, 1200000);
|
||||
if (rc) {
|
||||
pr_err("set_voltage l2 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
rc = gpio_request(DISP_RST_GPIO, "disp_rst_n");
|
||||
if (rc) {
|
||||
pr_err("request gpio DISP_RST_GPIO failed, rc=%d\n",
|
||||
rc);
|
||||
gpio_free(DISP_RST_GPIO);
|
||||
return -ENODEV;
|
||||
}
|
||||
dsi_power_on = true;
|
||||
}
|
||||
if (on) {
|
||||
rc = regulator_set_optimum_mode(reg_l8, 100000);
|
||||
if (rc < 0) {
|
||||
pr_err("set_optimum_mode l8 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
rc = regulator_set_optimum_mode(reg_l23, 100000);
|
||||
if (rc < 0) {
|
||||
pr_err("set_optimum_mode l23 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
rc = regulator_set_optimum_mode(reg_l2, 100000);
|
||||
if (rc < 0) {
|
||||
pr_err("set_optimum_mode l2 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
rc = regulator_enable(reg_l8);
|
||||
if (rc) {
|
||||
pr_err("enable l8 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_enable(reg_l23);
|
||||
if (rc) {
|
||||
pr_err("enable l8 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_enable(reg_l2);
|
||||
if (rc) {
|
||||
pr_err("enable l2 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
usleep(10000);
|
||||
gpio_set_value(DISP_RST_GPIO, 1);
|
||||
usleep(10);
|
||||
gpio_set_value(DISP_RST_GPIO, 0);
|
||||
usleep(20);
|
||||
gpio_set_value(DISP_RST_GPIO, 1);
|
||||
} else {
|
||||
|
||||
gpio_set_value(DISP_RST_GPIO, 0);
|
||||
|
||||
rc = regulator_disable(reg_l2);
|
||||
if (rc) {
|
||||
pr_err("disable reg_l2 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_disable(reg_l8);
|
||||
if (rc) {
|
||||
pr_err("disable reg_l8 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_disable(reg_l23);
|
||||
if (rc) {
|
||||
pr_err("disable reg_l23 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_set_optimum_mode(reg_l8, 100);
|
||||
if (rc < 0) {
|
||||
pr_err("set_optimum_mode l8 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
rc = regulator_set_optimum_mode(reg_l23, 100);
|
||||
if (rc < 0) {
|
||||
pr_err("set_optimum_mode l23 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
rc = regulator_set_optimum_mode(reg_l2, 100);
|
||||
if (rc < 0) {
|
||||
pr_err("set_optimum_mode l2 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mipi_dsi_panel_power(int on)
|
||||
{
|
||||
pr_debug("%s: on=%d\n", __func__, on);
|
||||
|
||||
return mipi_dsi_cdp_panel_power(on);
|
||||
}
|
||||
|
||||
static struct mipi_dsi_platform_data mipi_dsi_pdata = {
|
||||
.vsync_gpio = MDP_VSYNC_GPIO,
|
||||
.dsi_power_save = mipi_dsi_panel_power,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MSM_BUS_SCALING
|
||||
|
||||
static struct msm_bus_vectors mdp_init_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
|
||||
static struct msm_bus_vectors hdmi_as_primary_vectors[] = {
|
||||
/* If HDMI is used as primary */
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 2000000000,
|
||||
.ib = 2000000000,
|
||||
},
|
||||
};
|
||||
static struct msm_bus_paths mdp_bus_scale_usecases[] = {
|
||||
{
|
||||
ARRAY_SIZE(mdp_init_vectors),
|
||||
mdp_init_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(hdmi_as_primary_vectors),
|
||||
hdmi_as_primary_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(hdmi_as_primary_vectors),
|
||||
hdmi_as_primary_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(hdmi_as_primary_vectors),
|
||||
hdmi_as_primary_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(hdmi_as_primary_vectors),
|
||||
hdmi_as_primary_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(hdmi_as_primary_vectors),
|
||||
hdmi_as_primary_vectors,
|
||||
},
|
||||
};
|
||||
#else
|
||||
static struct msm_bus_vectors mdp_ui_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 216000000 * 2,
|
||||
.ib = 270000000 * 2,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors mdp_vga_vectors[] = {
|
||||
/* VGA and less video */
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 216000000 * 2,
|
||||
.ib = 270000000 * 2,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors mdp_720p_vectors[] = {
|
||||
/* 720p and less video */
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 230400000 * 2,
|
||||
.ib = 288000000 * 2,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors mdp_1080p_vectors[] = {
|
||||
/* 1080p and less video */
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 334080000 * 2,
|
||||
.ib = 417600000 * 2,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_paths mdp_bus_scale_usecases[] = {
|
||||
{
|
||||
ARRAY_SIZE(mdp_init_vectors),
|
||||
mdp_init_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(mdp_ui_vectors),
|
||||
mdp_ui_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(mdp_ui_vectors),
|
||||
mdp_ui_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(mdp_vga_vectors),
|
||||
mdp_vga_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(mdp_720p_vectors),
|
||||
mdp_720p_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(mdp_1080p_vectors),
|
||||
mdp_1080p_vectors,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct msm_bus_scale_pdata mdp_bus_scale_pdata = {
|
||||
mdp_bus_scale_usecases,
|
||||
ARRAY_SIZE(mdp_bus_scale_usecases),
|
||||
.name = "mdp",
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
|
||||
static int mdp_core_clk_rate_table[] = {
|
||||
200000000,
|
||||
200000000,
|
||||
200000000,
|
||||
200000000,
|
||||
};
|
||||
#else
|
||||
static int mdp_core_clk_rate_table[] = {
|
||||
85330000,
|
||||
128000000,
|
||||
160000000,
|
||||
200000000,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct msm_panel_common_pdata mdp_pdata = {
|
||||
.gpio = MDP_VSYNC_GPIO,
|
||||
#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
|
||||
.mdp_core_clk_rate = 200000000,
|
||||
#else
|
||||
.mdp_core_clk_rate = 85330000,
|
||||
#endif
|
||||
.mdp_core_clk_table = mdp_core_clk_rate_table,
|
||||
.num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
|
||||
#ifdef CONFIG_MSM_BUS_SCALING
|
||||
.mdp_bus_scale_table = &mdp_bus_scale_pdata,
|
||||
#endif
|
||||
.mdp_rev = MDP_REV_42,
|
||||
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
|
||||
.mem_hid = BIT(ION_CP_MM_HEAP_ID),
|
||||
#else
|
||||
.mem_hid = MEMTYPE_EBI1,
|
||||
#endif
|
||||
};
|
||||
|
||||
void __init msm8930_mdp_writeback(struct memtype_reserve* reserve_table)
|
||||
{
|
||||
mdp_pdata.ov0_wb_size = MSM_FB_OVERLAY0_WRITEBACK_SIZE;
|
||||
mdp_pdata.ov1_wb_size = MSM_FB_OVERLAY1_WRITEBACK_SIZE;
|
||||
#if defined(CONFIG_ANDROID_PMEM) && !defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
|
||||
reserve_table[mdp_pdata.mem_hid].size +=
|
||||
mdp_pdata.ov0_wb_size;
|
||||
reserve_table[mdp_pdata.mem_hid].size +=
|
||||
mdp_pdata.ov1_wb_size;
|
||||
#endif
|
||||
}
|
||||
|
||||
#define LPM_CHANNEL0 0
|
||||
static int toshiba_gpio[] = {LPM_CHANNEL0};
|
||||
|
||||
static struct mipi_dsi_panel_platform_data toshiba_pdata = {
|
||||
.gpio = toshiba_gpio,
|
||||
};
|
||||
|
||||
static struct platform_device mipi_dsi_toshiba_panel_device = {
|
||||
.name = "mipi_toshiba",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &toshiba_pdata,
|
||||
}
|
||||
};
|
||||
|
||||
#define FPGA_3D_GPIO_CONFIG_ADDR 0xB5
|
||||
|
||||
static struct mipi_dsi_phy_ctrl dsi_novatek_cmd_mode_phy_db = {
|
||||
|
||||
/* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */
|
||||
{0x0F, 0x0a, 0x04, 0x00, 0x20}, /* regulator */
|
||||
/* timing */
|
||||
{0xab, 0x8a, 0x18, 0x00, 0x92, 0x97, 0x1b, 0x8c,
|
||||
0x0c, 0x03, 0x04, 0xa0},
|
||||
{0x5f, 0x00, 0x00, 0x10}, /* phy ctrl */
|
||||
{0xff, 0x00, 0x06, 0x00}, /* strength */
|
||||
/* pll control */
|
||||
{0x40, 0xf9, 0x30, 0xda, 0x00, 0x40, 0x03, 0x62,
|
||||
0x40, 0x07, 0x03,
|
||||
0x00, 0x1a, 0x00, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01},
|
||||
};
|
||||
|
||||
static struct mipi_dsi_panel_platform_data novatek_pdata = {
|
||||
.fpga_3d_config_addr = FPGA_3D_GPIO_CONFIG_ADDR,
|
||||
.fpga_ctrl_mode = FPGA_SPI_INTF,
|
||||
.phy_ctrl_settings = &dsi_novatek_cmd_mode_phy_db,
|
||||
.dlane_swap = 0x1,
|
||||
.enable_wled_bl_ctrl = 0x1,
|
||||
};
|
||||
|
||||
static struct platform_device mipi_dsi_novatek_panel_device = {
|
||||
.name = "mipi_novatek",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &novatek_pdata,
|
||||
}
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
|
||||
static struct resource hdmi_msm_resources[] = {
|
||||
{
|
||||
.name = "hdmi_msm_qfprom_addr",
|
||||
.start = 0x00700000,
|
||||
.end = 0x007060FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = "hdmi_msm_hdmi_addr",
|
||||
.start = 0x04A00000,
|
||||
.end = 0x04A00FFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = "hdmi_msm_irq",
|
||||
.start = HDMI_IRQ,
|
||||
.end = HDMI_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static int hdmi_enable_5v(int on);
|
||||
static int hdmi_core_power(int on, int show);
|
||||
static int hdmi_cec_power(int on);
|
||||
|
||||
static struct msm_hdmi_platform_data hdmi_msm_data = {
|
||||
.irq = HDMI_IRQ,
|
||||
.enable_5v = hdmi_enable_5v,
|
||||
.core_power = hdmi_core_power,
|
||||
.cec_power = hdmi_cec_power,
|
||||
};
|
||||
|
||||
static struct platform_device hdmi_msm_device = {
|
||||
.name = "hdmi_msm",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(hdmi_msm_resources),
|
||||
.resource = hdmi_msm_resources,
|
||||
.dev.platform_data = &hdmi_msm_data,
|
||||
};
|
||||
#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
|
||||
|
||||
#ifdef CONFIG_FB_MSM_WRITEBACK_MSM_PANEL
|
||||
static struct platform_device wfd_panel_device = {
|
||||
.name = "wfd_panel",
|
||||
.id = 0,
|
||||
.dev.platform_data = NULL,
|
||||
};
|
||||
|
||||
static struct platform_device wfd_device = {
|
||||
.name = "msm_wfd",
|
||||
.id = -1,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MSM_BUS_SCALING
|
||||
static struct msm_bus_vectors dtv_bus_init_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
|
||||
static struct msm_bus_vectors dtv_bus_def_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 2000000000,
|
||||
.ib = 2000000000,
|
||||
},
|
||||
};
|
||||
#else
|
||||
static struct msm_bus_vectors dtv_bus_def_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_MDP_PORT0,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 566092800 * 2,
|
||||
.ib = 707616000 * 2,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct msm_bus_paths dtv_bus_scale_usecases[] = {
|
||||
{
|
||||
ARRAY_SIZE(dtv_bus_init_vectors),
|
||||
dtv_bus_init_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(dtv_bus_def_vectors),
|
||||
dtv_bus_def_vectors,
|
||||
},
|
||||
};
|
||||
static struct msm_bus_scale_pdata dtv_bus_scale_pdata = {
|
||||
dtv_bus_scale_usecases,
|
||||
ARRAY_SIZE(dtv_bus_scale_usecases),
|
||||
.name = "dtv",
|
||||
};
|
||||
|
||||
static struct lcdc_platform_data dtv_pdata = {
|
||||
.bus_scale_table = &dtv_bus_scale_pdata,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
|
||||
static int hdmi_enable_5v(int on)
|
||||
{
|
||||
static struct regulator *reg_ext_5v; /* HDMI_5V */
|
||||
static int prev_on;
|
||||
int rc;
|
||||
|
||||
if (on == prev_on)
|
||||
return 0;
|
||||
|
||||
if (!reg_ext_5v) {
|
||||
reg_ext_5v = regulator_get(&hdmi_msm_device.dev, "hdmi_mvs");
|
||||
if (IS_ERR(reg_ext_5v)) {
|
||||
pr_err("'%s' regulator not found, rc=%ld\n",
|
||||
"hdmi_mvs", IS_ERR(reg_ext_5v));
|
||||
reg_ext_5v = NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
if (on) {
|
||||
rc = regulator_enable(reg_ext_5v);
|
||||
if (rc) {
|
||||
pr_err("'%s' regulator enable failed, rc=%d\n",
|
||||
"reg_ext_5v", rc);
|
||||
return rc;
|
||||
}
|
||||
pr_debug("%s(on): success\n", __func__);
|
||||
} else {
|
||||
rc = regulator_disable(reg_ext_5v);
|
||||
if (rc)
|
||||
pr_warning("'%s' regulator disable failed, rc=%d\n",
|
||||
"reg_ext_5v", rc);
|
||||
pr_debug("%s(off): success\n", __func__);
|
||||
}
|
||||
|
||||
prev_on = on;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hdmi_core_power(int on, int show)
|
||||
{
|
||||
/* Both HDMI "avdd" and "vcc" are powered by 8038_l23 regulator */
|
||||
static struct regulator *reg_8038_l23;
|
||||
static int prev_on;
|
||||
int rc;
|
||||
|
||||
if (on == prev_on)
|
||||
return 0;
|
||||
|
||||
if (!reg_8038_l23) {
|
||||
reg_8038_l23 = regulator_get(&hdmi_msm_device.dev, "hdmi_avdd");
|
||||
if (IS_ERR(reg_8038_l23)) {
|
||||
pr_err("could not get reg_8038_l23, rc = %ld\n",
|
||||
PTR_ERR(reg_8038_l23));
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_set_voltage(reg_8038_l23, 1800000, 1800000);
|
||||
if (rc) {
|
||||
pr_err("set_voltage failed for 8921_l23, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
if (on) {
|
||||
rc = regulator_set_optimum_mode(reg_8038_l23, 100000);
|
||||
if (rc < 0) {
|
||||
pr_err("set_optimum_mode l23 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
rc = regulator_enable(reg_8038_l23);
|
||||
if (rc) {
|
||||
pr_err("'%s' regulator enable failed, rc=%d\n",
|
||||
"hdmi_avdd", rc);
|
||||
return rc;
|
||||
}
|
||||
rc = gpio_request(100, "HDMI_DDC_CLK");
|
||||
if (rc) {
|
||||
pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
|
||||
"HDMI_DDC_CLK", 100, rc);
|
||||
goto error1;
|
||||
}
|
||||
rc = gpio_request(101, "HDMI_DDC_DATA");
|
||||
if (rc) {
|
||||
pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
|
||||
"HDMI_DDC_DATA", 101, rc);
|
||||
goto error2;
|
||||
}
|
||||
rc = gpio_request(102, "HDMI_HPD");
|
||||
if (rc) {
|
||||
pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
|
||||
"HDMI_HPD", 102, rc);
|
||||
goto error3;
|
||||
}
|
||||
pr_debug("%s(on): success\n", __func__);
|
||||
} else {
|
||||
gpio_free(100);
|
||||
gpio_free(101);
|
||||
gpio_free(102);
|
||||
|
||||
rc = regulator_disable(reg_8038_l23);
|
||||
if (rc) {
|
||||
pr_err("disable reg_8038_l23 failed, rc=%d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = regulator_set_optimum_mode(reg_8038_l23, 100);
|
||||
if (rc < 0) {
|
||||
pr_err("set_optimum_mode l23 failed, rc=%d\n", rc);
|
||||
return -EINVAL;
|
||||
}
|
||||
pr_debug("%s(off): success\n", __func__);
|
||||
}
|
||||
|
||||
prev_on = on;
|
||||
|
||||
return 0;
|
||||
|
||||
error3:
|
||||
gpio_free(101);
|
||||
error2:
|
||||
gpio_free(100);
|
||||
error1:
|
||||
regulator_disable(reg_8038_l23);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int hdmi_cec_power(int on)
|
||||
{
|
||||
static int prev_on;
|
||||
int rc;
|
||||
|
||||
if (on == prev_on)
|
||||
return 0;
|
||||
|
||||
if (on) {
|
||||
rc = gpio_request(99, "HDMI_CEC_VAR");
|
||||
if (rc) {
|
||||
pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
|
||||
"HDMI_CEC_VAR", 99, rc);
|
||||
goto error;
|
||||
}
|
||||
pr_debug("%s(on): success\n", __func__);
|
||||
} else {
|
||||
gpio_free(99);
|
||||
pr_debug("%s(off): success\n", __func__);
|
||||
}
|
||||
|
||||
prev_on = on;
|
||||
|
||||
return 0;
|
||||
error:
|
||||
return rc;
|
||||
}
|
||||
#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
|
||||
|
||||
void __init msm8930_init_fb(void)
|
||||
{
|
||||
platform_device_register(&msm_fb_device);
|
||||
|
||||
#ifdef CONFIG_FB_MSM_WRITEBACK_MSM_PANEL
|
||||
platform_device_register(&wfd_panel_device);
|
||||
platform_device_register(&wfd_device);
|
||||
#endif
|
||||
|
||||
platform_device_register(&mipi_dsi_novatek_panel_device);
|
||||
|
||||
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
|
||||
platform_device_register(&hdmi_msm_device);
|
||||
#endif
|
||||
|
||||
platform_device_register(&mipi_dsi_toshiba_panel_device);
|
||||
|
||||
msm_fb_register_device("mdp", &mdp_pdata);
|
||||
msm_fb_register_device("mipi_dsi", &mipi_dsi_pdata);
|
||||
#ifdef CONFIG_MSM_BUS_SCALING
|
||||
msm_fb_register_device("dtv", &dtv_pdata);
|
||||
#endif
|
||||
}
|
||||
|
||||
void __init msm8930_allocate_fb_region(void)
|
||||
{
|
||||
void *addr;
|
||||
unsigned long size;
|
||||
|
||||
size = MSM_FB_SIZE;
|
||||
addr = alloc_bootmem_align(size, 0x1000);
|
||||
msm_fb_resources[0].start = __pa(addr);
|
||||
msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
|
||||
pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
|
||||
size, addr, __pa(addr));
|
||||
}
|
||||
711
arch/arm/mach-msm/board-8930-gpiomux.c
Normal file
711
arch/arm/mach-msm/board-8930-gpiomux.c
Normal file
@@ -0,0 +1,711 @@
|
||||
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <mach/gpiomux.h>
|
||||
#include <mach/socinfo.h>
|
||||
#include "devices.h"
|
||||
#include "board-8930.h"
|
||||
|
||||
/* The SPI configurations apply to GSBI 1*/
|
||||
static struct gpiomux_setting spi_active = {
|
||||
.func = GPIOMUX_FUNC_1,
|
||||
.drv = GPIOMUX_DRV_12MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting spi_suspended_config = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting gsbi3_suspended_cfg = {
|
||||
.func = GPIOMUX_FUNC_1,
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_KEEPER,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting gsbi3_active_cfg = {
|
||||
.func = GPIOMUX_FUNC_1,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting gsbi5 = {
|
||||
.func = GPIOMUX_FUNC_1,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting gsbi9 = {
|
||||
.func = GPIOMUX_FUNC_2,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting gsbi10 = {
|
||||
.func = GPIOMUX_FUNC_2,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting gsbi12 = {
|
||||
.func = GPIOMUX_FUNC_1,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting cdc_mclk = {
|
||||
.func = GPIOMUX_FUNC_1,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting audio_auxpcm[] = {
|
||||
/* Suspended state */
|
||||
{
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
/* Active state */
|
||||
{
|
||||
.func = GPIOMUX_FUNC_1,
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpiomux_setting audio_mbhc = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting audio_spkr_boost = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
|
||||
static struct gpiomux_setting gpio_eth_config = {
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct gpiomux_setting slimbus = {
|
||||
.func = GPIOMUX_FUNC_1,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_KEEPER,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting wcnss_5wire_suspend_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting wcnss_5wire_active_cfg = {
|
||||
.func = GPIOMUX_FUNC_1,
|
||||
.drv = GPIOMUX_DRV_6MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting atmel_resout_sus_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_6MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting atmel_resout_act_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_6MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting atmel_ldo_en_sus_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_6MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting atmel_ldo_en_act_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_6MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting atmel_int_act_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting atmel_int_sus_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
};
|
||||
#ifdef MSM8930_PHASE_2
|
||||
static struct gpiomux_setting hsusb_sus_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
.dir = GPIOMUX_OUT_LOW,
|
||||
};
|
||||
static struct msm_gpiomux_config msm8930_hsusb_configs[] = {
|
||||
{
|
||||
.gpio = 63, /* HSUSB_EXTERNAL_5V_LDO_EN */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &hsusb_sus_cfg,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 97, /* HSUSB_5V_EN */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &hsusb_sus_cfg,
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct gpiomux_setting hap_lvl_shft_suspended_config = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting hap_lvl_shft_active_config = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting ap2mdm_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting mdm2ap_status_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting mdm2ap_errfatal_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_16MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting ap2mdm_kpdpwr_n_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting mdp_vsync_suspend_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting mdp_vsync_active_cfg = {
|
||||
.func = GPIOMUX_FUNC_1,
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
|
||||
static struct gpiomux_setting hdmi_suspend_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting hdmi_active_1_cfg = {
|
||||
.func = GPIOMUX_FUNC_1,
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
};
|
||||
|
||||
static struct gpiomux_setting hdmi_active_2_cfg = {
|
||||
.func = GPIOMUX_FUNC_1,
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
|
||||
static struct msm_gpiomux_config msm8960_ethernet_configs[] = {
|
||||
{
|
||||
.gpio = 90,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &gpio_eth_config,
|
||||
}
|
||||
},
|
||||
{
|
||||
.gpio = 89,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &gpio_eth_config,
|
||||
}
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct msm_gpiomux_config msm8960_gsbi_configs[] __initdata = {
|
||||
{
|
||||
.gpio = 6, /* GSBI1 QUP SPI_DATA_MOSI */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &spi_suspended_config,
|
||||
[GPIOMUX_ACTIVE] = &spi_active,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 7, /* GSBI1 QUP SPI_DATA_MISO */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &spi_suspended_config,
|
||||
[GPIOMUX_ACTIVE] = &spi_active,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 8, /* GSBI1 QUP SPI_CS_N */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &spi_suspended_config,
|
||||
[GPIOMUX_ACTIVE] = &spi_active,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 9, /* GSBI1 QUP SPI_CLK */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &spi_suspended_config,
|
||||
[GPIOMUX_ACTIVE] = &spi_active,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 16, /* GSBI3 I2C QUP SDA */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &gsbi3_suspended_cfg,
|
||||
[GPIOMUX_ACTIVE] = &gsbi3_active_cfg,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 17, /* GSBI3 I2C QUP SCL */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &gsbi3_suspended_cfg,
|
||||
[GPIOMUX_ACTIVE] = &gsbi3_active_cfg,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 22, /* GSBI5 UART2 */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &gsbi5,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 23, /* GSBI5 UART2 */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &gsbi5,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 44, /* GSBI12 I2C QUP SDA */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &gsbi12,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 95, /* GSBI9 I2C QUP SDA */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &gsbi9,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 96, /* GSBI12 I2C QUP SCL */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &gsbi9,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 45, /* GSBI12 I2C QUP SCL */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &gsbi12,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 73, /* GSBI10 I2C QUP SDA */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &gsbi10,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 74, /* GSBI10 I2C QUP SCL */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &gsbi10,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config msm8960_slimbus_config[] __initdata = {
|
||||
{
|
||||
.gpio = 60, /* slimbus data */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &slimbus,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 61, /* slimbus clk */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &slimbus,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config msm8960_audio_codec_configs[] __initdata = {
|
||||
{
|
||||
.gpio = 59,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &cdc_mclk,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config msm8960_audio_mbhc_configs[] __initdata = {
|
||||
{
|
||||
.gpio = 37,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &audio_mbhc,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config msm8960_audio_spkr_configs[] __initdata = {
|
||||
{
|
||||
.gpio = 15,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &audio_spkr_boost,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
static struct msm_gpiomux_config msm8960_audio_auxpcm_configs[] __initdata = {
|
||||
{
|
||||
.gpio = 63,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &audio_auxpcm[0],
|
||||
[GPIOMUX_ACTIVE] = &audio_auxpcm[1],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 64,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &audio_auxpcm[0],
|
||||
[GPIOMUX_ACTIVE] = &audio_auxpcm[1],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 65,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &audio_auxpcm[0],
|
||||
[GPIOMUX_ACTIVE] = &audio_auxpcm[1],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 66,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &audio_auxpcm[0],
|
||||
[GPIOMUX_ACTIVE] = &audio_auxpcm[1],
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config wcnss_5wire_interface[] = {
|
||||
{
|
||||
.gpio = 84,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &wcnss_5wire_active_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &wcnss_5wire_suspend_cfg,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 85,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &wcnss_5wire_active_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &wcnss_5wire_suspend_cfg,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 86,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &wcnss_5wire_active_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &wcnss_5wire_suspend_cfg,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 87,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &wcnss_5wire_active_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &wcnss_5wire_suspend_cfg,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 88,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &wcnss_5wire_active_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &wcnss_5wire_suspend_cfg,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config msm8960_atmel_configs[] __initdata = {
|
||||
{ /* TS INTERRUPT */
|
||||
.gpio = 11,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &atmel_int_act_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &atmel_int_sus_cfg,
|
||||
},
|
||||
},
|
||||
{ /* TS LDO ENABLE */
|
||||
.gpio = 50,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &atmel_ldo_en_act_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &atmel_ldo_en_sus_cfg,
|
||||
},
|
||||
},
|
||||
{ /* TS RESOUT */
|
||||
.gpio = 52,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &atmel_resout_act_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &atmel_resout_sus_cfg,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config hap_lvl_shft_config[] __initdata = {
|
||||
{
|
||||
.gpio = 47,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &hap_lvl_shft_suspended_config,
|
||||
[GPIOMUX_ACTIVE] = &hap_lvl_shft_active_config,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config mdm_configs[] __initdata = {
|
||||
/* AP2MDM_STATUS */
|
||||
{
|
||||
.gpio = 94,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &ap2mdm_cfg,
|
||||
}
|
||||
},
|
||||
/* MDM2AP_STATUS */
|
||||
{
|
||||
.gpio = 69,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &mdm2ap_status_cfg,
|
||||
}
|
||||
},
|
||||
/* MDM2AP_ERRFATAL */
|
||||
{
|
||||
.gpio = 70,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &mdm2ap_errfatal_cfg,
|
||||
}
|
||||
},
|
||||
/* AP2MDM_ERRFATAL */
|
||||
{
|
||||
.gpio = 95,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &ap2mdm_cfg,
|
||||
}
|
||||
},
|
||||
/* AP2MDM_KPDPWR_N */
|
||||
{
|
||||
.gpio = 81,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &ap2mdm_kpdpwr_n_cfg,
|
||||
}
|
||||
},
|
||||
/* AP2MDM_PMIC_RESET_N */
|
||||
{
|
||||
.gpio = 80,
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &ap2mdm_kpdpwr_n_cfg,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config msm8960_mdp_vsync_configs[] __initdata = {
|
||||
{
|
||||
.gpio = 0,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &mdp_vsync_active_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &mdp_vsync_suspend_cfg,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
|
||||
static struct msm_gpiomux_config msm8960_hdmi_configs[] __initdata = {
|
||||
{
|
||||
.gpio = 99,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &hdmi_active_1_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &hdmi_suspend_cfg,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 100,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &hdmi_active_1_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &hdmi_suspend_cfg,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 101,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &hdmi_active_1_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &hdmi_suspend_cfg,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 102,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &hdmi_active_2_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &hdmi_suspend_cfg,
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct gpiomux_setting haptics_active_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
};
|
||||
static struct gpiomux_setting haptics_suspend_cfg = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config msm8930_haptics_configs[] __initdata = {
|
||||
{
|
||||
.gpio = 77,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &haptics_active_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &haptics_suspend_cfg,
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 78,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &haptics_active_cfg,
|
||||
[GPIOMUX_SUSPENDED] = &haptics_suspend_cfg,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpiomux_setting sd_det_line = {
|
||||
.func = GPIOMUX_FUNC_GPIO,
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config msm8930_sd_det_config[] __initdata = {
|
||||
{
|
||||
.gpio = 94, /* SD Card Detect Line */
|
||||
.settings = {
|
||||
[GPIOMUX_SUSPENDED] = &sd_det_line,
|
||||
[GPIOMUX_ACTIVE] = &sd_det_line,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
int __init msm8930_init_gpiomux(void)
|
||||
{
|
||||
int rc = msm_gpiomux_init(NR_GPIO_IRQS);
|
||||
if (rc) {
|
||||
pr_err(KERN_ERR "msm_gpiomux_init failed %d\n", rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
|
||||
msm_gpiomux_install(msm8960_ethernet_configs,
|
||||
ARRAY_SIZE(msm8960_ethernet_configs));
|
||||
#endif
|
||||
|
||||
msm_gpiomux_install(msm8960_gsbi_configs,
|
||||
ARRAY_SIZE(msm8960_gsbi_configs));
|
||||
|
||||
msm_gpiomux_install(msm8960_atmel_configs,
|
||||
ARRAY_SIZE(msm8960_atmel_configs));
|
||||
|
||||
msm_gpiomux_install(msm8960_slimbus_config,
|
||||
ARRAY_SIZE(msm8960_slimbus_config));
|
||||
|
||||
msm_gpiomux_install(msm8960_audio_codec_configs,
|
||||
ARRAY_SIZE(msm8960_audio_codec_configs));
|
||||
|
||||
msm_gpiomux_install(msm8960_audio_mbhc_configs,
|
||||
ARRAY_SIZE(msm8960_audio_mbhc_configs));
|
||||
|
||||
msm_gpiomux_install(msm8960_audio_spkr_configs,
|
||||
ARRAY_SIZE(msm8960_audio_spkr_configs));
|
||||
|
||||
msm_gpiomux_install(msm8960_audio_auxpcm_configs,
|
||||
ARRAY_SIZE(msm8960_audio_auxpcm_configs));
|
||||
|
||||
msm_gpiomux_install(wcnss_5wire_interface,
|
||||
ARRAY_SIZE(wcnss_5wire_interface));
|
||||
|
||||
if (machine_is_msm8930_mtp() || machine_is_msm8930_fluid() ||
|
||||
machine_is_msm8930_cdp()) {
|
||||
msm_gpiomux_install(hap_lvl_shft_config,
|
||||
ARRAY_SIZE(hap_lvl_shft_config));
|
||||
#ifdef MSM8930_PHASE_2
|
||||
msm_gpiomux_install(msm8930_hsusb_configs,
|
||||
ARRAY_SIZE(msm8930_hsusb_configs));
|
||||
#endif
|
||||
}
|
||||
|
||||
if (PLATFORM_IS_CHARM25())
|
||||
msm_gpiomux_install(mdm_configs,
|
||||
ARRAY_SIZE(mdm_configs));
|
||||
|
||||
if (machine_is_msm8930_cdp() || machine_is_msm8930_mtp()
|
||||
|| machine_is_msm8930_fluid())
|
||||
msm_gpiomux_install(msm8930_haptics_configs,
|
||||
ARRAY_SIZE(msm8930_haptics_configs));
|
||||
|
||||
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
|
||||
msm_gpiomux_install(msm8960_hdmi_configs,
|
||||
ARRAY_SIZE(msm8960_hdmi_configs));
|
||||
#endif
|
||||
|
||||
msm_gpiomux_install(msm8960_mdp_vsync_configs,
|
||||
ARRAY_SIZE(msm8960_mdp_vsync_configs));
|
||||
|
||||
msm_gpiomux_install(msm8930_sd_det_config,
|
||||
ARRAY_SIZE(msm8930_sd_det_config));
|
||||
|
||||
return 0;
|
||||
}
|
||||
163
arch/arm/mach-msm/board-8930-gpu.c
Normal file
163
arch/arm/mach-msm/board-8930-gpu.c
Normal file
@@ -0,0 +1,163 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/msm_kgsl.h>
|
||||
#include <mach/msm_bus_board.h>
|
||||
#include <mach/board.h>
|
||||
|
||||
#include "devices.h"
|
||||
#include "board-8930.h"
|
||||
|
||||
#ifdef CONFIG_MSM_BUS_SCALING
|
||||
static struct msm_bus_vectors grp3d_init_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_GRAPHICS_3D,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors grp3d_low_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_GRAPHICS_3D,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = KGSL_CONVERT_TO_MBPS(2000),
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors grp3d_nominal_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_GRAPHICS_3D,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = KGSL_CONVERT_TO_MBPS(3200),
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors grp3d_max_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_GRAPHICS_3D,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = KGSL_CONVERT_TO_MBPS(4264),
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_paths grp3d_bus_scale_usecases[] = {
|
||||
{
|
||||
ARRAY_SIZE(grp3d_init_vectors),
|
||||
grp3d_init_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(grp3d_low_vectors),
|
||||
grp3d_low_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(grp3d_nominal_vectors),
|
||||
grp3d_nominal_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(grp3d_max_vectors),
|
||||
grp3d_max_vectors,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_scale_pdata grp3d_bus_scale_pdata = {
|
||||
grp3d_bus_scale_usecases,
|
||||
ARRAY_SIZE(grp3d_bus_scale_usecases),
|
||||
.name = "grp3d",
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct resource kgsl_3d0_resources[] = {
|
||||
{
|
||||
.name = KGSL_3D0_REG_MEMORY,
|
||||
.start = 0x04300000, /* GFX3D address */
|
||||
.end = 0x0431ffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = KGSL_3D0_IRQ,
|
||||
.start = GFX3D_IRQ,
|
||||
.end = GFX3D_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct kgsl_iommu_ctx kgsl_3d0_iommu0_ctxs[] = {
|
||||
{ "gfx3d_user", 0 },
|
||||
{ "gfx3d_priv", 1 },
|
||||
};
|
||||
|
||||
static struct kgsl_device_iommu_data kgsl_3d0_iommu_data[] = {
|
||||
{
|
||||
.iommu_ctxs = kgsl_3d0_iommu0_ctxs,
|
||||
.iommu_ctx_count = ARRAY_SIZE(kgsl_3d0_iommu0_ctxs),
|
||||
.physstart = 0x07C00000,
|
||||
.physend = 0x07C00000 + SZ_1M - 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
|
||||
.pwrlevel = {
|
||||
{
|
||||
.gpu_freq = 400000000,
|
||||
.bus_freq = 3,
|
||||
.io_fraction = 0,
|
||||
},
|
||||
{
|
||||
.gpu_freq = 320000000,
|
||||
.bus_freq = 2,
|
||||
.io_fraction = 33,
|
||||
},
|
||||
{
|
||||
.gpu_freq = 192000000,
|
||||
.bus_freq = 1,
|
||||
.io_fraction = 100,
|
||||
},
|
||||
{
|
||||
.gpu_freq = 27000000,
|
||||
.bus_freq = 0,
|
||||
},
|
||||
},
|
||||
.init_level = 0,
|
||||
.num_levels = 4,
|
||||
.set_grp_async = NULL,
|
||||
.idle_timeout = HZ/12,
|
||||
.nap_allowed = true,
|
||||
.clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM_IFACE,
|
||||
#ifdef CONFIG_MSM_BUS_SCALING
|
||||
.bus_scale_table = &grp3d_bus_scale_pdata,
|
||||
#endif
|
||||
.iommu_data = kgsl_3d0_iommu_data,
|
||||
.iommu_count = ARRAY_SIZE(kgsl_3d0_iommu_data),
|
||||
};
|
||||
|
||||
static struct platform_device device_kgsl_3d0 = {
|
||||
.name = "kgsl-3d0",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(kgsl_3d0_resources),
|
||||
.resource = kgsl_3d0_resources,
|
||||
.dev = {
|
||||
.platform_data = &kgsl_3d0_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
void __init msm8930_init_gpu(void)
|
||||
{
|
||||
platform_device_register(&device_kgsl_3d0);
|
||||
}
|
||||
380
arch/arm/mach-msm/board-8930-pmic.c
Normal file
380
arch/arm/mach-msm/board-8930-pmic.c
Normal file
@@ -0,0 +1,380 @@
|
||||
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mfd/pm8xxx/pm8038.h>
|
||||
#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
|
||||
#include <linux/msm_ssbi.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <mach/msm_bus_board.h>
|
||||
#include <mach/restart.h>
|
||||
#include "devices.h"
|
||||
#include "board-8930.h"
|
||||
|
||||
struct pm8xxx_gpio_init {
|
||||
unsigned gpio;
|
||||
struct pm_gpio config;
|
||||
};
|
||||
|
||||
struct pm8xxx_mpp_init {
|
||||
unsigned mpp;
|
||||
struct pm8xxx_mpp_config_data config;
|
||||
};
|
||||
|
||||
#define PM8XXX_GPIO_INIT(_gpio, _dir, _buf, _val, _pull, _vin, _out_strength, \
|
||||
_func, _inv, _disable) \
|
||||
{ \
|
||||
.gpio = PM8038_GPIO_PM_TO_SYS(_gpio), \
|
||||
.config = { \
|
||||
.direction = _dir, \
|
||||
.output_buffer = _buf, \
|
||||
.output_value = _val, \
|
||||
.pull = _pull, \
|
||||
.vin_sel = _vin, \
|
||||
.out_strength = _out_strength, \
|
||||
.function = _func, \
|
||||
.inv_int_pol = _inv, \
|
||||
.disable_pin = _disable, \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PM8XXX_MPP_INIT(_mpp, _type, _level, _control) \
|
||||
{ \
|
||||
.mpp = PM8038_MPP_PM_TO_SYS(_mpp), \
|
||||
.config = { \
|
||||
.type = PM8XXX_MPP_TYPE_##_type, \
|
||||
.level = _level, \
|
||||
.control = PM8XXX_MPP_##_control, \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PM8XXX_GPIO_DISABLE(_gpio) \
|
||||
PM8XXX_GPIO_INIT(_gpio, PM_GPIO_DIR_IN, 0, 0, 0, PM8038_GPIO_VIN_L11, \
|
||||
0, 0, 0, 1)
|
||||
|
||||
#define PM8XXX_GPIO_OUTPUT(_gpio, _val) \
|
||||
PM8XXX_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT, PM_GPIO_OUT_BUF_CMOS, _val, \
|
||||
PM_GPIO_PULL_NO, PM8038_GPIO_VIN_L11, \
|
||||
PM_GPIO_STRENGTH_HIGH, \
|
||||
PM_GPIO_FUNC_NORMAL, 0, 0)
|
||||
|
||||
#define PM8XXX_GPIO_INPUT(_gpio, _pull) \
|
||||
PM8XXX_GPIO_INIT(_gpio, PM_GPIO_DIR_IN, PM_GPIO_OUT_BUF_CMOS, 0, \
|
||||
_pull, PM8038_GPIO_VIN_L11, \
|
||||
PM_GPIO_STRENGTH_NO, \
|
||||
PM_GPIO_FUNC_NORMAL, 0, 0)
|
||||
|
||||
#define PM8XXX_GPIO_OUTPUT_FUNC(_gpio, _val, _func) \
|
||||
PM8XXX_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT, PM_GPIO_OUT_BUF_CMOS, _val, \
|
||||
PM_GPIO_PULL_NO, PM8038_GPIO_VIN_L11, \
|
||||
PM_GPIO_STRENGTH_HIGH, \
|
||||
_func, 0, 0)
|
||||
|
||||
#define PM8XXX_GPIO_OUTPUT_VIN(_gpio, _val, _vin) \
|
||||
PM8XXX_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT, PM_GPIO_OUT_BUF_CMOS, _val, \
|
||||
PM_GPIO_PULL_NO, _vin, \
|
||||
PM_GPIO_STRENGTH_HIGH, \
|
||||
PM_GPIO_FUNC_NORMAL, 0, 0)
|
||||
|
||||
/* Initial pm8038 GPIO configurations */
|
||||
static struct pm8xxx_gpio_init pm8038_gpios[] __initdata = {
|
||||
/* keys GPIOs */
|
||||
PM8XXX_GPIO_INPUT(3, PM_GPIO_PULL_UP_30),
|
||||
PM8XXX_GPIO_INPUT(8, PM_GPIO_PULL_UP_30),
|
||||
PM8XXX_GPIO_INPUT(10, PM_GPIO_PULL_UP_30),
|
||||
PM8XXX_GPIO_INPUT(11, PM_GPIO_PULL_UP_30),
|
||||
/* haptics gpio */
|
||||
PM8XXX_GPIO_OUTPUT_FUNC(7, 0, PM_GPIO_FUNC_1),
|
||||
};
|
||||
|
||||
/* Initial pm8038 MPP configurations */
|
||||
static struct pm8xxx_mpp_init pm8038_mpps[] __initdata = {
|
||||
/* External 5V regulator enable; shared by HDMI and USB_OTG switches. */
|
||||
PM8XXX_MPP_INIT(3, D_INPUT, PM8038_MPP_DIG_LEVEL_VPH, DIN_TO_INT),
|
||||
};
|
||||
|
||||
void __init msm8930_pm8038_gpio_mpp_init(void)
|
||||
{
|
||||
int i, rc;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pm8038_gpios); i++) {
|
||||
rc = pm8xxx_gpio_config(pm8038_gpios[i].gpio,
|
||||
&pm8038_gpios[i].config);
|
||||
if (rc) {
|
||||
pr_err("%s: pm8xxx_gpio_config: rc=%d\n", __func__, rc);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Initial MPP configuration. */
|
||||
for (i = 0; i < ARRAY_SIZE(pm8038_mpps); i++) {
|
||||
rc = pm8xxx_mpp_config(pm8038_mpps[i].mpp,
|
||||
&pm8038_mpps[i].config);
|
||||
if (rc) {
|
||||
pr_err("%s: pm8xxx_mpp_config: rc=%d\n", __func__, rc);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static struct pm8xxx_adc_amux pm8xxx_adc_channels_data[] = {
|
||||
{"vcoin", CHANNEL_VCOIN, CHAN_PATH_SCALING2, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"vbat", CHANNEL_VBAT, CHAN_PATH_SCALING2, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"dcin", CHANNEL_DCIN, CHAN_PATH_SCALING4, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"ichg", CHANNEL_ICHG, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"vph_pwr", CHANNEL_VPH_PWR, CHAN_PATH_SCALING2, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"ibat", CHANNEL_IBAT, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"batt_therm", CHANNEL_BATT_THERM, CHAN_PATH_SCALING1, AMUX_RSV2,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_BATT_THERM},
|
||||
{"batt_id", CHANNEL_BATT_ID, CHAN_PATH_SCALING1, AMUX_RSV2,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"usbin", CHANNEL_USBIN, CHAN_PATH_SCALING3, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"pmic_therm", CHANNEL_DIE_TEMP, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_PMIC_THERM},
|
||||
{"625mv", CHANNEL_625MV, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"125v", CHANNEL_125V, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"chg_temp", CHANNEL_CHG_TEMP, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"pa_therm1", ADC_MPP_1_AMUX4, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_PA_THERM},
|
||||
{"xo_therm", CHANNEL_MUXOFF, CHAN_PATH_SCALING1, AMUX_RSV0,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_XOTHERM},
|
||||
{"pa_therm0", ADC_MPP_1_AMUX3, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_PA_THERM},
|
||||
};
|
||||
|
||||
static struct pm8xxx_adc_properties pm8xxx_adc_data = {
|
||||
.adc_vdd_reference = 1800, /* milli-voltage for this adc */
|
||||
.bitresolution = 15,
|
||||
.bipolar = 0,
|
||||
};
|
||||
|
||||
static struct pm8xxx_adc_platform_data pm8xxx_adc_pdata = {
|
||||
.adc_channel = pm8xxx_adc_channels_data,
|
||||
.adc_num_board_channel = ARRAY_SIZE(pm8xxx_adc_channels_data),
|
||||
.adc_prop = &pm8xxx_adc_data,
|
||||
.adc_mpp_base = PM8038_MPP_PM_TO_SYS(1),
|
||||
};
|
||||
|
||||
static struct pm8xxx_irq_platform_data pm8xxx_irq_pdata __devinitdata = {
|
||||
.irq_base = PM8038_IRQ_BASE,
|
||||
.devirq = MSM_GPIO_TO_INT(104),
|
||||
.irq_trigger_flag = IRQF_TRIGGER_LOW,
|
||||
};
|
||||
|
||||
static struct pm8xxx_gpio_platform_data pm8xxx_gpio_pdata __devinitdata = {
|
||||
.gpio_base = PM8038_GPIO_PM_TO_SYS(1),
|
||||
};
|
||||
|
||||
static struct pm8xxx_mpp_platform_data pm8xxx_mpp_pdata __devinitdata = {
|
||||
.mpp_base = PM8038_MPP_PM_TO_SYS(1),
|
||||
};
|
||||
|
||||
static struct pm8xxx_rtc_platform_data pm8xxx_rtc_pdata __devinitdata = {
|
||||
.rtc_write_enable = false,
|
||||
.rtc_alarm_powerup = false,
|
||||
};
|
||||
|
||||
static struct pm8xxx_pwrkey_platform_data pm8xxx_pwrkey_pdata = {
|
||||
.pull_up = 1,
|
||||
.kpd_trigger_delay_us = 15625,
|
||||
.wakeup = 1,
|
||||
};
|
||||
|
||||
static int pm8921_therm_mitigation[] = {
|
||||
1100,
|
||||
700,
|
||||
600,
|
||||
325,
|
||||
};
|
||||
|
||||
#define MAX_VOLTAGE_MV 4200
|
||||
static struct pm8921_charger_platform_data pm8921_chg_pdata __devinitdata = {
|
||||
.safety_time = 180,
|
||||
.update_time = 60000,
|
||||
.max_voltage = MAX_VOLTAGE_MV,
|
||||
.min_voltage = 3200,
|
||||
.resume_voltage_delta = 100,
|
||||
.term_current = 100,
|
||||
.cool_temp = 10,
|
||||
.warm_temp = 40,
|
||||
.temp_check_period = 1,
|
||||
.max_bat_chg_current = 1100,
|
||||
.cool_bat_chg_current = 350,
|
||||
.warm_bat_chg_current = 350,
|
||||
.cool_bat_voltage = 4100,
|
||||
.warm_bat_voltage = 4100,
|
||||
.thermal_mitigation = pm8921_therm_mitigation,
|
||||
.thermal_levels = ARRAY_SIZE(pm8921_therm_mitigation),
|
||||
.led_src_config = LED_SRC_VPH_PWR,
|
||||
};
|
||||
|
||||
#define PM8038_WLED_MAX_CURRENT 25
|
||||
#define PM8XXX_LED_PWM_PERIOD 1000
|
||||
#define PM8XXX_LED_PWM_DUTY_MS 20
|
||||
#define PM8038_RGB_LED_MAX_CURRENT 12
|
||||
|
||||
static struct led_info pm8038_led_info[] = {
|
||||
[0] = {
|
||||
.name = "wled",
|
||||
.default_trigger = "bkl_trigger",
|
||||
},
|
||||
[1] = {
|
||||
.name = "led:rgb_red",
|
||||
.default_trigger = "battery-charging",
|
||||
},
|
||||
[2] = {
|
||||
.name = "led:rgb_green",
|
||||
},
|
||||
[3] = {
|
||||
.name = "led:rgb_blue",
|
||||
},
|
||||
};
|
||||
|
||||
static struct led_platform_data pm8038_led_core_pdata = {
|
||||
.num_leds = ARRAY_SIZE(pm8038_led_info),
|
||||
.leds = pm8038_led_info,
|
||||
};
|
||||
|
||||
static struct wled_config_data wled_cfg = {
|
||||
.dig_mod_gen_en = true,
|
||||
.cs_out_en = true,
|
||||
.ctrl_delay_us = 0,
|
||||
.op_fdbck = true,
|
||||
.ovp_val = WLED_OVP_32V,
|
||||
.boost_curr_lim = WLED_CURR_LIMIT_525mA,
|
||||
.num_strings = 1,
|
||||
};
|
||||
|
||||
static int pm8038_led0_pwm_duty_pcts[56] = {
|
||||
1, 4, 8, 12, 16, 20, 24, 28, 32, 36,
|
||||
40, 44, 46, 52, 56, 60, 64, 68, 72, 76,
|
||||
80, 84, 88, 92, 96, 100, 100, 100, 98, 95,
|
||||
92, 88, 84, 82, 78, 74, 70, 66, 62, 58,
|
||||
58, 54, 50, 48, 42, 38, 34, 30, 26, 22,
|
||||
14, 10, 6, 4, 1
|
||||
};
|
||||
|
||||
static struct pm8xxx_pwm_duty_cycles pm8038_led0_pwm_duty_cycles = {
|
||||
.duty_pcts = (int *)&pm8038_led0_pwm_duty_pcts,
|
||||
.num_duty_pcts = ARRAY_SIZE(pm8038_led0_pwm_duty_pcts),
|
||||
.duty_ms = PM8XXX_LED_PWM_DUTY_MS,
|
||||
.start_idx = 0,
|
||||
};
|
||||
|
||||
static struct pm8xxx_led_config pm8038_led_configs[] = {
|
||||
[0] = {
|
||||
.id = PM8XXX_ID_WLED,
|
||||
.mode = PM8XXX_LED_MODE_MANUAL,
|
||||
.max_current = PM8038_WLED_MAX_CURRENT,
|
||||
.default_state = 0,
|
||||
.wled_cfg = &wled_cfg,
|
||||
},
|
||||
[1] = {
|
||||
.id = PM8XXX_ID_RGB_LED_RED,
|
||||
.mode = PM8XXX_LED_MODE_PWM1,
|
||||
.max_current = PM8038_RGB_LED_MAX_CURRENT,
|
||||
.pwm_channel = 5,
|
||||
.pwm_period_us = PM8XXX_LED_PWM_PERIOD,
|
||||
.pwm_duty_cycles = &pm8038_led0_pwm_duty_cycles,
|
||||
},
|
||||
[2] = {
|
||||
.id = PM8XXX_ID_RGB_LED_GREEN,
|
||||
.mode = PM8XXX_LED_MODE_PWM1,
|
||||
.max_current = PM8038_RGB_LED_MAX_CURRENT,
|
||||
.pwm_channel = 4,
|
||||
.pwm_period_us = PM8XXX_LED_PWM_PERIOD,
|
||||
.pwm_duty_cycles = &pm8038_led0_pwm_duty_cycles,
|
||||
},
|
||||
[3] = {
|
||||
.id = PM8XXX_ID_RGB_LED_BLUE,
|
||||
.mode = PM8XXX_LED_MODE_PWM1,
|
||||
.max_current = PM8038_RGB_LED_MAX_CURRENT,
|
||||
.pwm_channel = 3,
|
||||
.pwm_period_us = PM8XXX_LED_PWM_PERIOD,
|
||||
.pwm_duty_cycles = &pm8038_led0_pwm_duty_cycles,
|
||||
},
|
||||
};
|
||||
|
||||
static struct pm8xxx_led_platform_data pm8xxx_leds_pdata = {
|
||||
.led_core = &pm8038_led_core_pdata,
|
||||
.configs = pm8038_led_configs,
|
||||
.num_configs = ARRAY_SIZE(pm8038_led_configs),
|
||||
};
|
||||
|
||||
static struct pm8xxx_ccadc_platform_data pm8xxx_ccadc_pdata = {
|
||||
.r_sense = 10,
|
||||
};
|
||||
|
||||
static struct pm8xxx_misc_platform_data pm8xxx_misc_pdata = {
|
||||
.priority = 0,
|
||||
};
|
||||
|
||||
static struct pm8xxx_spk_platform_data pm8xxx_spk_pdata = {
|
||||
.spk_add_enable = false,
|
||||
};
|
||||
|
||||
static struct pm8921_bms_platform_data pm8921_bms_pdata __devinitdata = {
|
||||
.battery_type = BATT_UNKNOWN,
|
||||
.r_sense = 10,
|
||||
.i_test = 2500,
|
||||
.v_failure = 3000,
|
||||
.calib_delay_ms = 600000,
|
||||
.max_voltage_uv = MAX_VOLTAGE_MV * 1000,
|
||||
};
|
||||
|
||||
static struct pm8038_platform_data pm8038_platform_data __devinitdata = {
|
||||
.irq_pdata = &pm8xxx_irq_pdata,
|
||||
.gpio_pdata = &pm8xxx_gpio_pdata,
|
||||
.mpp_pdata = &pm8xxx_mpp_pdata,
|
||||
.rtc_pdata = &pm8xxx_rtc_pdata,
|
||||
.pwrkey_pdata = &pm8xxx_pwrkey_pdata,
|
||||
.misc_pdata = &pm8xxx_misc_pdata,
|
||||
.regulator_pdatas = msm8930_pm8038_regulator_pdata,
|
||||
.charger_pdata = &pm8921_chg_pdata,
|
||||
.bms_pdata = &pm8921_bms_pdata,
|
||||
.adc_pdata = &pm8xxx_adc_pdata,
|
||||
.leds_pdata = &pm8xxx_leds_pdata,
|
||||
.ccadc_pdata = &pm8xxx_ccadc_pdata,
|
||||
.spk_pdata = &pm8xxx_spk_pdata,
|
||||
};
|
||||
|
||||
static struct msm_ssbi_platform_data msm8930_ssbi_pm8038_pdata __devinitdata = {
|
||||
.controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
|
||||
.slave = {
|
||||
.name = "pm8038-core",
|
||||
.platform_data = &pm8038_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
void __init msm8930_init_pmic(void)
|
||||
{
|
||||
pmic_reset_irq = PM8038_IRQ_BASE + PM8038_RESOUT_IRQ;
|
||||
msm8960_device_ssbi_pmic.dev.platform_data =
|
||||
&msm8930_ssbi_pm8038_pdata;
|
||||
pm8038_platform_data.num_regulators
|
||||
= msm8930_pm8038_regulator_pdata_len;
|
||||
if (machine_is_apq8064_mtp())
|
||||
pm8921_bms_pdata.battery_type = BATT_PALLADIUM;
|
||||
else if (machine_is_apq8064_liquid())
|
||||
pm8921_bms_pdata.battery_type = BATT_DESAY;
|
||||
}
|
||||
513
arch/arm/mach-msm/board-8930-regulator.c
Normal file
513
arch/arm/mach-msm/board-8930-regulator.c
Normal file
@@ -0,0 +1,513 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/regulator/pm8xxx-regulator.h>
|
||||
|
||||
#include "board-8930.h"
|
||||
|
||||
#define VREG_CONSUMERS(_id) \
|
||||
static struct regulator_consumer_supply vreg_consumers_##_id[]
|
||||
|
||||
/*
|
||||
* Consumer specific regulator names:
|
||||
* regulator name consumer dev_name
|
||||
*/
|
||||
VREG_CONSUMERS(L1) = {
|
||||
REGULATOR_SUPPLY("8038_l1", NULL),
|
||||
REGULATOR_SUPPLY("iris_vddrfa", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(L2) = {
|
||||
REGULATOR_SUPPLY("8038_l2", NULL),
|
||||
REGULATOR_SUPPLY("iris_vdddig", "wcnss_wlan.0"),
|
||||
REGULATOR_SUPPLY("dsi_vdda", "mipi_dsi.1"),
|
||||
REGULATOR_SUPPLY("mipi_csi_vdd", "msm_csid.0"),
|
||||
REGULATOR_SUPPLY("mipi_csi_vdd", "msm_csid.1"),
|
||||
REGULATOR_SUPPLY("mipi_csi_vdd", "msm_csid.2"),
|
||||
};
|
||||
VREG_CONSUMERS(L3) = {
|
||||
REGULATOR_SUPPLY("8038_l3", NULL),
|
||||
REGULATOR_SUPPLY("HSUSB_3p3", "msm_otg"),
|
||||
};
|
||||
VREG_CONSUMERS(L4) = {
|
||||
REGULATOR_SUPPLY("8038_l4", NULL),
|
||||
REGULATOR_SUPPLY("HSUSB_1p8", "msm_otg"),
|
||||
REGULATOR_SUPPLY("iris_vddxo", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(L5) = {
|
||||
REGULATOR_SUPPLY("8038_l5", NULL),
|
||||
REGULATOR_SUPPLY("sdc_vdd", "msm_sdcc.1"),
|
||||
};
|
||||
VREG_CONSUMERS(L6) = {
|
||||
REGULATOR_SUPPLY("8038_l6", NULL),
|
||||
REGULATOR_SUPPLY("sdc_vdd", "msm_sdcc.3"),
|
||||
};
|
||||
VREG_CONSUMERS(L7) = {
|
||||
REGULATOR_SUPPLY("8038_l7", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L8) = {
|
||||
REGULATOR_SUPPLY("8038_l8", NULL),
|
||||
REGULATOR_SUPPLY("dsi_vdc", "mipi_dsi.1"),
|
||||
};
|
||||
VREG_CONSUMERS(L9) = {
|
||||
REGULATOR_SUPPLY("8038_l9", NULL),
|
||||
REGULATOR_SUPPLY("vdd_ana", "3-004a"),
|
||||
REGULATOR_SUPPLY("vdd", "3-0024"),
|
||||
REGULATOR_SUPPLY("cam_vana", "4-001a"),
|
||||
REGULATOR_SUPPLY("cam_vana", "4-006c"),
|
||||
REGULATOR_SUPPLY("cam_vana", "4-0048"),
|
||||
REGULATOR_SUPPLY("cam_vaf", "4-001a"),
|
||||
REGULATOR_SUPPLY("cam_vaf", "4-006c"),
|
||||
REGULATOR_SUPPLY("cam_vaf", "4-0048"),
|
||||
REGULATOR_SUPPLY("cam_vana", "4-0020"),
|
||||
REGULATOR_SUPPLY("cam_vaf", "4-0020"),
|
||||
};
|
||||
VREG_CONSUMERS(L10) = {
|
||||
REGULATOR_SUPPLY("8038_l10", NULL),
|
||||
REGULATOR_SUPPLY("iris_vddpa", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(L11) = {
|
||||
REGULATOR_SUPPLY("8038_l11", NULL),
|
||||
REGULATOR_SUPPLY("vdd_dig", "3-004a"),
|
||||
REGULATOR_SUPPLY("iris_vddio", "wcnss_wlan.0"),
|
||||
REGULATOR_SUPPLY("riva_vddpx", "wcnss_wlan.0"),
|
||||
REGULATOR_SUPPLY("sdc_vdd_io", "msm_sdcc.1"),
|
||||
REGULATOR_SUPPLY("VDDIO_CDC", "sitar-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_TX", "sitar-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_RX", "sitar-slim"),
|
||||
REGULATOR_SUPPLY("VDDIO_CDC", "sitar1p1-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_TX", "sitar1p1-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_RX", "sitar1p1-slim"),
|
||||
REGULATOR_SUPPLY("vddp", "0-0048"),
|
||||
};
|
||||
VREG_CONSUMERS(L12) = {
|
||||
REGULATOR_SUPPLY("8038_l12", NULL),
|
||||
REGULATOR_SUPPLY("cam_vdig", "4-001a"),
|
||||
REGULATOR_SUPPLY("cam_vdig", "4-006c"),
|
||||
REGULATOR_SUPPLY("cam_vdig", "4-0048"),
|
||||
REGULATOR_SUPPLY("cam_vdig", "4-0020"),
|
||||
};
|
||||
VREG_CONSUMERS(L14) = {
|
||||
REGULATOR_SUPPLY("8038_l14", NULL),
|
||||
REGULATOR_SUPPLY("pa_therm", "pm8xxx-adc"),
|
||||
};
|
||||
VREG_CONSUMERS(L15) = {
|
||||
REGULATOR_SUPPLY("8038_l15", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L16) = {
|
||||
REGULATOR_SUPPLY("8038_l16", NULL),
|
||||
REGULATOR_SUPPLY("core_vdd", "pil_qdsp6v4.2"),
|
||||
};
|
||||
VREG_CONSUMERS(L17) = {
|
||||
REGULATOR_SUPPLY("8038_l17", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L18) = {
|
||||
REGULATOR_SUPPLY("8038_l18", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L19) = {
|
||||
REGULATOR_SUPPLY("8038_l19", NULL),
|
||||
REGULATOR_SUPPLY("core_vdd", "pil_qdsp6v4.1"),
|
||||
};
|
||||
VREG_CONSUMERS(L20) = {
|
||||
REGULATOR_SUPPLY("8038_l20", NULL),
|
||||
REGULATOR_SUPPLY("VDDD_CDC_D", "sitar-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_A_1P2V", "sitar-slim"),
|
||||
REGULATOR_SUPPLY("VDDD_CDC_D", "sitar1p1-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_A_1P2V", "sitar1p1-slim"),
|
||||
};
|
||||
VREG_CONSUMERS(L21) = {
|
||||
REGULATOR_SUPPLY("8038_l21", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L22) = {
|
||||
REGULATOR_SUPPLY("8038_l22", NULL),
|
||||
REGULATOR_SUPPLY("sdc_vdd_io", "msm_sdcc.3"),
|
||||
};
|
||||
VREG_CONSUMERS(L23) = {
|
||||
REGULATOR_SUPPLY("8038_l23", NULL),
|
||||
REGULATOR_SUPPLY("dsi_vddio", "mipi_dsi.1"),
|
||||
REGULATOR_SUPPLY("hdmi_avdd", "hdmi_msm.0"),
|
||||
REGULATOR_SUPPLY("hdmi_vcc", "hdmi_msm.0"),
|
||||
REGULATOR_SUPPLY("pll_vdd", "pil_riva"),
|
||||
REGULATOR_SUPPLY("pll_vdd", "pil_qdsp6v4.1"),
|
||||
REGULATOR_SUPPLY("pll_vdd", "pil_qdsp6v4.2"),
|
||||
};
|
||||
VREG_CONSUMERS(L24) = {
|
||||
REGULATOR_SUPPLY("8038_l24", NULL),
|
||||
REGULATOR_SUPPLY("riva_vddmx", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(L26) = {
|
||||
REGULATOR_SUPPLY("8038_l26", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L27) = {
|
||||
REGULATOR_SUPPLY("8038_l27", NULL),
|
||||
REGULATOR_SUPPLY("core_vdd", "pil_qdsp6v4.0"),
|
||||
};
|
||||
VREG_CONSUMERS(S1) = {
|
||||
REGULATOR_SUPPLY("8038_s1", NULL),
|
||||
REGULATOR_SUPPLY("riva_vddcx", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(S2) = {
|
||||
REGULATOR_SUPPLY("8038_s2", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(S3) = {
|
||||
REGULATOR_SUPPLY("8038_s3", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(S4) = {
|
||||
REGULATOR_SUPPLY("8038_s4", NULL),
|
||||
REGULATOR_SUPPLY("CDC_VDD_CP", "sitar-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDD_CP", "sitar1p1-slim"),
|
||||
};
|
||||
VREG_CONSUMERS(S5) = {
|
||||
REGULATOR_SUPPLY("8038_s5", NULL),
|
||||
REGULATOR_SUPPLY("krait0", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(S6) = {
|
||||
REGULATOR_SUPPLY("8038_s6", NULL),
|
||||
REGULATOR_SUPPLY("krait1", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(LVS1) = {
|
||||
REGULATOR_SUPPLY("8038_lvs1", NULL),
|
||||
REGULATOR_SUPPLY("cam_vio", "4-001a"),
|
||||
REGULATOR_SUPPLY("cam_vio", "4-006c"),
|
||||
REGULATOR_SUPPLY("cam_vio", "4-0048"),
|
||||
REGULATOR_SUPPLY("cam_vio", "4-0020"),
|
||||
};
|
||||
VREG_CONSUMERS(LVS2) = {
|
||||
REGULATOR_SUPPLY("8038_lvs2", NULL),
|
||||
REGULATOR_SUPPLY("vcc_i2c", "3-004a"),
|
||||
REGULATOR_SUPPLY("vcc_i2c", "3-0024"),
|
||||
REGULATOR_SUPPLY("vcc_i2c", "0-0048"),
|
||||
};
|
||||
VREG_CONSUMERS(EXT_5V) = {
|
||||
REGULATOR_SUPPLY("ext_5v", NULL),
|
||||
REGULATOR_SUPPLY("hdmi_mvs", "hdmi_msm.0"),
|
||||
};
|
||||
VREG_CONSUMERS(EXT_OTG_SW) = {
|
||||
REGULATOR_SUPPLY("ext_otg_sw", NULL),
|
||||
REGULATOR_SUPPLY("vbus_otg", "msm_otg"),
|
||||
};
|
||||
VREG_CONSUMERS(VDD_DIG_CORNER) = {
|
||||
REGULATOR_SUPPLY("vdd_dig_corner", NULL),
|
||||
REGULATOR_SUPPLY("hsusb_vdd_dig", "msm_otg"),
|
||||
};
|
||||
|
||||
#define PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, _modes, _ops, \
|
||||
_apply_uV, _pull_down, _always_on, _supply_regulator, \
|
||||
_system_uA, _enable_time, _reg_id) \
|
||||
{ \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_modes_mask = _modes, \
|
||||
.valid_ops_mask = _ops, \
|
||||
.min_uV = _min_uV, \
|
||||
.max_uV = _max_uV, \
|
||||
.input_uV = _max_uV, \
|
||||
.apply_uV = _apply_uV, \
|
||||
.always_on = _always_on, \
|
||||
.name = _name, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id), \
|
||||
.consumer_supplies = vreg_consumers_##_id, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.id = _reg_id, \
|
||||
.pull_down_enable = _pull_down, \
|
||||
.system_uA = _system_uA, \
|
||||
.enable_time = _enable_time, \
|
||||
}
|
||||
|
||||
#define PM8XXX_LDO(_id, _name, _always_on, _pull_down, _min_uV, _max_uV, \
|
||||
_enable_time, _supply_regulator, _system_uA, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE | \
|
||||
REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
|
||||
REGULATOR_CHANGE_DRMS, 0, _pull_down, _always_on, \
|
||||
_supply_regulator, _system_uA, _enable_time, _reg_id)
|
||||
|
||||
#define PM8XXX_NLDO1200(_id, _name, _always_on, _pull_down, _min_uV, \
|
||||
_max_uV, _enable_time, _supply_regulator, _system_uA, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE | \
|
||||
REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
|
||||
REGULATOR_CHANGE_DRMS, 0, _pull_down, _always_on, \
|
||||
_supply_regulator, _system_uA, _enable_time, _reg_id)
|
||||
|
||||
#define PM8XXX_SMPS(_id, _name, _always_on, _pull_down, _min_uV, _max_uV, \
|
||||
_enable_time, _supply_regulator, _system_uA, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE | \
|
||||
REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
|
||||
REGULATOR_CHANGE_DRMS, 0, _pull_down, _always_on, \
|
||||
_supply_regulator, _system_uA, _enable_time, _reg_id)
|
||||
|
||||
#define PM8XXX_FTSMPS(_id, _name, _always_on, _pull_down, _min_uV, _max_uV, \
|
||||
_enable_time, _supply_regulator, _system_uA, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL, \
|
||||
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS \
|
||||
| REGULATOR_CHANGE_MODE, 0, _pull_down, _always_on, \
|
||||
_supply_regulator, _system_uA, _enable_time, _reg_id)
|
||||
|
||||
#define PM8XXX_VS(_id, _name, _always_on, _pull_down, _enable_time, \
|
||||
_supply_regulator, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, \
|
||||
_pull_down, _always_on, _supply_regulator, 0, _enable_time, \
|
||||
_reg_id)
|
||||
|
||||
#define PM8XXX_VS300(_id, _name, _always_on, _pull_down, _enable_time, \
|
||||
_supply_regulator, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, \
|
||||
_pull_down, _always_on, _supply_regulator, 0, _enable_time, \
|
||||
_reg_id)
|
||||
|
||||
#define PM8XXX_NCP(_id, _name, _always_on, _min_uV, _max_uV, _enable_time, \
|
||||
_supply_regulator, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, 0, \
|
||||
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, 0, 0, \
|
||||
_always_on, _supply_regulator, 0, _enable_time, _reg_id)
|
||||
|
||||
/* Pin control initialization */
|
||||
#define PM8XXX_PC(_id, _name, _always_on, _pin_fn, _pin_ctrl, \
|
||||
_supply_regulator, _reg_id) \
|
||||
{ \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS, \
|
||||
.always_on = _always_on, \
|
||||
.name = _name, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id##_PC), \
|
||||
.consumer_supplies = vreg_consumers_##_id##_PC, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.id = _reg_id, \
|
||||
.pin_fn = PM8XXX_VREG_PIN_FN_##_pin_fn, \
|
||||
.pin_ctrl = _pin_ctrl, \
|
||||
}
|
||||
|
||||
#define RPM_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, _default_uV, \
|
||||
_peak_uA, _avg_uA, _pull_down, _pin_ctrl, _freq, _pin_fn, \
|
||||
_force_mode, _sleep_set_force_mode, _power_mode, _state, \
|
||||
_sleep_selectable, _always_on, _supply_regulator, _system_uA) \
|
||||
{ \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_modes_mask = _modes, \
|
||||
.valid_ops_mask = _ops, \
|
||||
.min_uV = _min_uV, \
|
||||
.max_uV = _max_uV, \
|
||||
.input_uV = _min_uV, \
|
||||
.apply_uV = _apply_uV, \
|
||||
.always_on = _always_on, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id), \
|
||||
.consumer_supplies = vreg_consumers_##_id, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.id = RPM_VREG_ID_PM8038_##_id, \
|
||||
.default_uV = _default_uV, \
|
||||
.peak_uA = _peak_uA, \
|
||||
.avg_uA = _avg_uA, \
|
||||
.pull_down_enable = _pull_down, \
|
||||
.pin_ctrl = _pin_ctrl, \
|
||||
.freq = RPM_VREG_FREQ_##_freq, \
|
||||
.pin_fn = _pin_fn, \
|
||||
.force_mode = _force_mode, \
|
||||
.sleep_set_force_mode = _sleep_set_force_mode, \
|
||||
.power_mode = _power_mode, \
|
||||
.state = _state, \
|
||||
.sleep_selectable = _sleep_selectable, \
|
||||
.system_uA = _system_uA, \
|
||||
}
|
||||
|
||||
#define RPM_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
|
||||
_supply_regulator, _system_uA, _init_peak_uA) \
|
||||
RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
|
||||
| REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
|
||||
| REGULATOR_CHANGE_DRMS, 0, _max_uV, _init_peak_uA, 0, _pd, \
|
||||
RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8930_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8930_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8930_NONE, RPM_VREG_POWER_MODE_8930_PWM, \
|
||||
RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
|
||||
_supply_regulator, _system_uA)
|
||||
|
||||
#define RPM_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
|
||||
_supply_regulator, _system_uA, _freq, _force_mode, \
|
||||
_sleep_set_force_mode) \
|
||||
RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
|
||||
| REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
|
||||
| REGULATOR_CHANGE_DRMS, 0, _min_uV, _system_uA, 0, _pd, \
|
||||
RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_8930_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8930_##_force_mode, \
|
||||
RPM_VREG_FORCE_MODE_8930_##_sleep_set_force_mode, \
|
||||
RPM_VREG_POWER_MODE_8930_PWM, RPM_VREG_STATE_OFF, \
|
||||
_sleep_selectable, _always_on, _supply_regulator, _system_uA)
|
||||
|
||||
#define RPM_VS(_id, _always_on, _pd, _sleep_selectable, _supply_regulator) \
|
||||
RPM_INIT(_id, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, 0, 1000, 1000, _pd, \
|
||||
RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8930_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8930_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8930_NONE, RPM_VREG_POWER_MODE_8930_PWM, \
|
||||
RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
|
||||
_supply_regulator, 0)
|
||||
|
||||
#define RPM_NCP(_id, _always_on, _sleep_selectable, _min_uV, _max_uV, \
|
||||
_supply_regulator, _freq) \
|
||||
RPM_INIT(_id, _min_uV, _max_uV, 0, REGULATOR_CHANGE_VOLTAGE \
|
||||
| REGULATOR_CHANGE_STATUS, 0, _max_uV, 1000, 1000, 0, \
|
||||
RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_8930_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8930_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8930_NONE, RPM_VREG_POWER_MODE_8930_PWM, \
|
||||
RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
|
||||
_supply_regulator, 0)
|
||||
|
||||
#define RPM_CORNER(_id, _always_on, _sleep_selectable, _min_uV, _max_uV, \
|
||||
_supply_regulator) \
|
||||
RPM_INIT(_id, _min_uV, _max_uV, 0, REGULATOR_CHANGE_VOLTAGE \
|
||||
| REGULATOR_CHANGE_STATUS, 0, _max_uV, 0, 0, 0, \
|
||||
RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8930_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8930_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8930_NONE, RPM_VREG_POWER_MODE_8930_PWM, \
|
||||
RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
|
||||
_supply_regulator, 0)
|
||||
|
||||
/* Pin control initialization */
|
||||
#define RPM_PC_INIT(_id, _always_on, _pin_fn, _pin_ctrl, _supply_regulator) \
|
||||
{ \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS, \
|
||||
.always_on = _always_on, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id##_PC), \
|
||||
.consumer_supplies = vreg_consumers_##_id##_PC, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.id = RPM_VREG_ID_PM8038_##_id##_PC, \
|
||||
.pin_fn = RPM_VREG_PIN_FN_8930_##_pin_fn, \
|
||||
.pin_ctrl = _pin_ctrl, \
|
||||
}
|
||||
|
||||
#define GPIO_VREG(_id, _reg_name, _gpio_label, _gpio, _supply_regulator) \
|
||||
[MSM8930_GPIO_VREG_ID_##_id] = { \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id), \
|
||||
.consumer_supplies = vreg_consumers_##_id, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.regulator_name = _reg_name, \
|
||||
.gpio_label = _gpio_label, \
|
||||
.gpio = _gpio, \
|
||||
}
|
||||
|
||||
#define SAW_VREG_INIT(_id, _name, _min_uV, _max_uV) \
|
||||
{ \
|
||||
.constraints = { \
|
||||
.name = _name, \
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, \
|
||||
.min_uV = _min_uV, \
|
||||
.max_uV = _max_uV, \
|
||||
}, \
|
||||
.num_consumer_supplies = ARRAY_SIZE(vreg_consumers_##_id), \
|
||||
.consumer_supplies = vreg_consumers_##_id, \
|
||||
}
|
||||
|
||||
/* GPIO regulator constraints */
|
||||
struct gpio_regulator_platform_data
|
||||
msm8930_gpio_regulator_pdata[] __devinitdata = {
|
||||
/* ID vreg_name gpio_label gpio supply */
|
||||
GPIO_VREG(EXT_5V, "ext_5v", "ext_5v_en", 63, NULL),
|
||||
GPIO_VREG(EXT_OTG_SW, "ext_otg_sw", "ext_otg_sw_en", 97, "ext_5v"),
|
||||
};
|
||||
|
||||
/* SAW regulator constraints */
|
||||
struct regulator_init_data msm8930_saw_regulator_core0_pdata =
|
||||
/* ID vreg_name min_uV max_uV */
|
||||
SAW_VREG_INIT(S5, "8038_s5", 850000, 1300000);
|
||||
struct regulator_init_data msm8930_saw_regulator_core1_pdata =
|
||||
SAW_VREG_INIT(S6, "8038_s6", 850000, 1300000);
|
||||
|
||||
/* PM8038 regulator constraints */
|
||||
struct pm8xxx_regulator_platform_data
|
||||
msm8930_pm8038_regulator_pdata[] __devinitdata = {
|
||||
/*
|
||||
* ID name always_on pd min_uV max_uV en_t supply
|
||||
* system_uA reg_ID
|
||||
*/
|
||||
PM8XXX_NLDO1200(L16, "8038_l16", 0, 1, 375000, 1050000, 200, "8038_s3",
|
||||
0, 0),
|
||||
PM8XXX_NLDO1200(L19, "8038_l19", 0, 1, 375000, 1050000, 200, "8038_s3",
|
||||
0, 1),
|
||||
PM8XXX_NLDO1200(L27, "8038_l27", 0, 1, 375000, 1050000, 200, "8038_s3",
|
||||
0, 2),
|
||||
};
|
||||
|
||||
static struct rpm_regulator_init_data
|
||||
msm8930_rpm_regulator_init_data[] __devinitdata = {
|
||||
/* ID a_on pd ss min_uV max_uV supply sys_uA freq fm ss_fm */
|
||||
RPM_SMPS(S1, 0, 1, 1, 500000, 1150000, NULL, 100000, 4p80, AUTO, LPM),
|
||||
RPM_SMPS(S2, 1, 1, 1, 1400000, 1400000, NULL, 100000, 1p60, AUTO, LPM),
|
||||
RPM_SMPS(S3, 0, 1, 1, 1150000, 1150000, NULL, 100000, 3p20, AUTO, LPM),
|
||||
RPM_SMPS(S4, 1, 1, 1, 1950000, 2200000, NULL, 100000, 1p60, AUTO, LPM),
|
||||
|
||||
/* ID a_on pd ss min_uV max_uV supply sys_uA init_ip */
|
||||
RPM_LDO(L1, 0, 1, 0, 1300000, 1300000, "8038_s2", 0, 0),
|
||||
RPM_LDO(L2, 0, 1, 0, 1200000, 1200000, "8038_s2", 0, 0),
|
||||
RPM_LDO(L3, 0, 1, 0, 3075000, 3075000, NULL, 0, 0),
|
||||
RPM_LDO(L4, 1, 1, 0, 1800000, 1800000, NULL, 10000, 10000),
|
||||
RPM_LDO(L5, 0, 1, 0, 2950000, 2950000, NULL, 0, 0),
|
||||
RPM_LDO(L6, 0, 1, 0, 2950000, 2950000, NULL, 0, 0),
|
||||
RPM_LDO(L7, 0, 1, 0, 2050000, 2050000, "8038_s4", 0, 0),
|
||||
RPM_LDO(L8, 0, 1, 0, 2800000, 2800000, NULL, 0, 0),
|
||||
RPM_LDO(L9, 0, 1, 0, 2850000, 2850000, NULL, 0, 0),
|
||||
RPM_LDO(L10, 0, 1, 0, 2900000, 2900000, NULL, 0, 0),
|
||||
RPM_LDO(L11, 1, 1, 0, 1800000, 1800000, "8038_s4", 10000, 10000),
|
||||
RPM_LDO(L12, 0, 1, 0, 1200000, 1200000, "8038_s2", 0, 0),
|
||||
RPM_LDO(L14, 0, 1, 0, 1800000, 1800000, NULL, 0, 0),
|
||||
RPM_LDO(L15, 0, 1, 0, 1800000, 2950000, NULL, 0, 0),
|
||||
RPM_LDO(L17, 0, 1, 0, 1800000, 2950000, NULL, 0, 0),
|
||||
RPM_LDO(L18, 0, 1, 0, 1800000, 1800000, NULL, 0, 0),
|
||||
RPM_LDO(L20, 1, 1, 0, 1200000, 1200000, "8038_s2", 10000, 10000),
|
||||
RPM_LDO(L21, 0, 1, 0, 1900000, 1900000, "8038_s4", 0, 0),
|
||||
RPM_LDO(L22, 1, 1, 0, 1850000, 2950000, NULL, 10000, 10000),
|
||||
RPM_LDO(L23, 1, 1, 1, 1800000, 1800000, "8038_s4", 0, 0),
|
||||
RPM_LDO(L24, 0, 1, 1, 500000, 1150000, "8038_s2", 10000, 10000),
|
||||
RPM_LDO(L26, 1, 1, 0, 1050000, 1050000, "8038_s2", 10000, 10000),
|
||||
|
||||
/* ID a_on pd ss supply */
|
||||
RPM_VS(LVS1, 0, 1, 0, "8038_l11"),
|
||||
RPM_VS(LVS2, 0, 1, 0, "8038_l11"),
|
||||
|
||||
/* ID a_on ss min_corner max_corner supply */
|
||||
RPM_CORNER(VDD_DIG_CORNER, 0, 1, RPM_VREG_CORNER_NONE,
|
||||
RPM_VREG_CORNER_HIGH, NULL),
|
||||
};
|
||||
|
||||
int msm8930_pm8038_regulator_pdata_len __devinitdata =
|
||||
ARRAY_SIZE(msm8930_pm8038_regulator_pdata);
|
||||
|
||||
struct rpm_regulator_platform_data msm8930_rpm_regulator_pdata __devinitdata = {
|
||||
.init_data = msm8930_rpm_regulator_init_data,
|
||||
.num_regulators = ARRAY_SIZE(msm8930_rpm_regulator_init_data),
|
||||
.version = RPM_VREG_VERSION_8930,
|
||||
.vreg_id_vdd_mem = RPM_VREG_ID_PM8038_L24,
|
||||
.vreg_id_vdd_dig = RPM_VREG_ID_PM8038_VDD_DIG_CORNER,
|
||||
};
|
||||
304
arch/arm/mach-msm/board-8930-storage.c
Normal file
304
arch/arm/mach-msm/board-8930-storage.c
Normal file
@@ -0,0 +1,304 @@
|
||||
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/mmc.h>
|
||||
#include <mach/msm_bus_board.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/gpiomux.h>
|
||||
#include "devices.h"
|
||||
|
||||
#include "board-8930.h"
|
||||
#include "board-storage-common-a.h"
|
||||
|
||||
/* MSM8960 has 5 SDCC controllers */
|
||||
enum sdcc_controllers {
|
||||
SDCC1,
|
||||
SDCC2,
|
||||
SDCC3,
|
||||
SDCC4,
|
||||
SDCC5,
|
||||
MAX_SDCC_CONTROLLER
|
||||
};
|
||||
|
||||
/* All SDCC controllers require VDD/VCC voltage */
|
||||
static struct msm_mmc_reg_data mmc_vdd_reg_data[MAX_SDCC_CONTROLLER] = {
|
||||
/* SDCC1 : eMMC card connected */
|
||||
[SDCC1] = {
|
||||
.name = "sdc_vdd",
|
||||
.high_vol_level = 2950000,
|
||||
.low_vol_level = 2950000,
|
||||
.always_on = 1,
|
||||
.lpm_sup = 1,
|
||||
.lpm_uA = 9000,
|
||||
.hpm_uA = 200000, /* 200mA */
|
||||
},
|
||||
/* SDCC3 : External card slot connected */
|
||||
[SDCC3] = {
|
||||
.name = "sdc_vdd",
|
||||
.high_vol_level = 2950000,
|
||||
.low_vol_level = 2950000,
|
||||
/*
|
||||
* Normally this is not an always ON regulator. On this
|
||||
* platform, unfortunately the sd detect line is connected
|
||||
* to this via esd circuit and so turn this off/on while card
|
||||
* is not present causes the sd detect line to toggle
|
||||
* continuously. This is expected to be fixed in the newer
|
||||
* hardware revisions - maybe once that is done, this can be
|
||||
* reverted.
|
||||
*/
|
||||
.always_on = 1,
|
||||
.lpm_sup = 1,
|
||||
.hpm_uA = 800000, /* 800mA */
|
||||
.lpm_uA = 9000,
|
||||
}
|
||||
};
|
||||
|
||||
/* All SDCC controllers may require voting for VDD PAD voltage */
|
||||
static struct msm_mmc_reg_data mmc_vdd_io_reg_data[MAX_SDCC_CONTROLLER] = {
|
||||
/* SDCC1 : eMMC card connected */
|
||||
[SDCC1] = {
|
||||
.name = "sdc_vdd_io",
|
||||
.always_on = 1,
|
||||
.high_vol_level = 1800000,
|
||||
.low_vol_level = 1800000,
|
||||
.hpm_uA = 200000, /* 200mA */
|
||||
},
|
||||
/* SDCC3 : External card slot connected */
|
||||
[SDCC3] = {
|
||||
.name = "sdc_vdd_io",
|
||||
.high_vol_level = 2950000,
|
||||
.low_vol_level = 1850000,
|
||||
.always_on = 1,
|
||||
.lpm_sup = 1,
|
||||
/* Max. Active current required is 16 mA */
|
||||
.hpm_uA = 16000,
|
||||
/*
|
||||
* Sleep current required is ~300 uA. But min. vote can be
|
||||
* in terms of mA (min. 1 mA). So let's vote for 2 mA
|
||||
* during sleep.
|
||||
*/
|
||||
.lpm_uA = 2000,
|
||||
}
|
||||
};
|
||||
|
||||
static struct msm_mmc_slot_reg_data mmc_slot_vreg_data[MAX_SDCC_CONTROLLER] = {
|
||||
/* SDCC1 : eMMC card connected */
|
||||
[SDCC1] = {
|
||||
.vdd_data = &mmc_vdd_reg_data[SDCC1],
|
||||
.vdd_io_data = &mmc_vdd_io_reg_data[SDCC1],
|
||||
},
|
||||
/* SDCC3 : External card slot connected */
|
||||
[SDCC3] = {
|
||||
.vdd_data = &mmc_vdd_reg_data[SDCC3],
|
||||
.vdd_io_data = &mmc_vdd_io_reg_data[SDCC3],
|
||||
}
|
||||
};
|
||||
|
||||
/* SDC1 pad data */
|
||||
static struct msm_mmc_pad_drv sdc1_pad_drv_on_cfg[] = {
|
||||
{TLMM_HDRV_SDC1_CLK, GPIO_CFG_16MA},
|
||||
{TLMM_HDRV_SDC1_CMD, GPIO_CFG_10MA},
|
||||
{TLMM_HDRV_SDC1_DATA, GPIO_CFG_10MA}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_drv sdc1_pad_drv_off_cfg[] = {
|
||||
{TLMM_HDRV_SDC1_CLK, GPIO_CFG_2MA},
|
||||
{TLMM_HDRV_SDC1_CMD, GPIO_CFG_2MA},
|
||||
{TLMM_HDRV_SDC1_DATA, GPIO_CFG_2MA}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull sdc1_pad_pull_on_cfg[] = {
|
||||
{TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL},
|
||||
{TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP},
|
||||
{TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull sdc1_pad_pull_off_cfg[] = {
|
||||
{TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL},
|
||||
{TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP},
|
||||
{TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP}
|
||||
};
|
||||
|
||||
/* SDC3 pad data */
|
||||
static struct msm_mmc_pad_drv sdc3_pad_drv_on_cfg[] = {
|
||||
{TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA},
|
||||
{TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA},
|
||||
{TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_drv sdc3_pad_drv_off_cfg[] = {
|
||||
{TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA},
|
||||
{TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA},
|
||||
{TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull sdc3_pad_pull_on_cfg[] = {
|
||||
{TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL},
|
||||
{TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
|
||||
{TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull sdc3_pad_pull_off_cfg[] = {
|
||||
{TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL},
|
||||
/*
|
||||
* SDC3 CMD line should be PULLed UP otherwise fluid platform will
|
||||
* see transitions (1 -> 0 and 0 -> 1) on card detection line,
|
||||
* which would result in false card detection interrupts.
|
||||
*/
|
||||
{TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
|
||||
/*
|
||||
* Keeping DATA lines status to PULL UP will make sure that
|
||||
* there is no current leak during sleep if external pull up
|
||||
* is connected to DATA lines.
|
||||
*/
|
||||
{TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull_data mmc_pad_pull_data[MAX_SDCC_CONTROLLER] = {
|
||||
[SDCC1] = {
|
||||
.on = sdc1_pad_pull_on_cfg,
|
||||
.off = sdc1_pad_pull_off_cfg,
|
||||
.size = ARRAY_SIZE(sdc1_pad_pull_on_cfg)
|
||||
},
|
||||
[SDCC3] = {
|
||||
.on = sdc3_pad_pull_on_cfg,
|
||||
.off = sdc3_pad_pull_off_cfg,
|
||||
.size = ARRAY_SIZE(sdc3_pad_pull_on_cfg)
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_drv_data mmc_pad_drv_data[MAX_SDCC_CONTROLLER] = {
|
||||
[SDCC1] = {
|
||||
.on = sdc1_pad_drv_on_cfg,
|
||||
.off = sdc1_pad_drv_off_cfg,
|
||||
.size = ARRAY_SIZE(sdc1_pad_drv_on_cfg)
|
||||
},
|
||||
[SDCC3] = {
|
||||
.on = sdc3_pad_drv_on_cfg,
|
||||
.off = sdc3_pad_drv_off_cfg,
|
||||
.size = ARRAY_SIZE(sdc3_pad_drv_on_cfg)
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_data mmc_pad_data[MAX_SDCC_CONTROLLER] = {
|
||||
[SDCC1] = {
|
||||
.pull = &mmc_pad_pull_data[SDCC1],
|
||||
.drv = &mmc_pad_drv_data[SDCC1]
|
||||
},
|
||||
[SDCC3] = {
|
||||
.pull = &mmc_pad_pull_data[SDCC3],
|
||||
.drv = &mmc_pad_drv_data[SDCC3]
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_mmc_pin_data mmc_slot_pin_data[MAX_SDCC_CONTROLLER] = {
|
||||
[SDCC1] = {
|
||||
.pad_data = &mmc_pad_data[SDCC1],
|
||||
},
|
||||
[SDCC3] = {
|
||||
.pad_data = &mmc_pad_data[SDCC3],
|
||||
},
|
||||
};
|
||||
|
||||
#define MSM_MPM_PIN_SDC1_DAT1 17
|
||||
#define MSM_MPM_PIN_SDC3_DAT1 21
|
||||
|
||||
static unsigned int sdc1_sup_clk_rates[] = {
|
||||
400000, 24000000, 48000000,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
|
||||
static unsigned int sdc3_sup_clk_rates[] = {
|
||||
400000, 24000000, 48000000, 96000000, 192000000,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
|
||||
static struct mmc_platform_data msm8960_sdc1_data = {
|
||||
.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
|
||||
#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
|
||||
.mmc_bus_width = MMC_CAP_8_BIT_DATA,
|
||||
#else
|
||||
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
|
||||
#endif
|
||||
.sup_clk_table = sdc1_sup_clk_rates,
|
||||
.sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates),
|
||||
.pclk_src_dfab = 1,
|
||||
.nonremovable = 1,
|
||||
.vreg_data = &mmc_slot_vreg_data[SDCC1],
|
||||
.pin_data = &mmc_slot_pin_data[SDCC1],
|
||||
.mpm_sdiowakeup_int = MSM_MPM_PIN_SDC1_DAT1,
|
||||
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
|
||||
static struct mmc_platform_data msm8960_sdc3_data = {
|
||||
.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
|
||||
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
|
||||
.sup_clk_table = sdc3_sup_clk_rates,
|
||||
.sup_clk_cnt = ARRAY_SIZE(sdc3_sup_clk_rates),
|
||||
.pclk_src_dfab = 1,
|
||||
#ifdef CONFIG_MMC_MSM_SDC3_WP_SUPPORT
|
||||
/*TODO: Insert right replacement for PM8038 */
|
||||
#ifndef MSM8930_PHASE_2
|
||||
.wpswitch_gpio = PM8921_GPIO_PM_TO_SYS(16),
|
||||
#else
|
||||
.wpswitch_gpio = 66,
|
||||
.wpswitch_polarity = 1,
|
||||
#endif
|
||||
#endif
|
||||
.vreg_data = &mmc_slot_vreg_data[SDCC3],
|
||||
.pin_data = &mmc_slot_pin_data[SDCC3],
|
||||
#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
|
||||
/*TODO: Insert right replacement for PM8038 */
|
||||
#ifndef MSM8930_PHASE_2
|
||||
.status_gpio = PM8921_GPIO_PM_TO_SYS(26),
|
||||
.status_irq = PM8921_GPIO_IRQ(PM8921_IRQ_BASE, 26),
|
||||
#else
|
||||
.status_gpio = 94,
|
||||
.status_irq = MSM_GPIO_TO_INT(94),
|
||||
#endif
|
||||
.irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
|
||||
.is_status_gpio_active_low = true,
|
||||
#endif
|
||||
.xpc_cap = 1,
|
||||
.uhs_caps = (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
|
||||
MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 |
|
||||
MMC_CAP_UHS_SDR104 | MMC_CAP_MAX_CURRENT_800),
|
||||
.mpm_sdiowakeup_int = MSM_MPM_PIN_SDC3_DAT1,
|
||||
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
|
||||
};
|
||||
#endif
|
||||
|
||||
void __init msm8930_init_mmc(void)
|
||||
{
|
||||
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
|
||||
/* SDC1 : eMMC card connected */
|
||||
msm_add_sdcc(1, &msm8960_sdc1_data);
|
||||
#endif
|
||||
#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
|
||||
/* SDC3: External card slot */
|
||||
if (!machine_is_msm8930_cdp()) {
|
||||
msm8960_sdc3_data.wpswitch_gpio = 0;
|
||||
msm8960_sdc3_data.wpswitch_polarity = 0;
|
||||
}
|
||||
msm_add_sdcc(3, &msm8960_sdc3_data);
|
||||
#endif
|
||||
}
|
||||
2456
arch/arm/mach-msm/board-8930.c
Normal file
2456
arch/arm/mach-msm/board-8930.c
Normal file
File diff suppressed because it is too large
Load Diff
142
arch/arm/mach-msm/board-8930.h
Normal file
142
arch/arm/mach-msm/board-8930.h
Normal file
@@ -0,0 +1,142 @@
|
||||
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_MSM_BOARD_MSM8930_H
|
||||
#define __ARCH_ARM_MACH_MSM_BOARD_MSM8930_H
|
||||
|
||||
#define MSM8930_PHASE_2
|
||||
|
||||
#include <linux/regulator/msm-gpio-regulator.h>
|
||||
#include <linux/mfd/pm8xxx/pm8038.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c/sx150x.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/rpm-regulator.h>
|
||||
#include <mach/msm_memtypes.h>
|
||||
#include <mach/msm_rtb.h>
|
||||
|
||||
/*
|
||||
* TODO: When physical 8930/PM8038 hardware becomes
|
||||
* available, remove this block.
|
||||
*/
|
||||
#ifndef MSM8930_PHASE_2
|
||||
#include <linux/mfd/pm8xxx/pm8921.h>
|
||||
#define PM8921_GPIO_BASE NR_GPIO_IRQS
|
||||
#define PM8921_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio - 1 + PM8921_GPIO_BASE)
|
||||
#define PM8921_MPP_BASE (PM8921_GPIO_BASE + PM8921_NR_GPIOS)
|
||||
#define PM8921_MPP_PM_TO_SYS(pm_gpio) (pm_gpio - 1 + PM8921_MPP_BASE)
|
||||
#endif
|
||||
|
||||
/* Macros assume PMIC GPIOs and MPPs start at 1 */
|
||||
#define PM8038_GPIO_BASE NR_GPIO_IRQS
|
||||
#define PM8038_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio - 1 + PM8038_GPIO_BASE)
|
||||
#define PM8038_MPP_BASE (PM8038_GPIO_BASE + PM8038_NR_GPIOS)
|
||||
#define PM8038_MPP_PM_TO_SYS(pm_gpio) (pm_gpio - 1 + PM8038_MPP_BASE)
|
||||
#define PM8038_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
|
||||
|
||||
/*
|
||||
* TODO: When physical 8930/PM8038 hardware becomes
|
||||
* available, replace this block with 8930/pm8038 regulator
|
||||
* declarations.
|
||||
*/
|
||||
#ifndef MSM8930_PHASE_2
|
||||
extern struct pm8xxx_regulator_platform_data
|
||||
msm_pm8921_regulator_pdata[] __devinitdata;
|
||||
|
||||
extern int msm_pm8921_regulator_pdata_len __devinitdata;
|
||||
|
||||
extern struct gpio_regulator_platform_data
|
||||
msm_gpio_regulator_pdata[] __devinitdata;
|
||||
|
||||
extern struct rpm_regulator_platform_data msm_rpm_regulator_pdata __devinitdata;
|
||||
|
||||
#define GPIO_VREG_ID_EXT_5V 0
|
||||
#define GPIO_VREG_ID_EXT_L2 1
|
||||
#define GPIO_VREG_ID_EXT_3P3V 2
|
||||
#endif
|
||||
|
||||
extern struct regulator_init_data msm8930_saw_regulator_core0_pdata;
|
||||
extern struct regulator_init_data msm8930_saw_regulator_core1_pdata;
|
||||
|
||||
extern struct pm8xxx_regulator_platform_data
|
||||
msm8930_pm8038_regulator_pdata[] __devinitdata;
|
||||
|
||||
extern int msm8930_pm8038_regulator_pdata_len __devinitdata;
|
||||
|
||||
#define MSM8930_GPIO_VREG_ID_EXT_5V 0
|
||||
#define MSM8930_GPIO_VREG_ID_EXT_OTG_SW 1
|
||||
|
||||
extern struct gpio_regulator_platform_data
|
||||
msm8930_gpio_regulator_pdata[] __devinitdata;
|
||||
|
||||
extern struct rpm_regulator_platform_data
|
||||
msm8930_rpm_regulator_pdata __devinitdata;
|
||||
|
||||
#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
|
||||
enum {
|
||||
GPIO_EXPANDER_IRQ_BASE = (PM8038_IRQ_BASE + PM8038_NR_IRQS),
|
||||
GPIO_EXPANDER_GPIO_BASE = (PM8038_MPP_BASE + PM8038_NR_MPPS),
|
||||
/* CAM Expander */
|
||||
GPIO_CAM_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE,
|
||||
GPIO_CAM_GP_STROBE_READY = GPIO_CAM_EXPANDER_BASE,
|
||||
GPIO_CAM_GP_AFBUSY,
|
||||
GPIO_CAM_GP_STROBE_CE,
|
||||
GPIO_CAM_GP_CAM1MP_XCLR,
|
||||
GPIO_CAM_GP_CAMIF_RESET_N,
|
||||
GPIO_CAM_GP_XMT_FLASH_INT,
|
||||
GPIO_CAM_GP_LED_EN1,
|
||||
GPIO_CAM_GP_LED_EN2,
|
||||
|
||||
};
|
||||
#endif
|
||||
|
||||
enum {
|
||||
SX150X_CAM,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
extern struct sx150x_platform_data msm8930_sx150x_data[];
|
||||
extern struct msm_camera_board_info msm8930_camera_board_info;
|
||||
void msm8930_init_cam(void);
|
||||
void msm8930_init_fb(void);
|
||||
void msm8930_init_pmic(void);
|
||||
extern void msm8930_add_vidc_device(void);
|
||||
|
||||
/*
|
||||
* TODO: When physical 8930/PM8038 hardware becomes
|
||||
* available, remove this block or add the config
|
||||
* option.
|
||||
*/
|
||||
#ifndef MSM8930_PHASE_2
|
||||
void msm8960_init_pmic(void);
|
||||
void msm8960_pm8921_gpio_mpp_init(void);
|
||||
#endif
|
||||
|
||||
void msm8930_init_mmc(void);
|
||||
int msm8930_init_gpiomux(void);
|
||||
void msm8930_allocate_fb_region(void);
|
||||
void msm8930_pm8038_gpio_mpp_init(void);
|
||||
void msm8930_mdp_writeback(struct memtype_reserve *reserve_table);
|
||||
void __init msm8930_init_gpu(void);
|
||||
|
||||
#define PLATFORM_IS_CHARM25() \
|
||||
(machine_is_msm8930_cdp() && \
|
||||
(socinfo_get_platform_subtype() == 1) \
|
||||
)
|
||||
|
||||
#define MSM_8930_GSBI3_QUP_I2C_BUS_ID 3
|
||||
#define MSM_8930_GSBI4_QUP_I2C_BUS_ID 4
|
||||
#define MSM_8930_GSBI9_QUP_I2C_BUS_ID 0
|
||||
#define MSM_8930_GSBI10_QUP_I2C_BUS_ID 10
|
||||
|
||||
extern struct msm_rtb_platform_data msm8930_rtb_pdata;
|
||||
812
arch/arm/mach-msm/board-8960-camera.c
Normal file
812
arch/arm/mach-msm/board-8960-camera.c
Normal file
@@ -0,0 +1,812 @@
|
||||
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/msm_bus_board.h>
|
||||
#include <mach/gpiomux.h>
|
||||
#include "devices.h"
|
||||
#include "board-8960.h"
|
||||
|
||||
#ifdef CONFIG_MSM_CAMERA
|
||||
|
||||
#if (defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)) && \
|
||||
defined(CONFIG_I2C)
|
||||
|
||||
static struct i2c_board_info cam_expander_i2c_info[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("sx1508q", 0x22),
|
||||
.platform_data = &msm8960_sx150x_data[SX150X_CAM]
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_cam_expander_info cam_expander_info[] = {
|
||||
{
|
||||
cam_expander_i2c_info,
|
||||
MSM_8960_GSBI4_QUP_I2C_BUS_ID,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct gpiomux_setting cam_settings[] = {
|
||||
{
|
||||
.func = GPIOMUX_FUNC_GPIO, /*suspend*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_DOWN,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_1, /*active 1*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_GPIO, /*active 2*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_1, /*active 3*/
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_NONE,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_5, /*active 4*/
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_6, /*active 5*/
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_2, /*active 6*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_3, /*active 7*/
|
||||
.drv = GPIOMUX_DRV_8MA,
|
||||
.pull = GPIOMUX_PULL_UP,
|
||||
},
|
||||
|
||||
{
|
||||
.func = GPIOMUX_FUNC_GPIO, /*i2c suspend*/
|
||||
.drv = GPIOMUX_DRV_2MA,
|
||||
.pull = GPIOMUX_PULL_KEEPER,
|
||||
},
|
||||
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config msm8960_cdp_flash_configs[] = {
|
||||
{
|
||||
.gpio = 3,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[1],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config msm8960_cam_common_configs[] = {
|
||||
{
|
||||
.gpio = 2,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[2],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 3,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[2],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 4,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[1],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 5,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[3],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 76,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[2],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 107,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[2],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[0],
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_gpiomux_config msm8960_cam_2d_configs[] = {
|
||||
{
|
||||
.gpio = 18,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[3],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[8],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 19,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[3],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[8],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 20,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[3],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[8],
|
||||
},
|
||||
},
|
||||
{
|
||||
.gpio = 21,
|
||||
.settings = {
|
||||
[GPIOMUX_ACTIVE] = &cam_settings[3],
|
||||
[GPIOMUX_SUSPENDED] = &cam_settings[8],
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
#define VFE_CAMIF_TIMER1_GPIO 2
|
||||
#define VFE_CAMIF_TIMER2_GPIO 3
|
||||
#define VFE_CAMIF_TIMER3_GPIO_INT 4
|
||||
static struct msm_camera_sensor_strobe_flash_data strobe_flash_xenon = {
|
||||
.flash_trigger = VFE_CAMIF_TIMER2_GPIO,
|
||||
.flash_charge = VFE_CAMIF_TIMER1_GPIO,
|
||||
.flash_charge_done = VFE_CAMIF_TIMER3_GPIO_INT,
|
||||
.flash_recharge_duration = 50000,
|
||||
.irq = MSM_GPIO_TO_INT(VFE_CAMIF_TIMER3_GPIO_INT),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MSM_CAMERA_FLASH
|
||||
static struct msm_camera_sensor_flash_src msm_flash_src = {
|
||||
.flash_sr_type = MSM_CAMERA_FLASH_SRC_EXT,
|
||||
._fsrc.ext_driver_src.led_en = VFE_CAMIF_TIMER1_GPIO,
|
||||
._fsrc.ext_driver_src.led_flash_en = VFE_CAMIF_TIMER2_GPIO,
|
||||
._fsrc.ext_driver_src.flash_id = MAM_CAMERA_EXT_LED_FLASH_SC628A,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct msm_bus_vectors cam_init_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_MM_IMEM,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_MM_IMEM,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors cam_preview_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 27648000,
|
||||
.ib = 110592000,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_MM_IMEM,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_MM_IMEM,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors cam_video_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 154275840,
|
||||
.ib = 617103360,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 206807040,
|
||||
.ib = 488816640,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_MM_IMEM,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_MM_IMEM,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors cam_snapshot_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 274423680,
|
||||
.ib = 1097694720,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 540000000,
|
||||
.ib = 1350000000,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_MM_IMEM,
|
||||
.ab = 43200000,
|
||||
.ib = 69120000,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_MM_IMEM,
|
||||
.ab = 43200000,
|
||||
.ib = 69120000,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_vectors cam_zsl_vectors[] = {
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 302071680,
|
||||
.ib = 1208286720,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VPE,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 0,
|
||||
.ib = 0,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_EBI_CH0,
|
||||
.ab = 540000000,
|
||||
.ib = 1350000000,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_JPEG_ENC,
|
||||
.dst = MSM_BUS_SLAVE_MM_IMEM,
|
||||
.ab = 43200000,
|
||||
.ib = 69120000,
|
||||
},
|
||||
{
|
||||
.src = MSM_BUS_MASTER_VFE,
|
||||
.dst = MSM_BUS_SLAVE_MM_IMEM,
|
||||
.ab = 43200000,
|
||||
.ib = 69120000,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_paths cam_bus_client_config[] = {
|
||||
{
|
||||
ARRAY_SIZE(cam_init_vectors),
|
||||
cam_init_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(cam_preview_vectors),
|
||||
cam_preview_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(cam_video_vectors),
|
||||
cam_video_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(cam_snapshot_vectors),
|
||||
cam_snapshot_vectors,
|
||||
},
|
||||
{
|
||||
ARRAY_SIZE(cam_zsl_vectors),
|
||||
cam_zsl_vectors,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_bus_scale_pdata cam_bus_client_pdata = {
|
||||
cam_bus_client_config,
|
||||
ARRAY_SIZE(cam_bus_client_config),
|
||||
.name = "msm_camera",
|
||||
};
|
||||
|
||||
static struct msm_camera_device_platform_data msm_camera_csi_device_data[] = {
|
||||
{
|
||||
.csid_core = 0,
|
||||
.is_csiphy = 1,
|
||||
.is_csid = 1,
|
||||
.is_ispif = 1,
|
||||
.is_vpe = 1,
|
||||
.cam_bus_scale_table = &cam_bus_client_pdata,
|
||||
},
|
||||
{
|
||||
.csid_core = 1,
|
||||
.is_csiphy = 1,
|
||||
.is_csid = 1,
|
||||
.is_ispif = 1,
|
||||
.is_vpe = 1,
|
||||
.cam_bus_scale_table = &cam_bus_client_pdata,
|
||||
},
|
||||
{
|
||||
.csid_core = 2,
|
||||
.is_csiphy = 1,
|
||||
.is_csid = 1,
|
||||
.is_ispif = 1,
|
||||
.is_vpe = 1,
|
||||
.cam_bus_scale_table = &cam_bus_client_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct camera_vreg_t msm_8960_back_cam_vreg[] = {
|
||||
{"cam_vdig", REG_LDO, 1200000, 1200000, 105000},
|
||||
{"cam_vio", REG_VS, 0, 0, 0},
|
||||
{"cam_vana", REG_LDO, 2800000, 2850000, 85600},
|
||||
{"cam_vaf", REG_LDO, 2800000, 2800000, 300000},
|
||||
};
|
||||
|
||||
static struct camera_vreg_t msm_8960_front_cam_vreg[] = {
|
||||
{"cam_vio", REG_VS, 0, 0, 0},
|
||||
{"cam_vana", REG_LDO, 2800000, 2850000, 85600},
|
||||
{"cam_vdig", REG_LDO, 1200000, 1200000, 105000},
|
||||
};
|
||||
|
||||
static struct gpio msm8960_common_cam_gpio[] = {
|
||||
{5, GPIOF_DIR_IN, "CAMIF_MCLK"},
|
||||
{20, GPIOF_DIR_IN, "CAMIF_I2C_DATA"},
|
||||
{21, GPIOF_DIR_IN, "CAMIF_I2C_CLK"},
|
||||
};
|
||||
|
||||
static struct gpio msm8960_front_cam_gpio[] = {
|
||||
{76, GPIOF_DIR_OUT, "CAM_RESET"},
|
||||
};
|
||||
|
||||
static struct gpio msm8960_back_cam_gpio[] = {
|
||||
{107, GPIOF_DIR_OUT, "CAM_RESET"},
|
||||
};
|
||||
|
||||
static struct msm_gpio_set_tbl msm8960_front_cam_gpio_set_tbl[] = {
|
||||
{76, GPIOF_OUT_INIT_LOW, 1000},
|
||||
{76, GPIOF_OUT_INIT_HIGH, 4000},
|
||||
};
|
||||
|
||||
static struct msm_gpio_set_tbl msm8960_back_cam_gpio_set_tbl[] = {
|
||||
{107, GPIOF_OUT_INIT_LOW, 1000},
|
||||
{107, GPIOF_OUT_INIT_HIGH, 4000},
|
||||
};
|
||||
|
||||
static struct msm_camera_gpio_conf msm_8960_front_cam_gpio_conf = {
|
||||
.cam_gpiomux_conf_tbl = msm8960_cam_2d_configs,
|
||||
.cam_gpiomux_conf_tbl_size = ARRAY_SIZE(msm8960_cam_2d_configs),
|
||||
.cam_gpio_common_tbl = msm8960_common_cam_gpio,
|
||||
.cam_gpio_common_tbl_size = ARRAY_SIZE(msm8960_common_cam_gpio),
|
||||
.cam_gpio_req_tbl = msm8960_front_cam_gpio,
|
||||
.cam_gpio_req_tbl_size = ARRAY_SIZE(msm8960_front_cam_gpio),
|
||||
.cam_gpio_set_tbl = msm8960_front_cam_gpio_set_tbl,
|
||||
.cam_gpio_set_tbl_size = ARRAY_SIZE(msm8960_front_cam_gpio_set_tbl),
|
||||
};
|
||||
|
||||
static struct msm_camera_gpio_conf msm_8960_back_cam_gpio_conf = {
|
||||
.cam_gpiomux_conf_tbl = msm8960_cam_2d_configs,
|
||||
.cam_gpiomux_conf_tbl_size = ARRAY_SIZE(msm8960_cam_2d_configs),
|
||||
.cam_gpio_common_tbl = msm8960_common_cam_gpio,
|
||||
.cam_gpio_common_tbl_size = ARRAY_SIZE(msm8960_common_cam_gpio),
|
||||
.cam_gpio_req_tbl = msm8960_back_cam_gpio,
|
||||
.cam_gpio_req_tbl_size = ARRAY_SIZE(msm8960_back_cam_gpio),
|
||||
.cam_gpio_set_tbl = msm8960_back_cam_gpio_set_tbl,
|
||||
.cam_gpio_set_tbl_size = ARRAY_SIZE(msm8960_back_cam_gpio_set_tbl),
|
||||
};
|
||||
|
||||
static struct i2c_board_info msm_act_main_cam_i2c_info = {
|
||||
I2C_BOARD_INFO("msm_actuator", 0x11),
|
||||
};
|
||||
|
||||
static struct msm_actuator_info msm_act_main_cam_0_info = {
|
||||
.board_info = &msm_act_main_cam_i2c_info,
|
||||
.cam_name = MSM_ACTUATOR_MAIN_CAM_0,
|
||||
.bus_id = MSM_8960_GSBI4_QUP_I2C_BUS_ID,
|
||||
.vcm_pwd = 0,
|
||||
.vcm_enable = 0,
|
||||
};
|
||||
|
||||
static struct i2c_board_info msm_act_main_cam1_i2c_info = {
|
||||
I2C_BOARD_INFO("msm_actuator", 0x18),
|
||||
};
|
||||
|
||||
static struct msm_actuator_info msm_act_main_cam_1_info = {
|
||||
.board_info = &msm_act_main_cam1_i2c_info,
|
||||
.cam_name = MSM_ACTUATOR_MAIN_CAM_1,
|
||||
.bus_id = MSM_8960_GSBI4_QUP_I2C_BUS_ID,
|
||||
.vcm_pwd = 0,
|
||||
.vcm_enable = 0,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_flash_data flash_imx074 = {
|
||||
.flash_type = MSM_CAMERA_FLASH_LED,
|
||||
#ifdef CONFIG_MSM_CAMERA_FLASH
|
||||
.flash_src = &msm_flash_src
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct msm_camera_csi_lane_params imx074_csi_lane_params = {
|
||||
.csi_lane_assign = 0xE4,
|
||||
.csi_lane_mask = 0xF,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_platform_info sensor_board_info_imx074 = {
|
||||
.mount_angle = 90,
|
||||
.cam_vreg = msm_8960_back_cam_vreg,
|
||||
.num_vreg = ARRAY_SIZE(msm_8960_back_cam_vreg),
|
||||
.gpio_conf = &msm_8960_back_cam_gpio_conf,
|
||||
.csi_lane_params = &imx074_csi_lane_params,
|
||||
};
|
||||
|
||||
static struct i2c_board_info imx074_eeprom_i2c_info = {
|
||||
I2C_BOARD_INFO("imx074_eeprom", 0x34 << 1),
|
||||
};
|
||||
|
||||
static struct msm_eeprom_info imx074_eeprom_info = {
|
||||
.board_info = &imx074_eeprom_i2c_info,
|
||||
.bus_id = MSM_8960_GSBI4_QUP_I2C_BUS_ID,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_info msm_camera_sensor_imx074_data = {
|
||||
.sensor_name = "imx074",
|
||||
.pdata = &msm_camera_csi_device_data[0],
|
||||
.flash_data = &flash_imx074,
|
||||
.strobe_flash_data = &strobe_flash_xenon,
|
||||
.sensor_platform_info = &sensor_board_info_imx074,
|
||||
.csi_if = 1,
|
||||
.camera_type = BACK_CAMERA_2D,
|
||||
.sensor_type = BAYER_SENSOR,
|
||||
.actuator_info = &msm_act_main_cam_0_info,
|
||||
.eeprom_info = &imx074_eeprom_info,
|
||||
};
|
||||
|
||||
static struct camera_vreg_t msm_8960_mt9m114_vreg[] = {
|
||||
{"cam_vio", REG_VS, 0, 0, 0},
|
||||
{"cam_vdig", REG_LDO, 1200000, 1200000, 105000},
|
||||
{"cam_vana", REG_LDO, 2800000, 2850000, 85600},
|
||||
{"cam_vaf", REG_LDO, 2800000, 2800000, 300000},
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_flash_data flash_mt9m114 = {
|
||||
.flash_type = MSM_CAMERA_FLASH_NONE
|
||||
};
|
||||
|
||||
static struct msm_camera_csi_lane_params mt9m114_csi_lane_params = {
|
||||
.csi_lane_assign = 0xE4,
|
||||
.csi_lane_mask = 0x1,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_platform_info sensor_board_info_mt9m114 = {
|
||||
.mount_angle = 90,
|
||||
.cam_vreg = msm_8960_mt9m114_vreg,
|
||||
.num_vreg = ARRAY_SIZE(msm_8960_mt9m114_vreg),
|
||||
.gpio_conf = &msm_8960_front_cam_gpio_conf,
|
||||
.csi_lane_params = &mt9m114_csi_lane_params,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_info msm_camera_sensor_mt9m114_data = {
|
||||
.sensor_name = "mt9m114",
|
||||
.pdata = &msm_camera_csi_device_data[1],
|
||||
.flash_data = &flash_mt9m114,
|
||||
.sensor_platform_info = &sensor_board_info_mt9m114,
|
||||
.csi_if = 1,
|
||||
.camera_type = FRONT_CAMERA_2D,
|
||||
.sensor_type = YUV_SENSOR,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_flash_data flash_ov2720 = {
|
||||
.flash_type = MSM_CAMERA_FLASH_NONE,
|
||||
};
|
||||
|
||||
static struct msm_camera_csi_lane_params ov2720_csi_lane_params = {
|
||||
.csi_lane_assign = 0xE4,
|
||||
.csi_lane_mask = 0x3,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_platform_info sensor_board_info_ov2720 = {
|
||||
.mount_angle = 0,
|
||||
.cam_vreg = msm_8960_front_cam_vreg,
|
||||
.num_vreg = ARRAY_SIZE(msm_8960_front_cam_vreg),
|
||||
.gpio_conf = &msm_8960_front_cam_gpio_conf,
|
||||
.csi_lane_params = &ov2720_csi_lane_params,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_info msm_camera_sensor_ov2720_data = {
|
||||
.sensor_name = "ov2720",
|
||||
.pdata = &msm_camera_csi_device_data[1],
|
||||
.flash_data = &flash_ov2720,
|
||||
.sensor_platform_info = &sensor_board_info_ov2720,
|
||||
.csi_if = 1,
|
||||
.camera_type = FRONT_CAMERA_2D,
|
||||
.sensor_type = BAYER_SENSOR,
|
||||
};
|
||||
|
||||
static struct camera_vreg_t msm_8960_s5k3l1yx_vreg[] = {
|
||||
{"cam_vdig", REG_LDO, 1200000, 1200000, 105000},
|
||||
{"cam_vana", REG_LDO, 2800000, 2850000, 85600},
|
||||
{"cam_vio", REG_VS, 0, 0, 0},
|
||||
{"cam_vaf", REG_LDO, 2800000, 2800000, 300000},
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_flash_data flash_s5k3l1yx = {
|
||||
.flash_type = MSM_CAMERA_FLASH_NONE,
|
||||
};
|
||||
|
||||
static struct msm_camera_csi_lane_params s5k3l1yx_csi_lane_params = {
|
||||
.csi_lane_assign = 0xE4,
|
||||
.csi_lane_mask = 0xF,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_platform_info sensor_board_info_s5k3l1yx = {
|
||||
.mount_angle = 0,
|
||||
.cam_vreg = msm_8960_s5k3l1yx_vreg,
|
||||
.num_vreg = ARRAY_SIZE(msm_8960_s5k3l1yx_vreg),
|
||||
.gpio_conf = &msm_8960_back_cam_gpio_conf,
|
||||
.csi_lane_params = &s5k3l1yx_csi_lane_params,
|
||||
};
|
||||
|
||||
static struct msm_actuator_info msm_act_main_cam_2_info = {
|
||||
.board_info = &msm_act_main_cam_i2c_info,
|
||||
.cam_name = MSM_ACTUATOR_MAIN_CAM_2,
|
||||
.bus_id = MSM_8960_GSBI4_QUP_I2C_BUS_ID,
|
||||
.vcm_pwd = 0,
|
||||
.vcm_enable = 0,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_info msm_camera_sensor_s5k3l1yx_data = {
|
||||
.sensor_name = "s5k3l1yx",
|
||||
.pdata = &msm_camera_csi_device_data[0],
|
||||
.flash_data = &flash_s5k3l1yx,
|
||||
.sensor_platform_info = &sensor_board_info_s5k3l1yx,
|
||||
.csi_if = 1,
|
||||
.camera_type = BACK_CAMERA_2D,
|
||||
.sensor_type = BAYER_SENSOR,
|
||||
.actuator_info = &msm_act_main_cam_2_info,
|
||||
};
|
||||
|
||||
static struct msm_camera_csi_lane_params imx091_csi_lane_params = {
|
||||
.csi_lane_assign = 0xE4,
|
||||
.csi_lane_mask = 0xF,
|
||||
};
|
||||
|
||||
static struct camera_vreg_t msm_8960_imx091_vreg[] = {
|
||||
{"cam_vana", REG_LDO, 2800000, 2850000, 85600},
|
||||
{"cam_vaf", REG_LDO, 2800000, 2800000, 300000},
|
||||
{"cam_vdig", REG_LDO, 1200000, 1200000, 105000},
|
||||
{"cam_vio", REG_VS, 0, 0, 0},
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_flash_data flash_imx091 = {
|
||||
.flash_type = MSM_CAMERA_FLASH_LED,
|
||||
#ifdef CONFIG_MSM_CAMERA_FLASH
|
||||
.flash_src = &msm_flash_src
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_platform_info sensor_board_info_imx091 = {
|
||||
.mount_angle = 0,
|
||||
.cam_vreg = msm_8960_imx091_vreg,
|
||||
.num_vreg = ARRAY_SIZE(msm_8960_imx091_vreg),
|
||||
.gpio_conf = &msm_8960_back_cam_gpio_conf,
|
||||
.csi_lane_params = &imx091_csi_lane_params,
|
||||
};
|
||||
|
||||
static struct i2c_board_info imx091_eeprom_i2c_info = {
|
||||
I2C_BOARD_INFO("imx091_eeprom", 0x21),
|
||||
};
|
||||
|
||||
static struct msm_eeprom_info imx091_eeprom_info = {
|
||||
.board_info = &imx091_eeprom_i2c_info,
|
||||
.bus_id = MSM_8960_GSBI4_QUP_I2C_BUS_ID,
|
||||
};
|
||||
|
||||
static struct msm_camera_sensor_info msm_camera_sensor_imx091_data = {
|
||||
.sensor_name = "imx091",
|
||||
.pdata = &msm_camera_csi_device_data[0],
|
||||
.flash_data = &flash_imx091,
|
||||
.sensor_platform_info = &sensor_board_info_imx091,
|
||||
.csi_if = 1,
|
||||
.camera_type = BACK_CAMERA_2D,
|
||||
.sensor_type = BAYER_SENSOR,
|
||||
.actuator_info = &msm_act_main_cam_1_info,
|
||||
.eeprom_info = &imx091_eeprom_info,
|
||||
};
|
||||
|
||||
static struct pm8xxx_mpp_config_data privacy_light_on_config = {
|
||||
.type = PM8XXX_MPP_TYPE_SINK,
|
||||
.level = PM8XXX_MPP_CS_OUT_5MA,
|
||||
.control = PM8XXX_MPP_CS_CTRL_MPP_LOW_EN,
|
||||
};
|
||||
|
||||
static struct pm8xxx_mpp_config_data privacy_light_off_config = {
|
||||
.type = PM8XXX_MPP_TYPE_SINK,
|
||||
.level = PM8XXX_MPP_CS_OUT_5MA,
|
||||
.control = PM8XXX_MPP_CS_CTRL_DISABLE,
|
||||
};
|
||||
|
||||
static int32_t msm_camera_8960_ext_power_ctrl(int enable)
|
||||
{
|
||||
int rc = 0;
|
||||
if (enable) {
|
||||
rc = pm8xxx_mpp_config(PM8921_MPP_PM_TO_SYS(12),
|
||||
&privacy_light_on_config);
|
||||
} else {
|
||||
rc = pm8xxx_mpp_config(PM8921_MPP_PM_TO_SYS(12),
|
||||
&privacy_light_off_config);
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
|
||||
static struct platform_device msm_camera_server = {
|
||||
.name = "msm_cam_server",
|
||||
.id = 0,
|
||||
};
|
||||
|
||||
void __init msm8960_init_cam(void)
|
||||
{
|
||||
msm_gpiomux_install(msm8960_cam_common_configs,
|
||||
ARRAY_SIZE(msm8960_cam_common_configs));
|
||||
|
||||
if (machine_is_msm8960_cdp()) {
|
||||
msm_gpiomux_install(msm8960_cdp_flash_configs,
|
||||
ARRAY_SIZE(msm8960_cdp_flash_configs));
|
||||
msm_flash_src._fsrc.ext_driver_src.led_en =
|
||||
GPIO_CAM_GP_LED_EN1;
|
||||
msm_flash_src._fsrc.ext_driver_src.led_flash_en =
|
||||
GPIO_CAM_GP_LED_EN2;
|
||||
#if defined(CONFIG_I2C) && (defined(CONFIG_GPIO_SX150X) || \
|
||||
defined(CONFIG_GPIO_SX150X_MODULE))
|
||||
msm_flash_src._fsrc.ext_driver_src.expander_info =
|
||||
cam_expander_info;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (machine_is_msm8960_liquid()) {
|
||||
struct msm_camera_sensor_info *s_info;
|
||||
s_info = &msm_camera_sensor_imx074_data;
|
||||
s_info->sensor_platform_info->mount_angle = 180;
|
||||
s_info = &msm_camera_sensor_ov2720_data;
|
||||
s_info->sensor_platform_info->ext_power_ctrl =
|
||||
msm_camera_8960_ext_power_ctrl;
|
||||
}
|
||||
|
||||
if (machine_is_msm8960_fluid()) {
|
||||
msm_camera_sensor_imx091_data.sensor_platform_info->
|
||||
mount_angle = 270;
|
||||
}
|
||||
|
||||
platform_device_register(&msm_camera_server);
|
||||
platform_device_register(&msm8960_device_csiphy0);
|
||||
platform_device_register(&msm8960_device_csiphy1);
|
||||
platform_device_register(&msm8960_device_csiphy2);
|
||||
platform_device_register(&msm8960_device_csid0);
|
||||
platform_device_register(&msm8960_device_csid1);
|
||||
platform_device_register(&msm8960_device_csid2);
|
||||
platform_device_register(&msm8960_device_ispif);
|
||||
platform_device_register(&msm8960_device_vfe);
|
||||
platform_device_register(&msm8960_device_vpe);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_I2C
|
||||
static struct i2c_board_info msm8960_camera_i2c_boardinfo[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("imx074", 0x1A),
|
||||
.platform_data = &msm_camera_sensor_imx074_data,
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("ov2720", 0x6C),
|
||||
.platform_data = &msm_camera_sensor_ov2720_data,
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("mt9m114", 0x48),
|
||||
.platform_data = &msm_camera_sensor_mt9m114_data,
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("s5k3l1yx", 0x20),
|
||||
.platform_data = &msm_camera_sensor_s5k3l1yx_data,
|
||||
},
|
||||
#ifdef CONFIG_MSM_CAMERA_FLASH_SC628A
|
||||
{
|
||||
I2C_BOARD_INFO("sc628a", 0x6E),
|
||||
},
|
||||
#endif
|
||||
{
|
||||
I2C_BOARD_INFO("imx091", 0x34),
|
||||
.platform_data = &msm_camera_sensor_imx091_data,
|
||||
},
|
||||
};
|
||||
|
||||
struct msm_camera_board_info msm8960_camera_board_info = {
|
||||
.board_info = msm8960_camera_i2c_boardinfo,
|
||||
.num_i2c_board_info = ARRAY_SIZE(msm8960_camera_i2c_boardinfo),
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
1095
arch/arm/mach-msm/board-8960-display.c
Normal file
1095
arch/arm/mach-msm/board-8960-display.c
Normal file
File diff suppressed because it is too large
Load Diff
1004
arch/arm/mach-msm/board-8960-gpiomux.c
Normal file
1004
arch/arm/mach-msm/board-8960-gpiomux.c
Normal file
File diff suppressed because it is too large
Load Diff
624
arch/arm/mach-msm/board-8960-pmic.c
Normal file
624
arch/arm/mach-msm/board-8960-pmic.c
Normal file
@@ -0,0 +1,624 @@
|
||||
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mfd/pm8xxx/pm8921.h>
|
||||
#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/leds-pm8xxx.h>
|
||||
#include <linux/msm_ssbi.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <mach/msm_bus_board.h>
|
||||
#include <mach/restart.h>
|
||||
#include "devices.h"
|
||||
#include "board-8960.h"
|
||||
|
||||
struct pm8xxx_gpio_init {
|
||||
unsigned gpio;
|
||||
struct pm_gpio config;
|
||||
};
|
||||
|
||||
struct pm8xxx_mpp_init {
|
||||
unsigned mpp;
|
||||
struct pm8xxx_mpp_config_data config;
|
||||
};
|
||||
|
||||
#define PM8XXX_GPIO_INIT(_gpio, _dir, _buf, _val, _pull, _vin, _out_strength, \
|
||||
_func, _inv, _disable) \
|
||||
{ \
|
||||
.gpio = PM8921_GPIO_PM_TO_SYS(_gpio), \
|
||||
.config = { \
|
||||
.direction = _dir, \
|
||||
.output_buffer = _buf, \
|
||||
.output_value = _val, \
|
||||
.pull = _pull, \
|
||||
.vin_sel = _vin, \
|
||||
.out_strength = _out_strength, \
|
||||
.function = _func, \
|
||||
.inv_int_pol = _inv, \
|
||||
.disable_pin = _disable, \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PM8XXX_MPP_INIT(_mpp, _type, _level, _control) \
|
||||
{ \
|
||||
.mpp = PM8921_MPP_PM_TO_SYS(_mpp), \
|
||||
.config = { \
|
||||
.type = PM8XXX_MPP_TYPE_##_type, \
|
||||
.level = _level, \
|
||||
.control = PM8XXX_MPP_##_control, \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PM8XXX_GPIO_DISABLE(_gpio) \
|
||||
PM8XXX_GPIO_INIT(_gpio, PM_GPIO_DIR_IN, 0, 0, 0, PM_GPIO_VIN_S4, \
|
||||
0, 0, 0, 1)
|
||||
|
||||
#define PM8XXX_GPIO_OUTPUT(_gpio, _val) \
|
||||
PM8XXX_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT, PM_GPIO_OUT_BUF_CMOS, _val, \
|
||||
PM_GPIO_PULL_NO, PM_GPIO_VIN_S4, \
|
||||
PM_GPIO_STRENGTH_HIGH, \
|
||||
PM_GPIO_FUNC_NORMAL, 0, 0)
|
||||
|
||||
#define PM8XXX_GPIO_INPUT(_gpio, _pull) \
|
||||
PM8XXX_GPIO_INIT(_gpio, PM_GPIO_DIR_IN, PM_GPIO_OUT_BUF_CMOS, 0, \
|
||||
_pull, PM_GPIO_VIN_S4, \
|
||||
PM_GPIO_STRENGTH_NO, \
|
||||
PM_GPIO_FUNC_NORMAL, 0, 0)
|
||||
|
||||
#define PM8XXX_GPIO_OUTPUT_FUNC(_gpio, _val, _func) \
|
||||
PM8XXX_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT, PM_GPIO_OUT_BUF_CMOS, _val, \
|
||||
PM_GPIO_PULL_NO, PM_GPIO_VIN_S4, \
|
||||
PM_GPIO_STRENGTH_HIGH, \
|
||||
_func, 0, 0)
|
||||
|
||||
#define PM8XXX_GPIO_OUTPUT_VIN(_gpio, _val, _vin) \
|
||||
PM8XXX_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT, PM_GPIO_OUT_BUF_CMOS, _val, \
|
||||
PM_GPIO_PULL_NO, _vin, \
|
||||
PM_GPIO_STRENGTH_HIGH, \
|
||||
PM_GPIO_FUNC_NORMAL, 0, 0)
|
||||
|
||||
#define PM8XXX_GPIO_OUTPUT_STRENGTH(_gpio, _val, _out_strength) \
|
||||
PM8XXX_GPIO_INIT(_gpio, PM_GPIO_DIR_OUT, PM_GPIO_OUT_BUF_CMOS, _val, \
|
||||
PM_GPIO_PULL_NO, PM_GPIO_VIN_S4, \
|
||||
_out_strength, \
|
||||
PM_GPIO_FUNC_NORMAL, 0, 0)
|
||||
|
||||
/* Initial PM8921 GPIO configurations */
|
||||
static struct pm8xxx_gpio_init pm8921_gpios[] __initdata = {
|
||||
PM8XXX_GPIO_OUTPUT_VIN(6, 1, PM_GPIO_VIN_VPH), /* MHL power EN_N */
|
||||
PM8XXX_GPIO_DISABLE(7), /* Disable NFC */
|
||||
PM8XXX_GPIO_INPUT(16, PM_GPIO_PULL_UP_30), /* SD_CARD_WP */
|
||||
/* External regulator shared by display and touchscreen on LiQUID */
|
||||
PM8XXX_GPIO_OUTPUT(17, 0), /* DISP 3.3 V Boost */
|
||||
PM8XXX_GPIO_OUTPUT(18, 0), /* TABLA SPKR_LEFT_EN=off */
|
||||
PM8XXX_GPIO_OUTPUT(19, 0), /* TABLA SPKR_RIGHT_EN=off */
|
||||
PM8XXX_GPIO_DISABLE(22), /* Disable NFC */
|
||||
PM8XXX_GPIO_OUTPUT_FUNC(25, 0, PM_GPIO_FUNC_2), /* TN_CLK */
|
||||
PM8XXX_GPIO_INPUT(26, PM_GPIO_PULL_UP_30), /* SD_CARD_DET_N */
|
||||
PM8XXX_GPIO_OUTPUT(43, 1), /* DISP_RESET_N */
|
||||
PM8XXX_GPIO_OUTPUT(42, 0), /* USB 5V reg enable */
|
||||
/* TABLA CODEC RESET */
|
||||
PM8XXX_GPIO_OUTPUT_STRENGTH(34, 1, PM_GPIO_STRENGTH_MED)
|
||||
};
|
||||
|
||||
/* Initial PM8921 MPP configurations */
|
||||
static struct pm8xxx_mpp_init pm8921_mpps[] __initdata = {
|
||||
/* External 5V regulator enable; shared by HDMI and USB_OTG switches. */
|
||||
PM8XXX_MPP_INIT(7, D_INPUT, PM8921_MPP_DIG_LEVEL_VPH, DIN_TO_INT),
|
||||
PM8XXX_MPP_INIT(PM8XXX_AMUX_MPP_8, A_INPUT, PM8XXX_MPP_AIN_AMUX_CH8,
|
||||
DOUT_CTRL_LOW),
|
||||
};
|
||||
|
||||
void __init msm8960_pm8921_gpio_mpp_init(void)
|
||||
{
|
||||
int i, rc;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pm8921_gpios); i++) {
|
||||
rc = pm8xxx_gpio_config(pm8921_gpios[i].gpio,
|
||||
&pm8921_gpios[i].config);
|
||||
if (rc) {
|
||||
pr_err("%s: pm8xxx_gpio_config: rc=%d\n", __func__, rc);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pm8921_mpps); i++) {
|
||||
rc = pm8xxx_mpp_config(pm8921_mpps[i].mpp,
|
||||
&pm8921_mpps[i].config);
|
||||
if (rc) {
|
||||
pr_err("%s: pm8xxx_mpp_config: rc=%d\n", __func__, rc);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static struct pm8xxx_adc_amux pm8xxx_adc_channels_data[] = {
|
||||
{"vcoin", CHANNEL_VCOIN, CHAN_PATH_SCALING2, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"vbat", CHANNEL_VBAT, CHAN_PATH_SCALING2, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"dcin", CHANNEL_DCIN, CHAN_PATH_SCALING4, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"ichg", CHANNEL_ICHG, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"vph_pwr", CHANNEL_VPH_PWR, CHAN_PATH_SCALING2, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"ibat", CHANNEL_IBAT, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"batt_therm", CHANNEL_BATT_THERM, CHAN_PATH_SCALING1, AMUX_RSV2,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_BATT_THERM},
|
||||
{"batt_id", CHANNEL_BATT_ID, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"usbin", CHANNEL_USBIN, CHAN_PATH_SCALING3, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"pmic_therm", CHANNEL_DIE_TEMP, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_PMIC_THERM},
|
||||
{"625mv", CHANNEL_625MV, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"125v", CHANNEL_125V, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"chg_temp", CHANNEL_CHG_TEMP, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
|
||||
{"pa_therm1", ADC_MPP_1_AMUX8, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_PA_THERM},
|
||||
{"xo_therm", CHANNEL_MUXOFF, CHAN_PATH_SCALING1, AMUX_RSV0,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_XOTHERM},
|
||||
{"pa_therm0", ADC_MPP_1_AMUX3, CHAN_PATH_SCALING1, AMUX_RSV1,
|
||||
ADC_DECIMATION_TYPE2, ADC_SCALE_PA_THERM},
|
||||
};
|
||||
|
||||
static struct pm8xxx_adc_properties pm8xxx_adc_data = {
|
||||
.adc_vdd_reference = 1800, /* milli-voltage for this adc */
|
||||
.bitresolution = 15,
|
||||
.bipolar = 0,
|
||||
};
|
||||
|
||||
static struct pm8xxx_adc_platform_data pm8xxx_adc_pdata = {
|
||||
.adc_channel = pm8xxx_adc_channels_data,
|
||||
.adc_num_board_channel = ARRAY_SIZE(pm8xxx_adc_channels_data),
|
||||
.adc_prop = &pm8xxx_adc_data,
|
||||
.adc_mpp_base = PM8921_MPP_PM_TO_SYS(1),
|
||||
};
|
||||
|
||||
static struct pm8xxx_irq_platform_data pm8xxx_irq_pdata __devinitdata = {
|
||||
.irq_base = PM8921_IRQ_BASE,
|
||||
.devirq = MSM_GPIO_TO_INT(104),
|
||||
.irq_trigger_flag = IRQF_TRIGGER_LOW,
|
||||
};
|
||||
|
||||
static struct pm8xxx_gpio_platform_data pm8xxx_gpio_pdata __devinitdata = {
|
||||
.gpio_base = PM8921_GPIO_PM_TO_SYS(1),
|
||||
};
|
||||
|
||||
static struct pm8xxx_mpp_platform_data pm8xxx_mpp_pdata __devinitdata = {
|
||||
.mpp_base = PM8921_MPP_PM_TO_SYS(1),
|
||||
};
|
||||
|
||||
static struct pm8xxx_rtc_platform_data pm8xxx_rtc_pdata __devinitdata = {
|
||||
.rtc_write_enable = false,
|
||||
.rtc_alarm_powerup = false,
|
||||
};
|
||||
|
||||
static struct pm8xxx_pwrkey_platform_data pm8xxx_pwrkey_pdata = {
|
||||
.pull_up = 1,
|
||||
.kpd_trigger_delay_us = 15625,
|
||||
.wakeup = 1,
|
||||
};
|
||||
|
||||
/* Rotate lock key is not available so use F1 */
|
||||
#define KEY_ROTATE_LOCK KEY_F1
|
||||
|
||||
static const unsigned int keymap_liquid[] = {
|
||||
KEY(0, 0, KEY_VOLUMEUP),
|
||||
KEY(0, 1, KEY_VOLUMEDOWN),
|
||||
KEY(1, 3, KEY_ROTATE_LOCK),
|
||||
KEY(1, 4, KEY_HOME),
|
||||
};
|
||||
|
||||
static struct matrix_keymap_data keymap_data_liquid = {
|
||||
.keymap_size = ARRAY_SIZE(keymap_liquid),
|
||||
.keymap = keymap_liquid,
|
||||
};
|
||||
|
||||
static struct pm8xxx_keypad_platform_data keypad_data_liquid = {
|
||||
.input_name = "keypad_8960_liquid",
|
||||
.input_phys_device = "keypad_8960/input0",
|
||||
.num_rows = 2,
|
||||
.num_cols = 5,
|
||||
.rows_gpio_start = PM8921_GPIO_PM_TO_SYS(9),
|
||||
.cols_gpio_start = PM8921_GPIO_PM_TO_SYS(1),
|
||||
.debounce_ms = 15,
|
||||
.scan_delay_ms = 32,
|
||||
.row_hold_ns = 91500,
|
||||
.wakeup = 1,
|
||||
.keymap_data = &keymap_data_liquid,
|
||||
};
|
||||
|
||||
|
||||
static const unsigned int keymap[] = {
|
||||
KEY(0, 0, KEY_VOLUMEUP),
|
||||
KEY(0, 1, KEY_VOLUMEDOWN),
|
||||
KEY(0, 2, KEY_CAMERA_SNAPSHOT),
|
||||
KEY(0, 3, KEY_CAMERA_FOCUS),
|
||||
};
|
||||
|
||||
static struct matrix_keymap_data keymap_data = {
|
||||
.keymap_size = ARRAY_SIZE(keymap),
|
||||
.keymap = keymap,
|
||||
};
|
||||
|
||||
static struct pm8xxx_keypad_platform_data keypad_data = {
|
||||
.input_name = "keypad_8960",
|
||||
.input_phys_device = "keypad_8960/input0",
|
||||
.num_rows = 1,
|
||||
.num_cols = 5,
|
||||
.rows_gpio_start = PM8921_GPIO_PM_TO_SYS(9),
|
||||
.cols_gpio_start = PM8921_GPIO_PM_TO_SYS(1),
|
||||
.debounce_ms = 15,
|
||||
.scan_delay_ms = 32,
|
||||
.row_hold_ns = 91500,
|
||||
.wakeup = 1,
|
||||
.keymap_data = &keymap_data,
|
||||
};
|
||||
|
||||
static const unsigned int keymap_sim[] = {
|
||||
KEY(0, 0, KEY_7),
|
||||
KEY(0, 1, KEY_DOWN),
|
||||
KEY(0, 2, KEY_UP),
|
||||
KEY(0, 3, KEY_RIGHT),
|
||||
KEY(0, 4, KEY_ENTER),
|
||||
KEY(0, 5, KEY_L),
|
||||
KEY(0, 6, KEY_BACK),
|
||||
KEY(0, 7, KEY_M),
|
||||
|
||||
KEY(1, 0, KEY_LEFT),
|
||||
KEY(1, 1, KEY_SEND),
|
||||
KEY(1, 2, KEY_1),
|
||||
KEY(1, 3, KEY_4),
|
||||
KEY(1, 4, KEY_CLEAR),
|
||||
KEY(1, 5, KEY_MSDOS),
|
||||
KEY(1, 6, KEY_SPACE),
|
||||
KEY(1, 7, KEY_COMMA),
|
||||
|
||||
KEY(2, 0, KEY_6),
|
||||
KEY(2, 1, KEY_5),
|
||||
KEY(2, 2, KEY_8),
|
||||
KEY(2, 3, KEY_3),
|
||||
KEY(2, 4, KEY_NUMERIC_STAR),
|
||||
KEY(2, 5, KEY_UP),
|
||||
KEY(2, 6, KEY_DOWN),
|
||||
KEY(2, 7, KEY_LEFTSHIFT),
|
||||
|
||||
KEY(3, 0, KEY_9),
|
||||
KEY(3, 1, KEY_NUMERIC_POUND),
|
||||
KEY(3, 2, KEY_0),
|
||||
KEY(3, 3, KEY_2),
|
||||
KEY(3, 4, KEY_SLEEP),
|
||||
KEY(3, 5, KEY_F1),
|
||||
KEY(3, 6, KEY_F2),
|
||||
KEY(3, 7, KEY_F3),
|
||||
|
||||
KEY(4, 0, KEY_BACK),
|
||||
KEY(4, 1, KEY_HOME),
|
||||
KEY(4, 2, KEY_MENU),
|
||||
KEY(4, 3, KEY_VOLUMEUP),
|
||||
KEY(4, 4, KEY_VOLUMEDOWN),
|
||||
KEY(4, 5, KEY_F4),
|
||||
KEY(4, 6, KEY_F5),
|
||||
KEY(4, 7, KEY_F6),
|
||||
|
||||
KEY(5, 0, KEY_R),
|
||||
KEY(5, 1, KEY_T),
|
||||
KEY(5, 2, KEY_Y),
|
||||
KEY(5, 3, KEY_LEFTALT),
|
||||
KEY(5, 4, KEY_KPENTER),
|
||||
KEY(5, 5, KEY_Q),
|
||||
KEY(5, 6, KEY_W),
|
||||
KEY(5, 7, KEY_E),
|
||||
|
||||
KEY(6, 0, KEY_F),
|
||||
KEY(6, 1, KEY_G),
|
||||
KEY(6, 2, KEY_H),
|
||||
KEY(6, 3, KEY_CAPSLOCK),
|
||||
KEY(6, 4, KEY_PAGEUP),
|
||||
KEY(6, 5, KEY_A),
|
||||
KEY(6, 6, KEY_S),
|
||||
KEY(6, 7, KEY_D),
|
||||
|
||||
KEY(7, 0, KEY_V),
|
||||
KEY(7, 1, KEY_B),
|
||||
KEY(7, 2, KEY_N),
|
||||
KEY(7, 3, KEY_MENU),
|
||||
KEY(7, 4, KEY_PAGEDOWN),
|
||||
KEY(7, 5, KEY_Z),
|
||||
KEY(7, 6, KEY_X),
|
||||
KEY(7, 7, KEY_C),
|
||||
|
||||
KEY(8, 0, KEY_P),
|
||||
KEY(8, 1, KEY_J),
|
||||
KEY(8, 2, KEY_K),
|
||||
KEY(8, 3, KEY_INSERT),
|
||||
KEY(8, 4, KEY_LINEFEED),
|
||||
KEY(8, 5, KEY_U),
|
||||
KEY(8, 6, KEY_I),
|
||||
KEY(8, 7, KEY_O),
|
||||
|
||||
KEY(9, 0, KEY_4),
|
||||
KEY(9, 1, KEY_5),
|
||||
KEY(9, 2, KEY_6),
|
||||
KEY(9, 3, KEY_7),
|
||||
KEY(9, 4, KEY_8),
|
||||
KEY(9, 5, KEY_1),
|
||||
KEY(9, 6, KEY_2),
|
||||
KEY(9, 7, KEY_3),
|
||||
|
||||
KEY(10, 0, KEY_F7),
|
||||
KEY(10, 1, KEY_F8),
|
||||
KEY(10, 2, KEY_F9),
|
||||
KEY(10, 3, KEY_F10),
|
||||
KEY(10, 4, KEY_FN),
|
||||
KEY(10, 5, KEY_9),
|
||||
KEY(10, 6, KEY_0),
|
||||
KEY(10, 7, KEY_DOT),
|
||||
|
||||
KEY(11, 0, KEY_LEFTCTRL),
|
||||
KEY(11, 1, KEY_F11),
|
||||
KEY(11, 2, KEY_ENTER),
|
||||
KEY(11, 3, KEY_SEARCH),
|
||||
KEY(11, 4, KEY_DELETE),
|
||||
KEY(11, 5, KEY_RIGHT),
|
||||
KEY(11, 6, KEY_LEFT),
|
||||
KEY(11, 7, KEY_RIGHTSHIFT),
|
||||
KEY(0, 0, KEY_VOLUMEUP),
|
||||
KEY(0, 1, KEY_VOLUMEDOWN),
|
||||
KEY(0, 2, KEY_CAMERA_SNAPSHOT),
|
||||
KEY(0, 3, KEY_CAMERA_FOCUS),
|
||||
};
|
||||
|
||||
static struct matrix_keymap_data keymap_data_sim = {
|
||||
.keymap_size = ARRAY_SIZE(keymap_sim),
|
||||
.keymap = keymap_sim,
|
||||
};
|
||||
|
||||
static struct pm8xxx_keypad_platform_data keypad_data_sim = {
|
||||
.input_name = "keypad_8960",
|
||||
.input_phys_device = "keypad_8960/input0",
|
||||
.num_rows = 12,
|
||||
.num_cols = 8,
|
||||
.rows_gpio_start = PM8921_GPIO_PM_TO_SYS(9),
|
||||
.cols_gpio_start = PM8921_GPIO_PM_TO_SYS(1),
|
||||
.debounce_ms = 15,
|
||||
.scan_delay_ms = 32,
|
||||
.row_hold_ns = 91500,
|
||||
.wakeup = 1,
|
||||
.keymap_data = &keymap_data_sim,
|
||||
};
|
||||
|
||||
static int pm8921_therm_mitigation[] = {
|
||||
1100,
|
||||
700,
|
||||
600,
|
||||
325,
|
||||
};
|
||||
|
||||
#define MAX_VOLTAGE_MV 4200
|
||||
static struct pm8921_charger_platform_data pm8921_chg_pdata __devinitdata = {
|
||||
.safety_time = 180,
|
||||
.update_time = 60000,
|
||||
.max_voltage = MAX_VOLTAGE_MV,
|
||||
.min_voltage = 3200,
|
||||
.resume_voltage_delta = 100,
|
||||
.term_current = 100,
|
||||
.cool_temp = 10,
|
||||
.warm_temp = 40,
|
||||
.temp_check_period = 1,
|
||||
.max_bat_chg_current = 1100,
|
||||
.cool_bat_chg_current = 350,
|
||||
.warm_bat_chg_current = 350,
|
||||
.cool_bat_voltage = 4100,
|
||||
.warm_bat_voltage = 4100,
|
||||
.thermal_mitigation = pm8921_therm_mitigation,
|
||||
.thermal_levels = ARRAY_SIZE(pm8921_therm_mitigation),
|
||||
.rconn_mohm = 18,
|
||||
};
|
||||
|
||||
static struct pm8xxx_misc_platform_data pm8xxx_misc_pdata = {
|
||||
.priority = 0,
|
||||
};
|
||||
|
||||
static struct pm8921_bms_platform_data pm8921_bms_pdata __devinitdata = {
|
||||
.battery_type = BATT_UNKNOWN,
|
||||
.r_sense = 10,
|
||||
.i_test = 2500,
|
||||
.v_failure = 3000,
|
||||
.calib_delay_ms = 600000,
|
||||
.max_voltage_uv = MAX_VOLTAGE_MV * 1000,
|
||||
.rconn_mohm = 30,
|
||||
};
|
||||
|
||||
#define PM8921_LC_LED_MAX_CURRENT 4 /* I = 4mA */
|
||||
#define PM8921_LC_LED_LOW_CURRENT 1 /* I = 1mA */
|
||||
#define PM8XXX_LED_PWM_PERIOD 1000
|
||||
#define PM8XXX_LED_PWM_DUTY_MS 20
|
||||
/**
|
||||
* PM8XXX_PWM_CHANNEL_NONE shall be used when LED shall not be
|
||||
* driven using PWM feature.
|
||||
*/
|
||||
#define PM8XXX_PWM_CHANNEL_NONE -1
|
||||
|
||||
static struct led_info pm8921_led_info_liquid[] = {
|
||||
{
|
||||
.name = "led:red",
|
||||
.flags = PM8XXX_ID_LED_0,
|
||||
.default_trigger = "battery-charging",
|
||||
},
|
||||
{
|
||||
.name = "led:green",
|
||||
.flags = PM8XXX_ID_LED_0,
|
||||
.default_trigger = "battery-full",
|
||||
},
|
||||
{
|
||||
.name = "led:blue",
|
||||
.flags = PM8XXX_ID_LED_2,
|
||||
.default_trigger = "notification",
|
||||
},
|
||||
};
|
||||
|
||||
static struct pm8xxx_led_config pm8921_led_configs_liquid[] = {
|
||||
[0] = {
|
||||
.id = PM8XXX_ID_LED_0,
|
||||
.mode = PM8XXX_LED_MODE_MANUAL,
|
||||
.max_current = PM8921_LC_LED_MAX_CURRENT,
|
||||
},
|
||||
[1] = {
|
||||
.id = PM8XXX_ID_LED_1,
|
||||
.mode = PM8XXX_LED_MODE_MANUAL,
|
||||
.max_current = PM8921_LC_LED_LOW_CURRENT,
|
||||
},
|
||||
[2] = {
|
||||
.id = PM8XXX_ID_LED_2,
|
||||
.mode = PM8XXX_LED_MODE_MANUAL,
|
||||
.max_current = PM8921_LC_LED_MAX_CURRENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct led_platform_data pm8xxx_leds_core_liquid = {
|
||||
.num_leds = ARRAY_SIZE(pm8921_led_info_liquid),
|
||||
.leds = pm8921_led_info_liquid,
|
||||
};
|
||||
|
||||
static struct pm8xxx_led_platform_data pm8xxx_leds_pdata_liquid = {
|
||||
.led_core = &pm8xxx_leds_core_liquid,
|
||||
.configs = pm8921_led_configs_liquid,
|
||||
.num_configs = ARRAY_SIZE(pm8921_led_configs_liquid),
|
||||
};
|
||||
|
||||
static struct led_info pm8921_led_info[] = {
|
||||
[0] = {
|
||||
.name = "led:battery_charging",
|
||||
.default_trigger = "battery-charging",
|
||||
},
|
||||
[1] = {
|
||||
.name = "led:battery_full",
|
||||
.default_trigger = "battery-full",
|
||||
},
|
||||
};
|
||||
|
||||
static struct led_platform_data pm8921_led_core_pdata = {
|
||||
.num_leds = ARRAY_SIZE(pm8921_led_info),
|
||||
.leds = pm8921_led_info,
|
||||
};
|
||||
|
||||
static int pm8921_led0_pwm_duty_pcts[56] = {
|
||||
1, 4, 8, 12, 16, 20, 24, 28, 32, 36,
|
||||
40, 44, 46, 52, 56, 60, 64, 68, 72, 76,
|
||||
80, 84, 88, 92, 96, 100, 100, 100, 98, 95,
|
||||
92, 88, 84, 82, 78, 74, 70, 66, 62, 58,
|
||||
58, 54, 50, 48, 42, 38, 34, 30, 26, 22,
|
||||
14, 10, 6, 4, 1
|
||||
};
|
||||
|
||||
static struct pm8xxx_pwm_duty_cycles pm8921_led0_pwm_duty_cycles = {
|
||||
.duty_pcts = (int *)&pm8921_led0_pwm_duty_pcts,
|
||||
.num_duty_pcts = ARRAY_SIZE(pm8921_led0_pwm_duty_pcts),
|
||||
.duty_ms = PM8XXX_LED_PWM_DUTY_MS,
|
||||
.start_idx = 0,
|
||||
};
|
||||
|
||||
static struct pm8xxx_led_config pm8921_led_configs[] = {
|
||||
[0] = {
|
||||
.id = PM8XXX_ID_LED_0,
|
||||
.mode = PM8XXX_LED_MODE_PWM2,
|
||||
.max_current = PM8921_LC_LED_MAX_CURRENT,
|
||||
.pwm_channel = 5,
|
||||
.pwm_period_us = PM8XXX_LED_PWM_PERIOD,
|
||||
.pwm_duty_cycles = &pm8921_led0_pwm_duty_cycles,
|
||||
},
|
||||
[1] = {
|
||||
.id = PM8XXX_ID_LED_1,
|
||||
.mode = PM8XXX_LED_MODE_PWM1,
|
||||
.max_current = PM8921_LC_LED_MAX_CURRENT,
|
||||
.pwm_channel = 4,
|
||||
.pwm_period_us = PM8XXX_LED_PWM_PERIOD,
|
||||
},
|
||||
};
|
||||
|
||||
static struct pm8xxx_led_platform_data pm8xxx_leds_pdata = {
|
||||
.led_core = &pm8921_led_core_pdata,
|
||||
.configs = pm8921_led_configs,
|
||||
.num_configs = ARRAY_SIZE(pm8921_led_configs),
|
||||
};
|
||||
|
||||
static struct pm8xxx_ccadc_platform_data pm8xxx_ccadc_pdata = {
|
||||
.r_sense = 10,
|
||||
};
|
||||
|
||||
/**
|
||||
* PM8XXX_PWM_DTEST_CHANNEL_NONE shall be used when no LPG
|
||||
* channel should be in DTEST mode.
|
||||
*/
|
||||
|
||||
#define PM8XXX_PWM_DTEST_CHANNEL_NONE (-1)
|
||||
|
||||
static struct pm8xxx_pwm_platform_data pm8xxx_pwm_pdata = {
|
||||
.dtest_channel = PM8XXX_PWM_DTEST_CHANNEL_NONE,
|
||||
};
|
||||
|
||||
static struct pm8921_platform_data pm8921_platform_data __devinitdata = {
|
||||
.irq_pdata = &pm8xxx_irq_pdata,
|
||||
.gpio_pdata = &pm8xxx_gpio_pdata,
|
||||
.mpp_pdata = &pm8xxx_mpp_pdata,
|
||||
.rtc_pdata = &pm8xxx_rtc_pdata,
|
||||
.pwrkey_pdata = &pm8xxx_pwrkey_pdata,
|
||||
.keypad_pdata = &keypad_data,
|
||||
.misc_pdata = &pm8xxx_misc_pdata,
|
||||
.regulator_pdatas = msm_pm8921_regulator_pdata,
|
||||
.charger_pdata = &pm8921_chg_pdata,
|
||||
.bms_pdata = &pm8921_bms_pdata,
|
||||
.adc_pdata = &pm8xxx_adc_pdata,
|
||||
.leds_pdata = &pm8xxx_leds_pdata,
|
||||
.ccadc_pdata = &pm8xxx_ccadc_pdata,
|
||||
.pwm_pdata = &pm8xxx_pwm_pdata,
|
||||
};
|
||||
|
||||
static struct msm_ssbi_platform_data msm8960_ssbi_pm8921_pdata __devinitdata = {
|
||||
.controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
|
||||
.slave = {
|
||||
.name = "pm8921-core",
|
||||
.platform_data = &pm8921_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
void __init msm8960_init_pmic(void)
|
||||
{
|
||||
pmic_reset_irq = PM8921_IRQ_BASE + PM8921_RESOUT_IRQ;
|
||||
msm8960_device_ssbi_pmic.dev.platform_data =
|
||||
&msm8960_ssbi_pm8921_pdata;
|
||||
pm8921_platform_data.num_regulators = msm_pm8921_regulator_pdata_len;
|
||||
|
||||
/* Simulator supports a QWERTY keypad */
|
||||
if (machine_is_msm8960_sim())
|
||||
pm8921_platform_data.keypad_pdata = &keypad_data_sim;
|
||||
|
||||
if (machine_is_msm8960_liquid()) {
|
||||
pm8921_platform_data.keypad_pdata = &keypad_data_liquid;
|
||||
pm8921_platform_data.leds_pdata = &pm8xxx_leds_pdata_liquid;
|
||||
pm8921_platform_data.bms_pdata->battery_type = BATT_DESAY;
|
||||
} else if (machine_is_msm8960_mtp()) {
|
||||
pm8921_platform_data.bms_pdata->battery_type = BATT_PALLADIUM;
|
||||
}
|
||||
|
||||
if (machine_is_msm8960_fluid())
|
||||
pm8921_bms_pdata.rconn_mohm = 20;
|
||||
}
|
||||
570
arch/arm/mach-msm/board-8960-regulator.c
Normal file
570
arch/arm/mach-msm/board-8960-regulator.c
Normal file
@@ -0,0 +1,570 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/regulator/pm8xxx-regulator.h>
|
||||
#include <linux/regulator/msm-gpio-regulator.h>
|
||||
#include <mach/rpm-regulator.h>
|
||||
|
||||
#include "board-8960.h"
|
||||
|
||||
#define VREG_CONSUMERS(_id) \
|
||||
static struct regulator_consumer_supply vreg_consumers_##_id[]
|
||||
|
||||
/*
|
||||
* Consumer specific regulator names:
|
||||
* regulator name consumer dev_name
|
||||
*/
|
||||
VREG_CONSUMERS(L1) = {
|
||||
REGULATOR_SUPPLY("8921_l1", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L2) = {
|
||||
REGULATOR_SUPPLY("8921_l2", NULL),
|
||||
REGULATOR_SUPPLY("dsi_vdda", "mipi_dsi.1"),
|
||||
REGULATOR_SUPPLY("mipi_csi_vdd", "msm_csid.0"),
|
||||
REGULATOR_SUPPLY("mipi_csi_vdd", "msm_csid.1"),
|
||||
REGULATOR_SUPPLY("mipi_csi_vdd", "msm_csid.2"),
|
||||
};
|
||||
VREG_CONSUMERS(L3) = {
|
||||
REGULATOR_SUPPLY("8921_l3", NULL),
|
||||
REGULATOR_SUPPLY("HSUSB_3p3", "msm_otg"),
|
||||
};
|
||||
VREG_CONSUMERS(L4) = {
|
||||
REGULATOR_SUPPLY("8921_l4", NULL),
|
||||
REGULATOR_SUPPLY("HSUSB_1p8", "msm_otg"),
|
||||
REGULATOR_SUPPLY("iris_vddxo", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(L5) = {
|
||||
REGULATOR_SUPPLY("8921_l5", NULL),
|
||||
REGULATOR_SUPPLY("sdc_vdd", "msm_sdcc.1"),
|
||||
};
|
||||
VREG_CONSUMERS(L6) = {
|
||||
REGULATOR_SUPPLY("8921_l6", NULL),
|
||||
REGULATOR_SUPPLY("sdc_vdd", "msm_sdcc.3"),
|
||||
};
|
||||
VREG_CONSUMERS(L7) = {
|
||||
REGULATOR_SUPPLY("8921_l7", NULL),
|
||||
REGULATOR_SUPPLY("sdc_vdd_io", "msm_sdcc.3"),
|
||||
};
|
||||
VREG_CONSUMERS(L8) = {
|
||||
REGULATOR_SUPPLY("8921_l8", NULL),
|
||||
REGULATOR_SUPPLY("dsi_vdc", "mipi_dsi.1"),
|
||||
};
|
||||
VREG_CONSUMERS(L9) = {
|
||||
REGULATOR_SUPPLY("8921_l9", NULL),
|
||||
REGULATOR_SUPPLY("vdd", "3-0024"),
|
||||
REGULATOR_SUPPLY("vdd_ana", "3-004a"),
|
||||
};
|
||||
VREG_CONSUMERS(L10) = {
|
||||
REGULATOR_SUPPLY("8921_l10", NULL),
|
||||
REGULATOR_SUPPLY("iris_vddpa", "wcnss_wlan.0"),
|
||||
|
||||
};
|
||||
VREG_CONSUMERS(L11) = {
|
||||
REGULATOR_SUPPLY("8921_l11", NULL),
|
||||
REGULATOR_SUPPLY("cam_vana", "4-001a"),
|
||||
REGULATOR_SUPPLY("cam_vana", "4-006c"),
|
||||
REGULATOR_SUPPLY("cam_vana", "4-0048"),
|
||||
REGULATOR_SUPPLY("cam_vana", "4-0020"),
|
||||
REGULATOR_SUPPLY("cam_vana", "4-0034"),
|
||||
};
|
||||
VREG_CONSUMERS(L12) = {
|
||||
REGULATOR_SUPPLY("8921_l12", NULL),
|
||||
REGULATOR_SUPPLY("cam_vdig", "4-001a"),
|
||||
REGULATOR_SUPPLY("cam_vdig", "4-006c"),
|
||||
REGULATOR_SUPPLY("cam_vdig", "4-0048"),
|
||||
REGULATOR_SUPPLY("cam_vdig", "4-0020"),
|
||||
REGULATOR_SUPPLY("cam_vdig", "4-0034"),
|
||||
};
|
||||
VREG_CONSUMERS(L14) = {
|
||||
REGULATOR_SUPPLY("8921_l14", NULL),
|
||||
REGULATOR_SUPPLY("pa_therm", "pm8xxx-adc"),
|
||||
};
|
||||
VREG_CONSUMERS(L15) = {
|
||||
REGULATOR_SUPPLY("8921_l15", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L16) = {
|
||||
REGULATOR_SUPPLY("8921_l16", NULL),
|
||||
REGULATOR_SUPPLY("cam_vaf", "4-001a"),
|
||||
REGULATOR_SUPPLY("cam_vaf", "4-006c"),
|
||||
REGULATOR_SUPPLY("cam_vaf", "4-0048"),
|
||||
REGULATOR_SUPPLY("cam_vaf", "4-0020"),
|
||||
REGULATOR_SUPPLY("cam_vaf", "4-0034"),
|
||||
};
|
||||
VREG_CONSUMERS(L17) = {
|
||||
REGULATOR_SUPPLY("8921_l17", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L18) = {
|
||||
REGULATOR_SUPPLY("8921_l18", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L21) = {
|
||||
REGULATOR_SUPPLY("8921_l21", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L22) = {
|
||||
REGULATOR_SUPPLY("8921_l22", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(L23) = {
|
||||
REGULATOR_SUPPLY("8921_l23", NULL),
|
||||
REGULATOR_SUPPLY("dsi_vddio", "mipi_dsi.1"),
|
||||
REGULATOR_SUPPLY("hdmi_avdd", "hdmi_msm.0"),
|
||||
REGULATOR_SUPPLY("pll_vdd", "pil_riva"),
|
||||
REGULATOR_SUPPLY("pll_vdd", "pil_qdsp6v4.1"),
|
||||
REGULATOR_SUPPLY("pll_vdd", "pil_qdsp6v4.2"),
|
||||
};
|
||||
VREG_CONSUMERS(L24) = {
|
||||
REGULATOR_SUPPLY("8921_l24", NULL),
|
||||
REGULATOR_SUPPLY("riva_vddmx", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(L25) = {
|
||||
REGULATOR_SUPPLY("8921_l25", NULL),
|
||||
REGULATOR_SUPPLY("VDDD_CDC_D", "tabla-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_A_1P2V", "tabla-slim"),
|
||||
REGULATOR_SUPPLY("VDDD_CDC_D", "tabla2x-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_A_1P2V", "tabla2x-slim"),
|
||||
};
|
||||
VREG_CONSUMERS(L26) = {
|
||||
REGULATOR_SUPPLY("8921_l26", NULL),
|
||||
REGULATOR_SUPPLY("core_vdd", "pil_qdsp6v4.0"),
|
||||
};
|
||||
VREG_CONSUMERS(L27) = {
|
||||
REGULATOR_SUPPLY("8921_l27", NULL),
|
||||
REGULATOR_SUPPLY("core_vdd", "pil_qdsp6v4.2"),
|
||||
};
|
||||
VREG_CONSUMERS(L28) = {
|
||||
REGULATOR_SUPPLY("8921_l28", NULL),
|
||||
REGULATOR_SUPPLY("core_vdd", "pil_qdsp6v4.1"),
|
||||
};
|
||||
VREG_CONSUMERS(L29) = {
|
||||
REGULATOR_SUPPLY("8921_l29", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(S1) = {
|
||||
REGULATOR_SUPPLY("8921_s1", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(S2) = {
|
||||
REGULATOR_SUPPLY("8921_s2", NULL),
|
||||
REGULATOR_SUPPLY("iris_vddrfa", "wcnss_wlan.0"),
|
||||
|
||||
};
|
||||
VREG_CONSUMERS(S3) = {
|
||||
REGULATOR_SUPPLY("8921_s3", NULL),
|
||||
REGULATOR_SUPPLY("HSUSB_VDDCX", "msm_otg"),
|
||||
REGULATOR_SUPPLY("riva_vddcx", "wcnss_wlan.0"),
|
||||
REGULATOR_SUPPLY("HSIC_VDDCX", "msm_hsic_host"),
|
||||
};
|
||||
VREG_CONSUMERS(S4) = {
|
||||
REGULATOR_SUPPLY("8921_s4", NULL),
|
||||
REGULATOR_SUPPLY("sdc_vdd_io", "msm_sdcc.1"),
|
||||
REGULATOR_SUPPLY("sdc_vdd", "msm_sdcc.2"),
|
||||
REGULATOR_SUPPLY("sdc_vdd_io", "msm_sdcc.4"),
|
||||
REGULATOR_SUPPLY("riva_vddpx", "wcnss_wlan.0"),
|
||||
REGULATOR_SUPPLY("hdmi_vcc", "hdmi_msm.0"),
|
||||
REGULATOR_SUPPLY("VDDIO_CDC", "tabla-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDD_CP", "tabla-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_TX", "tabla-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_RX", "tabla-slim"),
|
||||
REGULATOR_SUPPLY("VDDIO_CDC", "tabla2x-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDD_CP", "tabla2x-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_TX", "tabla2x-slim"),
|
||||
REGULATOR_SUPPLY("CDC_VDDA_RX", "tabla2x-slim"),
|
||||
REGULATOR_SUPPLY("vcc_i2c", "3-005b"),
|
||||
REGULATOR_SUPPLY("EXT_HUB_VDDIO", "msm_smsc_hub"),
|
||||
REGULATOR_SUPPLY("vcc_i2c", "10-0048"),
|
||||
};
|
||||
VREG_CONSUMERS(S5) = {
|
||||
REGULATOR_SUPPLY("8921_s5", NULL),
|
||||
REGULATOR_SUPPLY("krait0", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(S6) = {
|
||||
REGULATOR_SUPPLY("8921_s6", NULL),
|
||||
REGULATOR_SUPPLY("krait1", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(S7) = {
|
||||
REGULATOR_SUPPLY("8921_s7", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(S8) = {
|
||||
REGULATOR_SUPPLY("8921_s8", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(LVS1) = {
|
||||
REGULATOR_SUPPLY("8921_lvs1", NULL),
|
||||
REGULATOR_SUPPLY("iris_vddio", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(LVS2) = {
|
||||
REGULATOR_SUPPLY("8921_lvs2", NULL),
|
||||
REGULATOR_SUPPLY("iris_vdddig", "wcnss_wlan.0"),
|
||||
};
|
||||
VREG_CONSUMERS(LVS3) = {
|
||||
REGULATOR_SUPPLY("8921_lvs3", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(LVS4) = {
|
||||
REGULATOR_SUPPLY("8921_lvs4", NULL),
|
||||
REGULATOR_SUPPLY("vcc_i2c", "3-0024"),
|
||||
REGULATOR_SUPPLY("vcc_i2c", "3-004a"),
|
||||
};
|
||||
VREG_CONSUMERS(LVS5) = {
|
||||
REGULATOR_SUPPLY("8921_lvs5", NULL),
|
||||
REGULATOR_SUPPLY("cam_vio", "4-001a"),
|
||||
REGULATOR_SUPPLY("cam_vio", "4-006c"),
|
||||
REGULATOR_SUPPLY("cam_vio", "4-0048"),
|
||||
REGULATOR_SUPPLY("cam_vio", "4-0020"),
|
||||
REGULATOR_SUPPLY("cam_vio", "4-0034"),
|
||||
};
|
||||
VREG_CONSUMERS(LVS6) = {
|
||||
REGULATOR_SUPPLY("8921_lvs6", NULL),
|
||||
REGULATOR_SUPPLY("vdd_io", "spi0.0"),
|
||||
};
|
||||
VREG_CONSUMERS(LVS7) = {
|
||||
REGULATOR_SUPPLY("8921_lvs7", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(USB_OTG) = {
|
||||
REGULATOR_SUPPLY("8921_usb_otg", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(HDMI_MVS) = {
|
||||
REGULATOR_SUPPLY("8921_hdmi_mvs", NULL),
|
||||
REGULATOR_SUPPLY("hdmi_mvs", "hdmi_msm.0"),
|
||||
};
|
||||
VREG_CONSUMERS(NCP) = {
|
||||
REGULATOR_SUPPLY("8921_ncp", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(EXT_5V) = {
|
||||
REGULATOR_SUPPLY("ext_5v", NULL),
|
||||
};
|
||||
VREG_CONSUMERS(EXT_L2) = {
|
||||
REGULATOR_SUPPLY("ext_l2", NULL),
|
||||
REGULATOR_SUPPLY("vdd_phy", "spi0.0"),
|
||||
};
|
||||
VREG_CONSUMERS(EXT_3P3V) = {
|
||||
REGULATOR_SUPPLY("ext_3p3v", NULL),
|
||||
REGULATOR_SUPPLY("vdd_ana", "3-005b"),
|
||||
REGULATOR_SUPPLY("vdd_lvds_3p3v", "mipi_dsi.1"),
|
||||
REGULATOR_SUPPLY("mhl_ext_3p3v", "msm_otg"),
|
||||
};
|
||||
VREG_CONSUMERS(EXT_OTG_SW) = {
|
||||
REGULATOR_SUPPLY("ext_otg_sw", NULL),
|
||||
REGULATOR_SUPPLY("vbus_otg", "msm_otg"),
|
||||
};
|
||||
|
||||
#define PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, _modes, _ops, \
|
||||
_apply_uV, _pull_down, _always_on, _supply_regulator, \
|
||||
_system_uA, _enable_time, _reg_id) \
|
||||
{ \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_modes_mask = _modes, \
|
||||
.valid_ops_mask = _ops, \
|
||||
.min_uV = _min_uV, \
|
||||
.max_uV = _max_uV, \
|
||||
.input_uV = _max_uV, \
|
||||
.apply_uV = _apply_uV, \
|
||||
.always_on = _always_on, \
|
||||
.name = _name, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id), \
|
||||
.consumer_supplies = vreg_consumers_##_id, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.id = _reg_id, \
|
||||
.pull_down_enable = _pull_down, \
|
||||
.system_uA = _system_uA, \
|
||||
.enable_time = _enable_time, \
|
||||
}
|
||||
|
||||
#define PM8XXX_LDO(_id, _name, _always_on, _pull_down, _min_uV, _max_uV, \
|
||||
_enable_time, _supply_regulator, _system_uA, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE | \
|
||||
REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
|
||||
REGULATOR_CHANGE_DRMS, 0, _pull_down, _always_on, \
|
||||
_supply_regulator, _system_uA, _enable_time, _reg_id)
|
||||
|
||||
#define PM8XXX_NLDO1200(_id, _name, _always_on, _pull_down, _min_uV, \
|
||||
_max_uV, _enable_time, _supply_regulator, _system_uA, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE | \
|
||||
REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
|
||||
REGULATOR_CHANGE_DRMS, 0, _pull_down, _always_on, \
|
||||
_supply_regulator, _system_uA, _enable_time, _reg_id)
|
||||
|
||||
#define PM8XXX_SMPS(_id, _name, _always_on, _pull_down, _min_uV, _max_uV, \
|
||||
_enable_time, _supply_regulator, _system_uA, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE | \
|
||||
REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
|
||||
REGULATOR_CHANGE_DRMS, 0, _pull_down, _always_on, \
|
||||
_supply_regulator, _system_uA, _enable_time, _reg_id)
|
||||
|
||||
#define PM8XXX_FTSMPS(_id, _name, _always_on, _pull_down, _min_uV, _max_uV, \
|
||||
_enable_time, _supply_regulator, _system_uA, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, REGULATOR_MODE_NORMAL, \
|
||||
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS \
|
||||
| REGULATOR_CHANGE_MODE, 0, _pull_down, _always_on, \
|
||||
_supply_regulator, _system_uA, _enable_time, _reg_id)
|
||||
|
||||
#define PM8XXX_VS(_id, _name, _always_on, _pull_down, _enable_time, \
|
||||
_supply_regulator, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, \
|
||||
_pull_down, _always_on, _supply_regulator, 0, _enable_time, \
|
||||
_reg_id)
|
||||
|
||||
#define PM8XXX_VS300(_id, _name, _always_on, _pull_down, _enable_time, \
|
||||
_supply_regulator, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, \
|
||||
_pull_down, _always_on, _supply_regulator, 0, _enable_time, \
|
||||
_reg_id)
|
||||
|
||||
#define PM8XXX_NCP(_id, _name, _always_on, _min_uV, _max_uV, _enable_time, \
|
||||
_supply_regulator, _reg_id) \
|
||||
PM8XXX_VREG_INIT(_id, _name, _min_uV, _max_uV, 0, \
|
||||
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, 0, 0, \
|
||||
_always_on, _supply_regulator, 0, _enable_time, _reg_id)
|
||||
|
||||
/* Pin control initialization */
|
||||
#define PM8XXX_PC(_id, _name, _always_on, _pin_fn, _pin_ctrl, \
|
||||
_supply_regulator, _reg_id) \
|
||||
{ \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS, \
|
||||
.always_on = _always_on, \
|
||||
.name = _name, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id##_PC), \
|
||||
.consumer_supplies = vreg_consumers_##_id##_PC, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.id = _reg_id, \
|
||||
.pin_fn = PM8XXX_VREG_PIN_FN_##_pin_fn, \
|
||||
.pin_ctrl = _pin_ctrl, \
|
||||
}
|
||||
|
||||
#define GPIO_VREG(_id, _reg_name, _gpio_label, _gpio, _supply_regulator) \
|
||||
[GPIO_VREG_ID_##_id] = { \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id), \
|
||||
.consumer_supplies = vreg_consumers_##_id, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.regulator_name = _reg_name, \
|
||||
.gpio_label = _gpio_label, \
|
||||
.gpio = _gpio, \
|
||||
}
|
||||
|
||||
#define SAW_VREG_INIT(_id, _name, _min_uV, _max_uV) \
|
||||
{ \
|
||||
.constraints = { \
|
||||
.name = _name, \
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, \
|
||||
.min_uV = _min_uV, \
|
||||
.max_uV = _max_uV, \
|
||||
}, \
|
||||
.num_consumer_supplies = ARRAY_SIZE(vreg_consumers_##_id), \
|
||||
.consumer_supplies = vreg_consumers_##_id, \
|
||||
}
|
||||
|
||||
#define RPM_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, _default_uV, \
|
||||
_peak_uA, _avg_uA, _pull_down, _pin_ctrl, _freq, _pin_fn, \
|
||||
_force_mode, _sleep_set_force_mode, _power_mode, _state, \
|
||||
_sleep_selectable, _always_on, _supply_regulator, _system_uA) \
|
||||
{ \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_modes_mask = _modes, \
|
||||
.valid_ops_mask = _ops, \
|
||||
.min_uV = _min_uV, \
|
||||
.max_uV = _max_uV, \
|
||||
.input_uV = _min_uV, \
|
||||
.apply_uV = _apply_uV, \
|
||||
.always_on = _always_on, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id), \
|
||||
.consumer_supplies = vreg_consumers_##_id, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.id = RPM_VREG_ID_PM8921_##_id, \
|
||||
.default_uV = _default_uV, \
|
||||
.peak_uA = _peak_uA, \
|
||||
.avg_uA = _avg_uA, \
|
||||
.pull_down_enable = _pull_down, \
|
||||
.pin_ctrl = _pin_ctrl, \
|
||||
.freq = RPM_VREG_FREQ_##_freq, \
|
||||
.pin_fn = _pin_fn, \
|
||||
.force_mode = _force_mode, \
|
||||
.sleep_set_force_mode = _sleep_set_force_mode, \
|
||||
.power_mode = _power_mode, \
|
||||
.state = _state, \
|
||||
.sleep_selectable = _sleep_selectable, \
|
||||
.system_uA = _system_uA, \
|
||||
}
|
||||
|
||||
#define RPM_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
|
||||
_supply_regulator, _system_uA, _init_peak_uA) \
|
||||
RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
|
||||
| REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
|
||||
| REGULATOR_CHANGE_DRMS, 0, _max_uV, _init_peak_uA, 0, _pd, \
|
||||
RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8960_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8960_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8960_NONE, RPM_VREG_POWER_MODE_8960_PWM, \
|
||||
RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
|
||||
_supply_regulator, _system_uA)
|
||||
|
||||
#define RPM_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
|
||||
_supply_regulator, _system_uA, _freq, _force_mode, \
|
||||
_sleep_set_force_mode) \
|
||||
RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
|
||||
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
|
||||
| REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
|
||||
| REGULATOR_CHANGE_DRMS, 0, _max_uV, _system_uA, 0, _pd, \
|
||||
RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_8960_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8960_##_force_mode, \
|
||||
RPM_VREG_FORCE_MODE_8960_##_sleep_set_force_mode, \
|
||||
RPM_VREG_POWER_MODE_8960_PWM, RPM_VREG_STATE_OFF, \
|
||||
_sleep_selectable, _always_on, _supply_regulator, _system_uA)
|
||||
|
||||
#define RPM_VS(_id, _always_on, _pd, _sleep_selectable, _supply_regulator) \
|
||||
RPM_INIT(_id, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, 0, 1000, 1000, _pd, \
|
||||
RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8960_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8960_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8960_NONE, RPM_VREG_POWER_MODE_8960_PWM, \
|
||||
RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
|
||||
_supply_regulator, 0)
|
||||
|
||||
#define RPM_NCP(_id, _always_on, _sleep_selectable, _min_uV, _max_uV, \
|
||||
_supply_regulator, _freq) \
|
||||
RPM_INIT(_id, _min_uV, _max_uV, 0, REGULATOR_CHANGE_VOLTAGE \
|
||||
| REGULATOR_CHANGE_STATUS, 0, _max_uV, 1000, 1000, 0, \
|
||||
RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_8960_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8960_NONE, \
|
||||
RPM_VREG_FORCE_MODE_8960_NONE, RPM_VREG_POWER_MODE_8960_PWM, \
|
||||
RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
|
||||
_supply_regulator, 0)
|
||||
|
||||
/* Pin control initialization */
|
||||
#define RPM_PC_INIT(_id, _always_on, _pin_fn, _pin_ctrl, _supply_regulator) \
|
||||
{ \
|
||||
.init_data = { \
|
||||
.constraints = { \
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS, \
|
||||
.always_on = _always_on, \
|
||||
}, \
|
||||
.num_consumer_supplies = \
|
||||
ARRAY_SIZE(vreg_consumers_##_id##_PC), \
|
||||
.consumer_supplies = vreg_consumers_##_id##_PC, \
|
||||
.supply_regulator = _supply_regulator, \
|
||||
}, \
|
||||
.id = RPM_VREG_ID_PM8921_##_id##_PC, \
|
||||
.pin_fn = RPM_VREG_PIN_FN_8960_##_pin_fn, \
|
||||
.pin_ctrl = _pin_ctrl, \
|
||||
}
|
||||
|
||||
/* GPIO regulator constraints */
|
||||
struct gpio_regulator_platform_data msm_gpio_regulator_pdata[] __devinitdata = {
|
||||
/* ID vreg_name gpio_label gpio supply */
|
||||
GPIO_VREG(EXT_5V, "ext_5v", "ext_5v_en", PM8921_MPP_PM_TO_SYS(7), NULL),
|
||||
GPIO_VREG(EXT_L2, "ext_l2", "ext_l2_en", 91, NULL),
|
||||
GPIO_VREG(EXT_3P3V, "ext_3p3v", "ext_3p3v_en",
|
||||
PM8921_GPIO_PM_TO_SYS(17), NULL),
|
||||
GPIO_VREG(EXT_OTG_SW, "ext_otg_sw", "ext_otg_sw_en",
|
||||
PM8921_GPIO_PM_TO_SYS(42), "8921_usb_otg"),
|
||||
};
|
||||
|
||||
/* SAW regulator constraints */
|
||||
struct regulator_init_data msm_saw_regulator_pdata_s5 =
|
||||
/* ID vreg_name min_uV max_uV */
|
||||
SAW_VREG_INIT(S5, "8921_s5", 850000, 1300000);
|
||||
struct regulator_init_data msm_saw_regulator_pdata_s6 =
|
||||
SAW_VREG_INIT(S6, "8921_s6", 850000, 1300000);
|
||||
|
||||
/* PM8921 regulator constraints */
|
||||
struct pm8xxx_regulator_platform_data
|
||||
msm_pm8921_regulator_pdata[] __devinitdata = {
|
||||
/*
|
||||
* ID name always_on pd min_uV max_uV en_t supply
|
||||
* system_uA reg_ID
|
||||
*/
|
||||
PM8XXX_NLDO1200(L26, "8921_l26", 0, 1, 375000, 1050000, 200, "8921_s7",
|
||||
0, 1),
|
||||
PM8XXX_NLDO1200(L27, "8921_l27", 0, 1, 375000, 1050000, 200, "8921_s7",
|
||||
0, 2),
|
||||
PM8XXX_NLDO1200(L28, "8921_l28", 0, 1, 375000, 1050000, 200, "8921_s7",
|
||||
0, 3),
|
||||
PM8XXX_LDO(L29, "8921_l29", 0, 1, 2050000, 2100000, 200, "8921_s8",
|
||||
0, 4),
|
||||
|
||||
/* ID name always_on pd en_t supply reg_ID */
|
||||
PM8XXX_VS300(USB_OTG, "8921_usb_otg", 0, 1, 0, "ext_5v", 5),
|
||||
PM8XXX_VS300(HDMI_MVS, "8921_hdmi_mvs", 0, 1, 0, "ext_5v", 6),
|
||||
};
|
||||
|
||||
static struct rpm_regulator_init_data
|
||||
msm_rpm_regulator_init_data[] __devinitdata = {
|
||||
/* ID a_on pd ss min_uV max_uV supply sys_uA freq fm ss_fm */
|
||||
RPM_SMPS(S1, 1, 1, 0, 1225000, 1225000, NULL, 100000, 3p20, NONE, NONE),
|
||||
RPM_SMPS(S2, 0, 1, 0, 1300000, 1300000, NULL, 0, 1p60, NONE, NONE),
|
||||
RPM_SMPS(S3, 0, 1, 1, 500000, 1150000, NULL, 100000, 4p80, NONE, NONE),
|
||||
RPM_SMPS(S4, 1, 1, 0, 1800000, 1800000, NULL, 100000, 1p60, AUTO, AUTO),
|
||||
RPM_SMPS(S7, 0, 1, 0, 1150000, 1150000, NULL, 100000, 3p20, NONE, NONE),
|
||||
RPM_SMPS(S8, 1, 1, 1, 2050000, 2050000, NULL, 100000, 1p60, NONE, NONE),
|
||||
|
||||
/* ID a_on pd ss min_uV max_uV supply sys_uA init_ip */
|
||||
RPM_LDO(L1, 1, 1, 0, 1050000, 1050000, "8921_s4", 0, 10000),
|
||||
RPM_LDO(L2, 0, 1, 0, 1200000, 1200000, "8921_s4", 0, 0),
|
||||
RPM_LDO(L3, 0, 1, 0, 3075000, 3075000, NULL, 0, 0),
|
||||
RPM_LDO(L4, 1, 1, 0, 1800000, 1800000, NULL, 10000, 10000),
|
||||
RPM_LDO(L5, 0, 1, 0, 2950000, 2950000, NULL, 0, 0),
|
||||
RPM_LDO(L6, 0, 1, 0, 2950000, 2950000, NULL, 0, 0),
|
||||
RPM_LDO(L7, 1, 1, 0, 1850000, 2950000, NULL, 10000, 10000),
|
||||
RPM_LDO(L8, 0, 1, 0, 2800000, 3000000, NULL, 0, 0),
|
||||
RPM_LDO(L9, 0, 1, 0, 3000000, 3000000, NULL, 0, 0),
|
||||
RPM_LDO(L10, 0, 1, 0, 3000000, 3000000, NULL, 0, 0),
|
||||
RPM_LDO(L11, 0, 1, 0, 2850000, 2850000, NULL, 0, 0),
|
||||
RPM_LDO(L12, 0, 1, 0, 1200000, 1200000, "8921_s4", 0, 0),
|
||||
RPM_LDO(L14, 0, 1, 0, 1800000, 1800000, NULL, 0, 0),
|
||||
RPM_LDO(L15, 0, 1, 0, 1800000, 2950000, NULL, 0, 0),
|
||||
RPM_LDO(L16, 0, 1, 0, 2800000, 2800000, NULL, 0, 0),
|
||||
RPM_LDO(L17, 0, 1, 0, 1800000, 2950000, NULL, 0, 0),
|
||||
RPM_LDO(L18, 0, 1, 0, 1300000, 1300000, "8921_s4", 0, 0),
|
||||
RPM_LDO(L21, 0, 1, 0, 1900000, 1900000, "8921_s8", 0, 0),
|
||||
RPM_LDO(L22, 0, 1, 0, 2750000, 2750000, NULL, 0, 0),
|
||||
RPM_LDO(L23, 1, 1, 1, 1800000, 1800000, "8921_s8", 10000, 10000),
|
||||
RPM_LDO(L24, 0, 1, 1, 750000, 1150000, "8921_s1", 10000, 10000),
|
||||
RPM_LDO(L25, 1, 1, 0, 1250000, 1250000, "8921_s1", 10000, 10000),
|
||||
|
||||
/* ID a_on pd ss supply */
|
||||
RPM_VS(LVS1, 0, 1, 0, "8921_s4"),
|
||||
RPM_VS(LVS2, 0, 1, 0, "8921_s1"),
|
||||
RPM_VS(LVS3, 0, 1, 0, "8921_s4"),
|
||||
RPM_VS(LVS4, 0, 1, 0, "8921_s4"),
|
||||
RPM_VS(LVS5, 0, 1, 0, "8921_s4"),
|
||||
RPM_VS(LVS6, 0, 1, 0, "8921_s4"),
|
||||
RPM_VS(LVS7, 0, 1, 0, "8921_s4"),
|
||||
|
||||
/* ID a_on ss min_uV max_uV supply freq */
|
||||
RPM_NCP(NCP, 0, 0, 1800000, 1800000, "8921_l6", 1p60),
|
||||
};
|
||||
|
||||
int msm_pm8921_regulator_pdata_len __devinitdata =
|
||||
ARRAY_SIZE(msm_pm8921_regulator_pdata);
|
||||
|
||||
struct rpm_regulator_platform_data msm_rpm_regulator_pdata __devinitdata = {
|
||||
.init_data = msm_rpm_regulator_init_data,
|
||||
.num_regulators = ARRAY_SIZE(msm_rpm_regulator_init_data),
|
||||
.version = RPM_VREG_VERSION_8960,
|
||||
.vreg_id_vdd_mem = RPM_VREG_ID_PM8921_L24,
|
||||
.vreg_id_vdd_dig = RPM_VREG_ID_PM8921_S3,
|
||||
};
|
||||
383
arch/arm/mach-msm/board-8960-storage.c
Normal file
383
arch/arm/mach-msm/board-8960-storage.c
Normal file
@@ -0,0 +1,383 @@
|
||||
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/mmc.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/gpiomux.h>
|
||||
#include "devices.h"
|
||||
#include "board-8960.h"
|
||||
#include "board-storage-common-a.h"
|
||||
|
||||
/* MSM8960 has 5 SDCC controllers */
|
||||
enum sdcc_controllers {
|
||||
SDCC1,
|
||||
SDCC2,
|
||||
SDCC3,
|
||||
SDCC4,
|
||||
SDCC5,
|
||||
MAX_SDCC_CONTROLLER
|
||||
};
|
||||
|
||||
/* All SDCC controllers require VDD/VCC voltage */
|
||||
static struct msm_mmc_reg_data mmc_vdd_reg_data[MAX_SDCC_CONTROLLER] = {
|
||||
/* SDCC1 : eMMC card connected */
|
||||
[SDCC1] = {
|
||||
.name = "sdc_vdd",
|
||||
.high_vol_level = 2950000,
|
||||
.low_vol_level = 2950000,
|
||||
.always_on = 1,
|
||||
.lpm_sup = 1,
|
||||
.lpm_uA = 9000,
|
||||
.hpm_uA = 200000, /* 200mA */
|
||||
},
|
||||
/* SDCC2 : SDIO slot connected */
|
||||
[SDCC2] = {
|
||||
.name = "sdc_vdd",
|
||||
.high_vol_level = 1800000,
|
||||
.low_vol_level = 1800000,
|
||||
.always_on = 1,
|
||||
.lpm_sup = 1,
|
||||
.lpm_uA = 9000,
|
||||
.hpm_uA = 200000, /* 200mA */
|
||||
},
|
||||
/* SDCC3 : External card slot connected */
|
||||
[SDCC3] = {
|
||||
.name = "sdc_vdd",
|
||||
.high_vol_level = 2950000,
|
||||
.low_vol_level = 2950000,
|
||||
.hpm_uA = 600000, /* 600mA */
|
||||
}
|
||||
};
|
||||
|
||||
/* SDCC controllers may require voting for IO operating voltage */
|
||||
static struct msm_mmc_reg_data mmc_vdd_io_reg_data[MAX_SDCC_CONTROLLER] = {
|
||||
/* SDCC1 : eMMC card connected */
|
||||
[SDCC1] = {
|
||||
.name = "sdc_vdd_io",
|
||||
.always_on = 1,
|
||||
.high_vol_level = 1800000,
|
||||
.low_vol_level = 1800000,
|
||||
.hpm_uA = 200000, /* 200mA */
|
||||
},
|
||||
/* SDCC3 : External card slot connected */
|
||||
[SDCC3] = {
|
||||
.name = "sdc_vdd_io",
|
||||
.high_vol_level = 2950000,
|
||||
.low_vol_level = 1850000,
|
||||
.always_on = 1,
|
||||
.lpm_sup = 1,
|
||||
/* Max. Active current required is 16 mA */
|
||||
.hpm_uA = 16000,
|
||||
/*
|
||||
* Sleep current required is ~300 uA. But min. vote can be
|
||||
* in terms of mA (min. 1 mA). So let's vote for 2 mA
|
||||
* during sleep.
|
||||
*/
|
||||
.lpm_uA = 2000,
|
||||
},
|
||||
/* SDCC4 : SDIO slot connected */
|
||||
[SDCC4] = {
|
||||
.name = "sdc_vdd_io",
|
||||
.high_vol_level = 1800000,
|
||||
.low_vol_level = 1800000,
|
||||
.always_on = 1,
|
||||
.lpm_sup = 1,
|
||||
.hpm_uA = 200000, /* 200mA */
|
||||
.lpm_uA = 2000,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_mmc_slot_reg_data mmc_slot_vreg_data[MAX_SDCC_CONTROLLER] = {
|
||||
/* SDCC1 : eMMC card connected */
|
||||
[SDCC1] = {
|
||||
.vdd_data = &mmc_vdd_reg_data[SDCC1],
|
||||
.vdd_io_data = &mmc_vdd_io_reg_data[SDCC1],
|
||||
},
|
||||
/* SDCC2 : SDIO card slot connected */
|
||||
[SDCC2] = {
|
||||
.vdd_data = &mmc_vdd_reg_data[SDCC2],
|
||||
},
|
||||
/* SDCC3 : External card slot connected */
|
||||
[SDCC3] = {
|
||||
.vdd_data = &mmc_vdd_reg_data[SDCC3],
|
||||
.vdd_io_data = &mmc_vdd_io_reg_data[SDCC3],
|
||||
},
|
||||
/* SDCC4 : SDIO card slot connected */
|
||||
[SDCC4] = {
|
||||
.vdd_io_data = &mmc_vdd_io_reg_data[SDCC4],
|
||||
},
|
||||
};
|
||||
|
||||
/* SDC1 pad data */
|
||||
static struct msm_mmc_pad_drv sdc1_pad_drv_on_cfg[] = {
|
||||
{TLMM_HDRV_SDC1_CLK, GPIO_CFG_16MA},
|
||||
{TLMM_HDRV_SDC1_CMD, GPIO_CFG_10MA},
|
||||
{TLMM_HDRV_SDC1_DATA, GPIO_CFG_10MA}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_drv sdc1_pad_drv_off_cfg[] = {
|
||||
{TLMM_HDRV_SDC1_CLK, GPIO_CFG_2MA},
|
||||
{TLMM_HDRV_SDC1_CMD, GPIO_CFG_2MA},
|
||||
{TLMM_HDRV_SDC1_DATA, GPIO_CFG_2MA}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull sdc1_pad_pull_on_cfg[] = {
|
||||
{TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL},
|
||||
{TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP},
|
||||
{TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull sdc1_pad_pull_off_cfg[] = {
|
||||
{TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL},
|
||||
{TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP},
|
||||
{TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP}
|
||||
};
|
||||
|
||||
/* SDC3 pad data */
|
||||
static struct msm_mmc_pad_drv sdc3_pad_drv_on_cfg[] = {
|
||||
{TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA},
|
||||
{TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA},
|
||||
{TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_drv sdc3_pad_drv_off_cfg[] = {
|
||||
{TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA},
|
||||
{TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA},
|
||||
{TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull sdc3_pad_pull_on_cfg[] = {
|
||||
{TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL},
|
||||
{TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
|
||||
{TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull sdc3_pad_pull_off_cfg[] = {
|
||||
{TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL},
|
||||
/*
|
||||
* SDC3 CMD line should be PULLed UP otherwise fluid platform will
|
||||
* see transitions (1 -> 0 and 0 -> 1) on card detection line,
|
||||
* which would result in false card detection interrupts.
|
||||
*/
|
||||
{TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
|
||||
/*
|
||||
* Keeping DATA lines status to PULL UP will make sure that
|
||||
* there is no current leak during sleep if external pull up
|
||||
* is connected to DATA lines.
|
||||
*/
|
||||
{TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_pull_data mmc_pad_pull_data[MAX_SDCC_CONTROLLER] = {
|
||||
[SDCC1] = {
|
||||
.on = sdc1_pad_pull_on_cfg,
|
||||
.off = sdc1_pad_pull_off_cfg,
|
||||
.size = ARRAY_SIZE(sdc1_pad_pull_on_cfg)
|
||||
},
|
||||
[SDCC3] = {
|
||||
.on = sdc3_pad_pull_on_cfg,
|
||||
.off = sdc3_pad_pull_off_cfg,
|
||||
.size = ARRAY_SIZE(sdc3_pad_pull_on_cfg)
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_drv_data mmc_pad_drv_data[MAX_SDCC_CONTROLLER] = {
|
||||
[SDCC1] = {
|
||||
.on = sdc1_pad_drv_on_cfg,
|
||||
.off = sdc1_pad_drv_off_cfg,
|
||||
.size = ARRAY_SIZE(sdc1_pad_drv_on_cfg)
|
||||
},
|
||||
[SDCC3] = {
|
||||
.on = sdc3_pad_drv_on_cfg,
|
||||
.off = sdc3_pad_drv_off_cfg,
|
||||
.size = ARRAY_SIZE(sdc3_pad_drv_on_cfg)
|
||||
},
|
||||
};
|
||||
|
||||
struct msm_mmc_gpio sdc2_gpio[] = {
|
||||
{92, "sdc2_dat_3"},
|
||||
{91, "sdc2_dat_2"},
|
||||
{90, "sdc2_dat_1"},
|
||||
{89, "sdc2_dat_0"},
|
||||
{97, "sdc2_cmd"},
|
||||
{98, "sdc2_clk"}
|
||||
};
|
||||
|
||||
struct msm_mmc_gpio sdc4_gpio[] = {
|
||||
{83, "sdc4_dat_3"},
|
||||
{84, "sdc4_dat_2"},
|
||||
{85, "sdc4_dat_1"},
|
||||
{86, "sdc4_dat_0"},
|
||||
{87, "sdc4_cmd"},
|
||||
{88, "sdc4_clk"}
|
||||
};
|
||||
|
||||
struct msm_mmc_gpio_data mmc_gpio_data[MAX_SDCC_CONTROLLER] = {
|
||||
[SDCC2] = {
|
||||
.gpio = sdc2_gpio,
|
||||
.size = ARRAY_SIZE(sdc2_gpio),
|
||||
},
|
||||
[SDCC4] = {
|
||||
.gpio = sdc4_gpio,
|
||||
.size = ARRAY_SIZE(sdc4_gpio),
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_mmc_pad_data mmc_pad_data[MAX_SDCC_CONTROLLER] = {
|
||||
[SDCC1] = {
|
||||
.pull = &mmc_pad_pull_data[SDCC1],
|
||||
.drv = &mmc_pad_drv_data[SDCC1]
|
||||
},
|
||||
[SDCC3] = {
|
||||
.pull = &mmc_pad_pull_data[SDCC3],
|
||||
.drv = &mmc_pad_drv_data[SDCC3]
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_mmc_pin_data mmc_slot_pin_data[MAX_SDCC_CONTROLLER] = {
|
||||
[SDCC1] = {
|
||||
.pad_data = &mmc_pad_data[SDCC1],
|
||||
},
|
||||
[SDCC2] = {
|
||||
.is_gpio = 1,
|
||||
.gpio_data = &mmc_gpio_data[SDCC2],
|
||||
},
|
||||
[SDCC3] = {
|
||||
.pad_data = &mmc_pad_data[SDCC3],
|
||||
},
|
||||
[SDCC4] = {
|
||||
.is_gpio = 1,
|
||||
.gpio_data = &mmc_gpio_data[SDCC4],
|
||||
},
|
||||
};
|
||||
|
||||
#define MSM_MPM_PIN_SDC1_DAT1 17
|
||||
#define MSM_MPM_PIN_SDC3_DAT1 21
|
||||
|
||||
static unsigned int sdc1_sup_clk_rates[] = {
|
||||
400000, 24000000, 48000000
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
|
||||
static unsigned int sdc3_sup_clk_rates[] = {
|
||||
400000, 24000000, 48000000, 96000000, 192000000
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
|
||||
static struct mmc_platform_data msm8960_sdc1_data = {
|
||||
.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
|
||||
#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
|
||||
.mmc_bus_width = MMC_CAP_8_BIT_DATA,
|
||||
#else
|
||||
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
|
||||
#endif
|
||||
.sup_clk_table = sdc1_sup_clk_rates,
|
||||
.sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates),
|
||||
.pclk_src_dfab = 1,
|
||||
.nonremovable = 1,
|
||||
.vreg_data = &mmc_slot_vreg_data[SDCC1],
|
||||
.pin_data = &mmc_slot_pin_data[SDCC1],
|
||||
.mpm_sdiowakeup_int = MSM_MPM_PIN_SDC1_DAT1,
|
||||
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
|
||||
static unsigned int sdc2_sup_clk_rates[] = {
|
||||
400000, 24000000, 48000000
|
||||
};
|
||||
|
||||
static struct mmc_platform_data msm8960_sdc2_data = {
|
||||
.ocr_mask = MMC_VDD_165_195,
|
||||
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
|
||||
.sup_clk_table = sdc2_sup_clk_rates,
|
||||
.sup_clk_cnt = ARRAY_SIZE(sdc2_sup_clk_rates),
|
||||
.pclk_src_dfab = 1,
|
||||
.vreg_data = &mmc_slot_vreg_data[SDCC2],
|
||||
.pin_data = &mmc_slot_pin_data[SDCC2],
|
||||
.sdiowakeup_irq = MSM_GPIO_TO_INT(90),
|
||||
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
|
||||
static struct mmc_platform_data msm8960_sdc3_data = {
|
||||
.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
|
||||
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
|
||||
.sup_clk_table = sdc3_sup_clk_rates,
|
||||
.sup_clk_cnt = ARRAY_SIZE(sdc3_sup_clk_rates),
|
||||
.pclk_src_dfab = 1,
|
||||
#ifdef CONFIG_MMC_MSM_SDC3_WP_SUPPORT
|
||||
.wpswitch_gpio = PM8921_GPIO_PM_TO_SYS(16),
|
||||
#endif
|
||||
.vreg_data = &mmc_slot_vreg_data[SDCC3],
|
||||
.pin_data = &mmc_slot_pin_data[SDCC3],
|
||||
#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
|
||||
.status_gpio = PM8921_GPIO_PM_TO_SYS(26),
|
||||
.status_irq = PM8921_GPIO_IRQ(PM8921_IRQ_BASE, 26),
|
||||
.irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
|
||||
.is_status_gpio_active_low = true,
|
||||
#endif
|
||||
.xpc_cap = 1,
|
||||
.uhs_caps = (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
|
||||
MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 |
|
||||
MMC_CAP_UHS_SDR104 | MMC_CAP_MAX_CURRENT_600),
|
||||
.mpm_sdiowakeup_int = MSM_MPM_PIN_SDC3_DAT1,
|
||||
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
|
||||
static unsigned int sdc4_sup_clk_rates[] = {
|
||||
400000, 24000000, 48000000
|
||||
};
|
||||
|
||||
static struct mmc_platform_data msm8960_sdc4_data = {
|
||||
.ocr_mask = MMC_VDD_165_195,
|
||||
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
|
||||
.sup_clk_table = sdc4_sup_clk_rates,
|
||||
.sup_clk_cnt = ARRAY_SIZE(sdc4_sup_clk_rates),
|
||||
.pclk_src_dfab = 1,
|
||||
.vreg_data = &mmc_slot_vreg_data[SDCC4],
|
||||
.pin_data = &mmc_slot_pin_data[SDCC4],
|
||||
.sdiowakeup_irq = MSM_GPIO_TO_INT(85),
|
||||
.msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
|
||||
};
|
||||
#endif
|
||||
|
||||
void __init msm8960_init_mmc(void)
|
||||
{
|
||||
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
|
||||
/* SDC1 : eMMC card connected */
|
||||
msm_add_sdcc(1, &msm8960_sdc1_data);
|
||||
#endif
|
||||
#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
|
||||
/* SDC2: SDIO slot for WLAN*/
|
||||
msm_add_sdcc(2, &msm8960_sdc2_data);
|
||||
#endif
|
||||
#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
|
||||
/* SDC3: External card slot */
|
||||
msm_add_sdcc(3, &msm8960_sdc3_data);
|
||||
#endif
|
||||
#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
|
||||
/* SDC4: SDIO slot for WLAN */
|
||||
msm_add_sdcc(4, &msm8960_sdc4_data);
|
||||
#endif
|
||||
}
|
||||
3261
arch/arm/mach-msm/board-8960.c
Normal file
3261
arch/arm/mach-msm/board-8960.c
Normal file
File diff suppressed because it is too large
Load Diff
94
arch/arm/mach-msm/board-8960.h
Normal file
94
arch/arm/mach-msm/board-8960.h
Normal file
@@ -0,0 +1,94 @@
|
||||
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_MSM_BOARD_MSM8960_H
|
||||
#define __ARCH_ARM_MACH_MSM_BOARD_MSM8960_H
|
||||
|
||||
#include <linux/regulator/msm-gpio-regulator.h>
|
||||
#include <linux/mfd/pm8xxx/pm8921.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c/sx150x.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/rpm-regulator.h>
|
||||
#include <mach/msm_memtypes.h>
|
||||
#include <mach/msm_rtb.h>
|
||||
#include <mach/msm_cache_dump.h>
|
||||
|
||||
/* Macros assume PMIC GPIOs and MPPs start at 1 */
|
||||
#define PM8921_GPIO_BASE NR_GPIO_IRQS
|
||||
#define PM8921_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio - 1 + PM8921_GPIO_BASE)
|
||||
#define PM8921_MPP_BASE (PM8921_GPIO_BASE + PM8921_NR_GPIOS)
|
||||
#define PM8921_MPP_PM_TO_SYS(pm_gpio) (pm_gpio - 1 + PM8921_MPP_BASE)
|
||||
#define PM8921_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
|
||||
|
||||
extern struct pm8xxx_regulator_platform_data
|
||||
msm_pm8921_regulator_pdata[] __devinitdata;
|
||||
|
||||
extern int msm_pm8921_regulator_pdata_len __devinitdata;
|
||||
|
||||
#define GPIO_VREG_ID_EXT_5V 0
|
||||
#define GPIO_VREG_ID_EXT_L2 1
|
||||
#define GPIO_VREG_ID_EXT_3P3V 2
|
||||
#define GPIO_VREG_ID_EXT_OTG_SW 3
|
||||
|
||||
extern struct gpio_regulator_platform_data
|
||||
msm_gpio_regulator_pdata[] __devinitdata;
|
||||
|
||||
extern struct regulator_init_data msm_saw_regulator_pdata_s5;
|
||||
extern struct regulator_init_data msm_saw_regulator_pdata_s6;
|
||||
|
||||
extern struct rpm_regulator_platform_data msm_rpm_regulator_pdata __devinitdata;
|
||||
|
||||
#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
|
||||
enum {
|
||||
GPIO_EXPANDER_IRQ_BASE = (PM8921_IRQ_BASE + PM8921_NR_IRQS),
|
||||
GPIO_EXPANDER_GPIO_BASE = (PM8921_MPP_BASE + PM8921_NR_MPPS),
|
||||
/* CAM Expander */
|
||||
GPIO_CAM_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE,
|
||||
GPIO_CAM_GP_STROBE_READY = GPIO_CAM_EXPANDER_BASE,
|
||||
GPIO_CAM_GP_AFBUSY,
|
||||
GPIO_CAM_GP_STROBE_CE,
|
||||
GPIO_CAM_GP_CAM1MP_XCLR,
|
||||
GPIO_CAM_GP_CAMIF_RESET_N,
|
||||
GPIO_CAM_GP_XMT_FLASH_INT,
|
||||
GPIO_CAM_GP_LED_EN1,
|
||||
GPIO_CAM_GP_LED_EN2,
|
||||
GPIO_LIQUID_EXPANDER_BASE = GPIO_CAM_EXPANDER_BASE + 8,
|
||||
};
|
||||
#endif
|
||||
|
||||
enum {
|
||||
SX150X_CAM,
|
||||
SX150X_LIQUID,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
extern struct sx150x_platform_data msm8960_sx150x_data[];
|
||||
extern struct msm_camera_board_info msm8960_camera_board_info;
|
||||
|
||||
void msm8960_init_cam(void);
|
||||
void msm8960_init_fb(void);
|
||||
void msm8960_init_pmic(void);
|
||||
void msm8960_init_mmc(void);
|
||||
int msm8960_init_gpiomux(void);
|
||||
unsigned char msm8960_hdmi_as_primary_selected(void);
|
||||
void msm8960_allocate_fb_region(void);
|
||||
void msm8960_set_display_params(char *prim_panel, char *ext_panel);
|
||||
void msm8960_pm8921_gpio_mpp_init(void);
|
||||
void msm8960_mdp_writeback(struct memtype_reserve *reserve_table);
|
||||
#define MSM_8960_GSBI4_QUP_I2C_BUS_ID 4
|
||||
#define MSM_8960_GSBI3_QUP_I2C_BUS_ID 3
|
||||
#define MSM_8960_GSBI10_QUP_I2C_BUS_ID 10
|
||||
|
||||
extern struct msm_rtb_platform_data msm8960_rtb_pdata;
|
||||
extern struct msm_cache_dump_platform_data msm8960_cache_dump_pdata;
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user