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msm_fb: display: Add DMA and Overlay blt mode address to MDP driver

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For handling split IOMMU domain cases, BLT mode requires DMA to map
for reads and Overlay for writes. DMA and Overlay blt addresses are
added to configure the respective registers to avoid page faults and
normal operation of supported panel interfaces.

Change-Id: Id007cf96588f817bcfe8559177abb073a9b00755
Signed-off-by: Ravishangar Kalyanam <rkalya@codeaurora.org>
This commit is contained in:
Ravishangar Kalyanam
2012-06-13 11:25:38 -07:00
committed by Stephen Boyd
parent 8ef1229097
commit a00a29607c
10 changed files with 148 additions and 115 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/video/msm/mdp.h
View File

@@ -75,7 +75,8 @@ extern struct workqueue_struct *mdp_hist_wq;
struct mdp_buf_type {
struct ion_handle *ihdl;
u32 phys_addr;
u32 write_addr;
u32 read_addr;
u32 size;
};

3
drivers/video/msm/mdp4.h
View File

@@ -337,7 +337,8 @@ struct mdp4_overlay_pipe {
uint32 element1; /* 0 = C0, 1 = C1, 2 = C2, 3 = C3 */
uint32 element0; /* 0 = C0, 1 = C1, 2 = C2, 3 = C3 */
struct completion comp;
ulong blt_addr; /* blt mode addr */
ulong ov_blt_addr; /* blt mode addr */
ulong dma_blt_addr; /* blt mode addr */
ulong blt_base;
ulong blt_offset;
uint32 blt_cnt;

20
drivers/video/msm/mdp4_overlay.c
View File

@@ -346,7 +346,7 @@ void mdp4_overlay_dmae_xy(struct mdp4_overlay_pipe *pipe)
MDP_OUTP(MDP_BASE + 0xb0004,
(pipe->src_height << 16 | pipe->src_width));
if (pipe->blt_addr) {
if (pipe->dma_blt_addr) {
uint32 off, bpp;
#ifdef BLT_RGB565
bpp = 2; /* overlay ouput is RGB565 */
@@ -356,7 +356,7 @@ void mdp4_overlay_dmae_xy(struct mdp4_overlay_pipe *pipe)
off = 0;
if (pipe->ov_cnt & 0x01)
off = pipe->src_height * pipe->src_width * bpp;
MDP_OUTP(MDP_BASE + 0xb0008, pipe->blt_addr + off);
MDP_OUTP(MDP_BASE + 0xb0008, pipe->dma_blt_addr + off);
/* RGB888, output of overlay blending */
MDP_OUTP(MDP_BASE + 0xb000c, pipe->src_width * bpp);
} else {
@@ -424,7 +424,7 @@ void mdp4_overlay_dmap_xy(struct mdp4_overlay_pipe *pipe)
if (mdp_is_in_isr == FALSE)
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
if (pipe->blt_addr) {
if (pipe->dma_blt_addr) {
#ifdef BLT_RGB565
bpp = 2; /* overlay ouput is RGB565 */
#else
@@ -433,7 +433,7 @@ void mdp4_overlay_dmap_xy(struct mdp4_overlay_pipe *pipe)
off = 0;
if (pipe->dmap_cnt & 0x01)
off = pipe->src_height * pipe->src_width * bpp;
MDP_OUTP(MDP_BASE + 0x90008, pipe->blt_addr + off);
MDP_OUTP(MDP_BASE + 0x90008, pipe->dma_blt_addr + off);
/* RGB888, output of overlay blending */
MDP_OUTP(MDP_BASE + 0x9000c, pipe->src_width * bpp);
} else {
@@ -1321,7 +1321,7 @@ void mdp4_overlayproc_cfg(struct mdp4_overlay_pipe *pipe)
/*
* BLT support both primary and external external
*/
if (pipe->blt_addr) {
if (pipe->ov_blt_addr) {
int off, bpp;
#ifdef BLT_RGB565
bpp = 2; /* overlay ouput is RGB565 */
@@ -1338,10 +1338,10 @@ void mdp4_overlayproc_cfg(struct mdp4_overlay_pipe *pipe)
if (pipe->ov_cnt & 0x01)
off = pipe->src_height * pipe->src_width * bpp;
outpdw(overlay_base + 0x000c, pipe->blt_addr + off);
outpdw(overlay_base + 0x000c, pipe->ov_blt_addr + off);
/* overlay ouput is RGB888 */
outpdw(overlay_base + 0x0010, pipe->src_width * bpp);
outpdw(overlay_base + 0x001c, pipe->blt_addr + off);
outpdw(overlay_base + 0x001c, pipe->ov_blt_addr + off);
/* MDDI - BLT + on demand */
outpdw(overlay_base + 0x0004, 0x08);
@@ -1361,19 +1361,19 @@ void mdp4_overlayproc_cfg(struct mdp4_overlay_pipe *pipe)
pipe->src_width * bpp;
outpdw(overlay_base + 0x000c,
pipe->blt_addr + off);
pipe->ov_blt_addr + off);
/* overlay ouput is RGB888 */
outpdw(overlay_base + 0x0010,
((pipe->src_width << 16) |
pipe->src_width));
outpdw(overlay_base + 0x001c,
pipe->blt_addr + off);
pipe->ov_blt_addr + off);
off = pipe->src_height * pipe->src_width;
/* align chroma to 2k address */
off = (off + 2047) & ~2047;
/* UV plane adress */
outpdw(overlay_base + 0x0020,
pipe->blt_addr + off);
pipe->ov_blt_addr + off);
/* MDDI - BLT + on demand */
outpdw(overlay_base + 0x0004, 0x08);
/* pseudo planar + writeback */

49
drivers/video/msm/mdp4_overlay_dsi_cmd.c
View File

@@ -162,7 +162,8 @@ void mdp4_overlay_update_dsi_cmd(struct msm_fb_data_type *mfd)
dsi_pipe = pipe; /* keep it */
mdp4_init_writeback_buf(mfd, MDP4_MIXER0);
pipe->blt_addr = 0;
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
} else {
pipe = dsi_pipe;
@@ -321,24 +322,25 @@ int mdp4_dsi_overlay_blt_start(struct msm_fb_data_type *mfd)
{
unsigned long flag;
pr_debug("%s: blt_end=%d blt_addr=%x pid=%d\n",
__func__, dsi_pipe->blt_end, (int)dsi_pipe->blt_addr, current->pid);
pr_debug("%s: blt_end=%d ov_blt_addr=%x pid=%d\n",
__func__, dsi_pipe->blt_end, (int)dsi_pipe->ov_blt_addr, current->pid);
mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);
if (mfd->ov0_wb_buf->phys_addr == 0) {
if (mfd->ov0_wb_buf->write_addr == 0) {
pr_info("%s: no blt_base assigned\n", __func__);
return -EBUSY;
}
if (dsi_pipe->blt_addr == 0) {
if (dsi_pipe->ov_blt_addr == 0) {
mdp4_dsi_cmd_dma_busy_wait(mfd);
spin_lock_irqsave(&mdp_spin_lock, flag);
dsi_pipe->blt_end = 0;
dsi_pipe->blt_cnt = 0;
dsi_pipe->ov_cnt = 0;
dsi_pipe->dmap_cnt = 0;
dsi_pipe->blt_addr = mfd->ov0_wb_buf->phys_addr;
dsi_pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;
dsi_pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;
mdp4_stat.blt_dsi_cmd++;
spin_unlock_irqrestore(&mdp_spin_lock, flag);
return 0;
@@ -352,10 +354,10 @@ int mdp4_dsi_overlay_blt_stop(struct msm_fb_data_type *mfd)
unsigned long flag;
pr_debug("%s: blt_end=%d blt_addr=%x\n",
__func__, dsi_pipe->blt_end, (int)dsi_pipe->blt_addr);
pr_debug("%s: blt_end=%d ov_blt_addr=%x\n",
__func__, dsi_pipe->blt_end, (int)dsi_pipe->ov_blt_addr);
if ((dsi_pipe->blt_end == 0) && dsi_pipe->blt_addr) {
if ((dsi_pipe->blt_end == 0) && dsi_pipe->ov_blt_addr) {
spin_lock_irqsave(&mdp_spin_lock, flag);
dsi_pipe->blt_end = 1; /* mark as end */
spin_unlock_irqrestore(&mdp_spin_lock, flag);
@@ -393,7 +395,7 @@ void mdp4_blt_xy_update(struct mdp4_overlay_pipe *pipe)
char *overlay_base;
if (pipe->blt_addr == 0)
if (pipe->ov_blt_addr == 0)
return;
@@ -405,7 +407,7 @@ void mdp4_blt_xy_update(struct mdp4_overlay_pipe *pipe)
off = 0;
if (pipe->dmap_cnt & 0x01)
off = pipe->src_height * pipe->src_width * bpp;
addr = pipe->blt_addr + off;
addr = pipe->dma_blt_addr + off;
/* dmap */
MDP_OUTP(MDP_BASE + 0x90008, addr);
@@ -413,7 +415,7 @@ void mdp4_blt_xy_update(struct mdp4_overlay_pipe *pipe)
off = 0;
if (pipe->ov_cnt & 0x01)
off = pipe->src_height * pipe->src_width * bpp;
addr2 = pipe->blt_addr + off;
addr2 = pipe->ov_blt_addr + off;
/* overlay 0 */
overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
outpdw(overlay_base + 0x000c, addr2);
@@ -441,7 +443,8 @@ void mdp4_dma_p_done_dsi(struct mdp_dma_data *dma)
spin_unlock(&mdp_spin_lock);
if (dsi_pipe->blt_end) {
dsi_pipe->blt_end = 0;
dsi_pipe->blt_addr = 0;
dsi_pipe->dma_blt_addr = 0;
dsi_pipe->ov_blt_addr = 0;
pr_debug("%s: END, ov_cnt=%d dmap_cnt=%d\n",
__func__, dsi_pipe->ov_cnt, dsi_pipe->dmap_cnt);
mdp_intr_mask &= ~INTR_DMA_P_DONE;
@@ -479,7 +482,7 @@ void mdp4_overlay0_done_dsi_cmd(struct mdp_dma_data *dma)
{
int diff;
if (dsi_pipe->blt_addr == 0) {
if (dsi_pipe->ov_blt_addr == 0) {
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE);
spin_lock(&mdp_spin_lock);
dma->busy = FALSE;
@@ -539,7 +542,7 @@ void mdp4_dsi_cmd_overlay_restore(void)
mipi_dsi_mdp_busy_wait(dsi_mfd);
mdp4_overlay_update_dsi_cmd(dsi_mfd);
if (dsi_pipe->blt_addr)
if (dsi_pipe->ov_blt_addr)
mdp4_dsi_blt_dmap_busy_wait(dsi_mfd);
mdp4_dsi_cmd_overlay_kickoff(dsi_mfd, dsi_pipe);
}
@@ -622,17 +625,17 @@ void mdp4_dsi_cmd_kickoff_video(struct msm_fb_data_type *mfd,
* to be called before kickoff.
* vice versa for blt disabled.
*/
if (dsi_pipe->blt_addr && dsi_pipe->blt_cnt == 0)
if (dsi_pipe->ov_blt_addr && dsi_pipe->blt_cnt == 0)
mdp4_overlay_update_dsi_cmd(mfd); /* first time */
else if (dsi_pipe->blt_addr == 0 && dsi_pipe->blt_cnt) {
else if (dsi_pipe->ov_blt_addr == 0 && dsi_pipe->blt_cnt) {
mdp4_overlay_update_dsi_cmd(mfd); /* last time */
dsi_pipe->blt_cnt = 0;
}
pr_debug("%s: blt_addr=%d blt_cnt=%d\n",
__func__, (int)dsi_pipe->blt_addr, dsi_pipe->blt_cnt);
pr_debug("%s: ov_blt_addr=%d blt_cnt=%d\n",
__func__, (int)dsi_pipe->ov_blt_addr, dsi_pipe->blt_cnt);
if (dsi_pipe->blt_addr)
if (dsi_pipe->ov_blt_addr)
mdp4_dsi_blt_dmap_busy_wait(dsi_mfd);
mdp4_dsi_cmd_overlay_kickoff(mfd, pipe);
@@ -658,7 +661,7 @@ void mdp4_dsi_cmd_overlay_kickoff(struct msm_fb_data_type *mfd,
mipi_dsi_mdp_busy_wait(mfd);
if (dsi_pipe->blt_addr == 0)
if (dsi_pipe->ov_blt_addr == 0)
mipi_dsi_cmd_mdp_start();
mdp4_overlay_dsi_state_set(ST_DSI_PLAYING);
@@ -666,7 +669,7 @@ void mdp4_dsi_cmd_overlay_kickoff(struct msm_fb_data_type *mfd,
spin_lock_irqsave(&mdp_spin_lock, flag);
mdp_enable_irq(MDP_OVERLAY0_TERM);
mfd->dma->busy = TRUE;
if (dsi_pipe->blt_addr)
if (dsi_pipe->ov_blt_addr)
mfd->dma->dmap_busy = TRUE;
/* start OVERLAY pipe */
spin_unlock_irqrestore(&mdp_spin_lock, flag);
@@ -700,7 +703,7 @@ void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
if (mfd && mfd->panel_power_on) {
mdp4_dsi_cmd_dma_busy_wait(mfd);
if (dsi_pipe && dsi_pipe->blt_addr)
if (dsi_pipe && dsi_pipe->ov_blt_addr)
mdp4_dsi_blt_dmap_busy_wait(mfd);
mdp4_overlay_update_dsi_cmd(mfd);

33
drivers/video/msm/mdp4_overlay_dsi_video.c
View File

@@ -152,7 +152,8 @@ int mdp4_dsi_video_on(struct platform_device *pdev)
init_completion(&dsi_video_comp);
mdp4_init_writeback_buf(mfd, MDP4_MIXER0);
pipe->blt_addr = 0;
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
} else {
pipe = dsi_pipe;
@@ -416,7 +417,7 @@ static void mdp4_dsi_video_blt_ov_update(struct mdp4_overlay_pipe *pipe)
char *overlay_base;
if (pipe->blt_addr == 0)
if (pipe->ov_blt_addr == 0)
return;
@@ -428,7 +429,7 @@ static void mdp4_dsi_video_blt_ov_update(struct mdp4_overlay_pipe *pipe)
off = 0;
if (pipe->ov_cnt & 0x01)
off = pipe->src_height * pipe->src_width * bpp;
addr = pipe->blt_addr + off;
addr = pipe->ov_blt_addr + off;
/* overlay 0 */
overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
@@ -441,7 +442,7 @@ static void mdp4_dsi_video_blt_dmap_update(struct mdp4_overlay_pipe *pipe)
uint32 off, addr;
int bpp;
if (pipe->blt_addr == 0)
if (pipe->ov_blt_addr == 0)
return;
@@ -453,7 +454,7 @@ static void mdp4_dsi_video_blt_dmap_update(struct mdp4_overlay_pipe *pipe)
off = 0;
if (pipe->dmap_cnt & 0x01)
off = pipe->src_height * pipe->src_width * bpp;
addr = pipe->blt_addr + off;
addr = pipe->dma_blt_addr + off;
/* dmap */
MDP_OUTP(MDP_BASE + 0x90008, addr);
@@ -529,7 +530,7 @@ void mdp4_overlay_dsi_video_vsync_push(struct msm_fb_data_type *mfd,
if (pipe->flags & MDP_OV_PLAY_NOWAIT)
return;
if (dsi_pipe->blt_addr) {
if (dsi_pipe->ov_blt_addr) {
mdp4_overlay_dsi_video_dma_busy_wait(mfd);
mdp4_dsi_video_blt_ov_update(dsi_pipe);
@@ -572,7 +573,7 @@ void mdp4_dma_p_done_dsi_video(struct mdp_dma_data *dma)
mdp4_overlayproc_cfg(dsi_pipe);
mdp4_overlay_dmap_xy(dsi_pipe);
mdp_is_in_isr = FALSE;
if (dsi_pipe->blt_addr) {
if (dsi_pipe->ov_blt_addr) {
mdp4_dsi_video_blt_ov_update(dsi_pipe);
dsi_pipe->ov_cnt++;
outp32(MDP_INTR_CLEAR, INTR_OVERLAY0_DONE);
@@ -595,7 +596,7 @@ void mdp4_overlay0_done_dsi_video(struct mdp_dma_data *dma)
{
spin_lock(&mdp_spin_lock);
dma->busy = FALSE;
if (dsi_pipe->blt_addr == 0) {
if (dsi_pipe->ov_blt_addr == 0) {
spin_unlock(&mdp_spin_lock);
return;
}
@@ -618,21 +619,23 @@ static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);
if (mfd->ov0_wb_buf->phys_addr == 0) {
if (mfd->ov0_wb_buf->write_addr == 0) {
pr_info("%s: no blt_base assigned\n", __func__);
return;
}
spin_lock_irqsave(&mdp_spin_lock, flag);
if (enable && dsi_pipe->blt_addr == 0) {
dsi_pipe->blt_addr = mfd->ov0_wb_buf->phys_addr;
if (enable && dsi_pipe->ov_blt_addr == 0) {
dsi_pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;
dsi_pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;
dsi_pipe->blt_cnt = 0;
dsi_pipe->ov_cnt = 0;
dsi_pipe->dmap_cnt = 0;
mdp4_stat.blt_dsi_video++;
change++;
} else if (enable == 0 && dsi_pipe->blt_addr) {
dsi_pipe->blt_addr = 0;
} else if (enable == 0 && dsi_pipe->ov_blt_addr) {
dsi_pipe->ov_blt_addr = 0;
dsi_pipe->dma_blt_addr = 0;
change++;
}
@@ -641,8 +644,8 @@ static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
return;
}
pr_debug("%s: enable=%d blt_addr=%x\n", __func__,
enable, (int)dsi_pipe->blt_addr);
pr_debug("%s: enable=%d ov_blt_addr=%x\n", __func__,
enable, (int)dsi_pipe->ov_blt_addr);
blt_cfg_changed = 1;
spin_unlock_irqrestore(&mdp_spin_lock, flag);

31
drivers/video/msm/mdp4_overlay_dtv.c
View File

@@ -377,7 +377,8 @@ int mdp4_overlay_dtv_set(struct msm_fb_data_type *mfd,
return -ENODEV;
mdp4_init_writeback_buf(mfd, MDP4_MIXER1);
dtv_pipe->blt_addr = 0;
dtv_pipe->ov_blt_addr = 0;
dtv_pipe->dma_blt_addr = 0;
return mdp4_dtv_start(mfd);
}
@@ -408,7 +409,7 @@ static void mdp4_dtv_blt_ov_update(struct mdp4_overlay_pipe *pipe)
int bpp;
char *overlay_base;
if (pipe->blt_addr == 0)
if (pipe->ov_blt_addr == 0)
return;
#ifdef BLT_RGB565
bpp = 2; /* overlay ouput is RGB565 */
@@ -418,7 +419,7 @@ static void mdp4_dtv_blt_ov_update(struct mdp4_overlay_pipe *pipe)
off = (pipe->ov_cnt & 0x01) ?
pipe->src_height * pipe->src_width * bpp : 0;
addr = pipe->blt_addr + off;
addr = pipe->ov_blt_addr + off;
pr_debug("%s overlay addr 0x%x\n", __func__, addr);
/* overlay 1 */
overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
@@ -431,7 +432,7 @@ static inline void mdp4_dtv_blt_dmae_update(struct mdp4_overlay_pipe *pipe)
uint32 off, addr;
int bpp;
if (pipe->blt_addr == 0)
if (pipe->ov_blt_addr == 0)
return;
#ifdef BLT_RGB565
@@ -441,7 +442,7 @@ static inline void mdp4_dtv_blt_dmae_update(struct mdp4_overlay_pipe *pipe)
#endif
off = (pipe->dmae_cnt & 0x01) ?
pipe->src_height * pipe->src_width * bpp : 0;
addr = pipe->blt_addr + off;
addr = pipe->dma_blt_addr + off;
MDP_OUTP(MDP_BASE + 0xb0008, addr);
}
@@ -464,7 +465,7 @@ static void mdp4_overlay_dtv_ov_start(struct msm_fb_data_type *mfd)
return;
}
if (dtv_pipe->blt_addr) {
if (dtv_pipe->ov_blt_addr) {
mdp4_dtv_blt_ov_update(dtv_pipe);
dtv_pipe->ov_cnt++;
mdp4_overlay_dtv_ov_kick_start();
@@ -524,7 +525,7 @@ static void mdp4_overlay_dtv_wait4_ov_done(struct msm_fb_data_type *mfd,
msecs_to_jiffies(VSYNC_PERIOD * 3));
mdp_disable_irq(MDP_OVERLAY1_TERM);
if (dtv_pipe->blt_addr)
if (dtv_pipe->ov_blt_addr)
mdp4_overlay_dtv_wait4dmae(mfd);
}
@@ -581,7 +582,7 @@ void mdp4_overlay1_done_dtv()
{
if (!dtv_pipe)
return;
if (dtv_pipe->blt_addr) {
if (dtv_pipe->ov_blt_addr) {
mdp4_dtv_blt_dmae_update(dtv_pipe);
dtv_pipe->dmae_cnt++;
}
@@ -642,7 +643,7 @@ static void mdp4_dtv_do_blt(struct msm_fb_data_type *mfd, int enable)
unsigned long flag;
int change = 0;
if (!mfd->ov1_wb_buf->phys_addr) {
if (!mfd->ov1_wb_buf->write_addr) {
pr_debug("%s: no writeback buf assigned\n", __func__);
return;
}
@@ -654,16 +655,18 @@ static void mdp4_dtv_do_blt(struct msm_fb_data_type *mfd, int enable)
}
spin_lock_irqsave(&mdp_spin_lock, flag);
if (enable && dtv_pipe->blt_addr == 0) {
dtv_pipe->blt_addr = mfd->ov1_wb_buf->phys_addr;
if (enable && dtv_pipe->ov_blt_addr == 0) {
dtv_pipe->ov_blt_addr = mfd->ov1_wb_buf->write_addr;
dtv_pipe->dma_blt_addr = mfd->ov1_wb_buf->read_addr;
change++;
dtv_pipe->ov_cnt = 0;
dtv_pipe->dmae_cnt = 0;
} else if (enable == 0 && dtv_pipe->blt_addr) {
dtv_pipe->blt_addr = 0;
} else if (enable == 0 && dtv_pipe->ov_blt_addr) {
dtv_pipe->ov_blt_addr = 0;
dtv_pipe->dma_blt_addr = 0;
change++;
}
pr_debug("%s: blt_addr=%x\n", __func__, (int)dtv_pipe->blt_addr);
pr_debug("%s: ov_blt_addr=%x\n", __func__, (int)dtv_pipe->ov_blt_addr);
spin_unlock_irqrestore(&mdp_spin_lock, flag);
if (!change)

34
drivers/video/msm/mdp4_overlay_lcdc.c
View File

@@ -133,8 +133,8 @@ int mdp_lcdc_on(struct platform_device *pdev)
init_completion(&lcdc_comp);
mdp4_init_writeback_buf(mfd, MDP4_MIXER0);
pipe->blt_addr = 0;
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
} else {
pipe = lcdc_pipe;
}
@@ -325,7 +325,7 @@ static void mdp4_lcdc_blt_ov_update(struct mdp4_overlay_pipe *pipe)
char *overlay_base;
if (pipe->blt_addr == 0)
if (pipe->ov_blt_addr == 0)
return;
@@ -337,7 +337,7 @@ static void mdp4_lcdc_blt_ov_update(struct mdp4_overlay_pipe *pipe)
off = 0;
if (pipe->ov_cnt & 0x01)
off = pipe->src_height * pipe->src_width * bpp;
addr = pipe->blt_addr + off;
addr = pipe->ov_blt_addr + off;
/* overlay 0 */
overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
@@ -350,7 +350,7 @@ static void mdp4_lcdc_blt_dmap_update(struct mdp4_overlay_pipe *pipe)
uint32 off, addr;
int bpp;
if (pipe->blt_addr == 0)
if (pipe->ov_blt_addr == 0)
return;
@@ -362,7 +362,7 @@ static void mdp4_lcdc_blt_dmap_update(struct mdp4_overlay_pipe *pipe)
off = 0;
if (pipe->dmap_cnt & 0x01)
off = pipe->src_height * pipe->src_width * bpp;
addr = pipe->blt_addr + off;
addr = pipe->dma_blt_addr + off;
/* dmap */
MDP_OUTP(MDP_BASE + 0x90008, addr);
@@ -438,7 +438,7 @@ void mdp4_overlay_lcdc_vsync_push(struct msm_fb_data_type *mfd,
if (pipe->flags & MDP_OV_PLAY_NOWAIT)
return;
if (lcdc_pipe->blt_addr) {
if (lcdc_pipe->ov_blt_addr) {
mdp4_overlay_lcdc_dma_busy_wait(mfd);
mdp4_lcdc_blt_ov_update(lcdc_pipe);
@@ -485,7 +485,7 @@ void mdp4_overlay0_done_lcdc(struct mdp_dma_data *dma)
{
spin_lock(&mdp_spin_lock);
dma->busy = FALSE;
if (lcdc_pipe->blt_addr == 0) {
if (lcdc_pipe->ov_blt_addr == 0) {
spin_unlock(&mdp_spin_lock);
return;
}
@@ -500,7 +500,7 @@ static void mdp4_overlay_lcdc_prefill(struct msm_fb_data_type *mfd)
{
unsigned long flag;
if (lcdc_pipe->blt_addr) {
if (lcdc_pipe->ov_blt_addr) {
mdp4_overlay_lcdc_dma_busy_wait(mfd);
mdp4_lcdc_blt_ov_update(lcdc_pipe);
@@ -530,24 +530,26 @@ static void mdp4_lcdc_do_blt(struct msm_fb_data_type *mfd, int enable)
mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);
if (!mfd->ov0_wb_buf->phys_addr) {
if (!mfd->ov0_wb_buf->write_addr) {
pr_debug("%s: no blt_base assigned\n", __func__);
return;
}
spin_lock_irqsave(&mdp_spin_lock, flag);
if (enable && lcdc_pipe->blt_addr == 0) {
lcdc_pipe->blt_addr = mfd->ov0_wb_buf->phys_addr;
if (enable && lcdc_pipe->ov_blt_addr == 0) {
lcdc_pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;
lcdc_pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;
change++;
lcdc_pipe->blt_cnt = 0;
lcdc_pipe->ov_cnt = 0;
lcdc_pipe->dmap_cnt = 0;
mdp4_stat.blt_lcdc++;
} else if (enable == 0 && lcdc_pipe->blt_addr) {
lcdc_pipe->blt_addr = 0;
} else if (enable == 0 && lcdc_pipe->ov_blt_addr) {
lcdc_pipe->ov_blt_addr = 0;
lcdc_pipe->dma_blt_addr = 0;
change++;
}
pr_info("%s: blt_addr=%x\n", __func__, (int)lcdc_pipe->blt_addr);
pr_info("%s: ov_blt_addr=%x\n", __func__, (int)lcdc_pipe->ov_blt_addr);
spin_unlock_irqrestore(&mdp_spin_lock, flag);
if (!change)
@@ -561,7 +563,7 @@ static void mdp4_lcdc_do_blt(struct msm_fb_data_type *mfd, int enable)
mdp4_overlayproc_cfg(lcdc_pipe);
mdp4_overlay_dmap_xy(lcdc_pipe);
if (lcdc_pipe->blt_addr) {
if (lcdc_pipe->ov_blt_addr) {
mdp4_overlay_lcdc_prefill(mfd);
mdp4_overlay_lcdc_prefill(mfd);
}

44
drivers/video/msm/mdp4_overlay_mddi.c
View File

@@ -163,7 +163,8 @@ void mdp4_overlay_update_lcd(struct msm_fb_data_type *mfd)
MDP_OUTP(MDP_BASE + 0x00098, 0x01);
mdp4_init_writeback_buf(mfd, MDP4_MIXER0);
pipe->blt_addr = 0;
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
} else {
pipe = mddi_pipe;
}
@@ -254,23 +255,25 @@ int mdp4_mddi_overlay_blt_start(struct msm_fb_data_type *mfd)
unsigned long flag;
pr_debug("%s: blt_end=%d blt_addr=%x pid=%d\n",
__func__, mddi_pipe->blt_end, (int)mddi_pipe->blt_addr, current->pid);
__func__, mddi_pipe->blt_end,
(int)mddi_pipe->ov_blt_addr, current->pid);
mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);
if (mfd->ov0_wb_buf->phys_addr == 0) {
if (mfd->ov0_wb_buf->write_addr == 0) {
pr_info("%s: no blt_base assigned\n", __func__);
return -EBUSY;
}
if (mddi_pipe->blt_addr == 0) {
if (mddi_pipe->ov_blt_addr == 0) {
mdp4_mddi_dma_busy_wait(mfd);
spin_lock_irqsave(&mdp_spin_lock, flag);
mddi_pipe->blt_end = 0;
mddi_pipe->blt_cnt = 0;
mddi_pipe->ov_cnt = 0;
mddi_pipe->dmap_cnt = 0;
mddi_pipe->blt_addr = mfd->ov0_wb_buf->phys_addr;
mddi_pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;
mddi_pipe->dma_blt_addr = mfd->ov0_wb_buf->write_addr;
mdp4_stat.blt_mddi++;
spin_unlock_irqrestore(&mdp_spin_lock, flag);
return 0;
@@ -284,9 +287,9 @@ int mdp4_mddi_overlay_blt_stop(struct msm_fb_data_type *mfd)
unsigned long flag;
pr_debug("%s: blt_end=%d blt_addr=%x\n",
__func__, mddi_pipe->blt_end, (int)mddi_pipe->blt_addr);
__func__, mddi_pipe->blt_end, (int)mddi_pipe->ov_blt_addr);
if ((mddi_pipe->blt_end == 0) && mddi_pipe->blt_addr) {
if ((mddi_pipe->blt_end == 0) && mddi_pipe->ov_blt_addr) {
spin_lock_irqsave(&mdp_spin_lock, flag);
mddi_pipe->blt_end = 1; /* mark as end */
spin_unlock_irqrestore(&mdp_spin_lock, flag);
@@ -323,7 +326,7 @@ void mdp4_blt_xy_update(struct mdp4_overlay_pipe *pipe)
int bpp;
char *overlay_base;
if (pipe->blt_addr == 0)
if (pipe->ov_blt_addr == 0)
return;
@@ -336,7 +339,7 @@ void mdp4_blt_xy_update(struct mdp4_overlay_pipe *pipe)
if (pipe->dmap_cnt & 0x01)
off = pipe->src_height * pipe->src_width * bpp;
addr = pipe->blt_addr + off;
addr = pipe->ov_blt_addr + off;
/* dmap */
MDP_OUTP(MDP_BASE + 0x90008, addr);
@@ -344,7 +347,7 @@ void mdp4_blt_xy_update(struct mdp4_overlay_pipe *pipe)
off = 0;
if (pipe->ov_cnt & 0x01)
off = pipe->src_height * pipe->src_width * bpp;
addr2 = pipe->blt_addr + off;
addr2 = pipe->ov_blt_addr + off;
/* overlay 0 */
overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
outpdw(overlay_base + 0x000c, addr2);
@@ -371,7 +374,8 @@ void mdp4_dma_p_done_mddi(struct mdp_dma_data *dma)
if (mddi_pipe->blt_end) {
mddi_pipe->blt_end = 0;
mddi_pipe->blt_addr = 0;
mddi_pipe->ov_blt_addr = 0;
mddi_pipe->dma_blt_addr = 0;
pr_debug("%s: END, ov_cnt=%d dmap_cnt=%d\n", __func__,
mddi_pipe->ov_cnt, mddi_pipe->dmap_cnt);
mdp_intr_mask &= ~INTR_DMA_P_DONE;
@@ -406,7 +410,7 @@ void mdp4_overlay0_done_mddi(struct mdp_dma_data *dma)
{
int diff;
if (mddi_pipe->blt_addr == 0) {
if (mddi_pipe->ov_blt_addr == 0) {
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE);
spin_lock(&mdp_spin_lock);
dma->busy = FALSE;
@@ -473,7 +477,7 @@ void mdp4_mddi_overlay_restore(void)
mdp4_mddi_dma_busy_wait(mddi_mfd);
mdp4_overlay_update_lcd(mddi_mfd);
if (mddi_pipe->blt_addr)
if (mddi_pipe->ov_blt_addr)
mdp4_mddi_blt_dmap_busy_wait(mddi_mfd);
mdp4_mddi_overlay_kickoff(mddi_mfd, mddi_pipe);
mddi_mfd->dma_update_flag = 1;
@@ -539,17 +543,17 @@ void mdp4_mddi_kickoff_video(struct msm_fb_data_type *mfd,
* to be called before kickoff.
* vice versa for blt disabled.
*/
if (mddi_pipe->blt_addr && mddi_pipe->blt_cnt == 0)
if (mddi_pipe->ov_blt_addr && mddi_pipe->blt_cnt == 0)
mdp4_overlay_update_lcd(mfd); /* first time */
else if (mddi_pipe->blt_addr == 0 && mddi_pipe->blt_cnt) {
else if (mddi_pipe->ov_blt_addr == 0 && mddi_pipe->blt_cnt) {
mdp4_overlay_update_lcd(mfd); /* last time */
mddi_pipe->blt_cnt = 0;
}
pr_debug("%s: blt_addr=%d blt_cnt=%d\n",
__func__, (int)mddi_pipe->blt_addr, mddi_pipe->blt_cnt);
__func__, (int)mddi_pipe->ov_blt_addr, mddi_pipe->blt_cnt);
if (mddi_pipe->blt_addr)
if (mddi_pipe->ov_blt_addr)
mdp4_mddi_blt_dmap_busy_wait(mddi_mfd);
mdp4_mddi_overlay_kickoff(mfd, pipe);
}
@@ -572,7 +576,7 @@ void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd,
mdp_enable_irq(MDP_OVERLAY0_TERM);
spin_lock_irqsave(&mdp_spin_lock, flag);
mfd->dma->busy = TRUE;
if (mddi_pipe->blt_addr)
if (mddi_pipe->ov_blt_addr)
mfd->dma->dmap_busy = TRUE;
spin_unlock_irqrestore(&mdp_spin_lock, flag);
/* start OVERLAY pipe */
@@ -657,7 +661,7 @@ void mdp4_mddi_dma_s_kickoff(struct msm_fb_data_type *mfd,
mdp_enable_irq(MDP_DMA_S_TERM);
if (mddi_pipe->blt_addr == 0)
if (mddi_pipe->ov_blt_addr == 0)
mfd->dma->busy = TRUE;
mfd->ibuf_flushed = TRUE;
@@ -688,7 +692,7 @@ void mdp4_mddi_overlay(struct msm_fb_data_type *mfd)
if (mfd && mfd->panel_power_on) {
mdp4_mddi_dma_busy_wait(mfd);
if (mddi_pipe && mddi_pipe->blt_addr)
if (mddi_pipe && mddi_pipe->ov_blt_addr)
mdp4_mddi_blt_dmap_busy_wait(mfd);
mdp4_overlay_update_lcd(mfd);

14
drivers/video/msm/mdp4_overlay_writeback.c
View File

@@ -272,11 +272,11 @@ void mdp4_writeback_kickoff_video(struct msm_fb_data_type *mfd,
}
mutex_unlock(&mfd->writeback_mutex);
writeback_pipe->blt_addr = (ulong) (node ? node->addr : NULL);
writeback_pipe->ov_blt_addr = (ulong) (node ? node->addr : NULL);
if (!writeback_pipe->blt_addr) {
if (!writeback_pipe->ov_blt_addr) {
pr_err("%s: no writeback buffer 0x%x, %p\n", __func__,
(unsigned int)writeback_pipe->blt_addr, node);
(unsigned int)writeback_pipe->ov_blt_addr, node);
mutex_unlock(&mfd->unregister_mutex);
return;
}
@@ -324,13 +324,13 @@ void mdp4_writeback_overlay(struct msm_fb_data_type *mfd)
}
mutex_unlock(&mfd->writeback_mutex);
writeback_pipe->blt_addr = (ulong) (node ? node->addr : NULL);
writeback_pipe->ov_blt_addr = (ulong) (node ? node->addr : NULL);
mutex_lock(&mfd->dma->ov_mutex);
pr_debug("%s in writeback\n", __func__);
if (writeback_pipe && !writeback_pipe->blt_addr) {
if (writeback_pipe && !writeback_pipe->ov_blt_addr) {
pr_err("%s: no writeback buffer 0x%x\n", __func__,
(unsigned int)writeback_pipe->blt_addr);
(unsigned int)writeback_pipe->ov_blt_addr);
ret = mdp4_overlay_writeback_update(mfd);
if (ret)
pr_err("%s: update failed writeback pipe NULL\n",
@@ -351,7 +351,7 @@ void mdp4_writeback_overlay(struct msm_fb_data_type *mfd)
}
pr_debug("%s: in writeback pan display 0x%x\n", __func__,
(unsigned int)writeback_pipe->blt_addr);
(unsigned int)writeback_pipe->ov_blt_addr);
mdp4_writeback_kickoff_ui(mfd, writeback_pipe);
mdp4_iommu_unmap(writeback_pipe);

32
drivers/video/msm/mdp4_util.c
View File

@@ -2559,13 +2559,14 @@ void mdp4_init_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
buf = mfd->ov1_wb_buf;
buf->ihdl = NULL;
buf->phys_addr = 0;
buf->write_addr = 0;
buf->read_addr = 0;
}
u32 mdp4_allocate_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
{
struct mdp_buf_type *buf;
ion_phys_addr_t addr;
ion_phys_addr_t addr, read_addr = 0;
size_t buffer_size;
unsigned long len;
@@ -2574,7 +2575,7 @@ u32 mdp4_allocate_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
else
buf = mfd->ov1_wb_buf;
if (buf->phys_addr || !IS_ERR_OR_NULL(buf->ihdl))
if (buf->write_addr || !IS_ERR_OR_NULL(buf->ihdl))
return 0;
if (!buf->size) {
@@ -2592,6 +2593,12 @@ u32 mdp4_allocate_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
mfd->mem_hid);
if (!IS_ERR_OR_NULL(buf->ihdl)) {
if (mdp_iommu_split_domain) {
if (ion_map_iommu(mfd->iclient, buf->ihdl,
DISPLAY_READ_DOMAIN, GEN_POOL, SZ_4K,
0, &read_addr, &len, 0, 0)) {
pr_err("ion_map_iommu() read failed\n");
return -ENOMEM;
}
if (mfd->mem_hid & ION_SECURE) {
if (ion_phys(mfd->iclient, buf->ihdl,
&addr, (size_t *)&len)) {
@@ -2612,7 +2619,7 @@ u32 mdp4_allocate_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
if (ion_map_iommu(mfd->iclient, buf->ihdl,
DISPLAY_READ_DOMAIN, GEN_POOL, SZ_4K,
0, &addr, &len, 0, 0)) {
pr_err("ion_map_iommu() failed\n");
pr_err("ion_map_iommu() write failed\n");
return -ENOMEM;
}
}
@@ -2628,7 +2635,13 @@ u32 mdp4_allocate_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
if (addr) {
pr_info("allocating %d bytes at %x for mdp writeback\n",
buffer_size, (u32) addr);
buf->phys_addr = addr;
buf->write_addr = addr;
if (read_addr)
buf->read_addr = read_addr;
else
buf->read_addr = buf->write_addr;
return 0;
} else {
pr_err("%s cannot allocate memory for mdp writeback!\n",
@@ -2652,6 +2665,8 @@ void mdp4_free_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
if (!(mfd->mem_hid & ION_SECURE))
ion_unmap_iommu(mfd->iclient, buf->ihdl,
DISPLAY_WRITE_DOMAIN, GEN_POOL);
ion_unmap_iommu(mfd->iclient, buf->ihdl,
DISPLAY_READ_DOMAIN, GEN_POOL);
} else {
ion_unmap_iommu(mfd->iclient, buf->ihdl,
DISPLAY_READ_DOMAIN, GEN_POOL);
@@ -2662,13 +2677,14 @@ void mdp4_free_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
buf->ihdl = NULL;
}
} else {
if (buf->phys_addr) {
free_contiguous_memory_by_paddr(buf->phys_addr);
if (buf->write_addr) {
free_contiguous_memory_by_paddr(buf->write_addr);
pr_debug("%s:%d free writeback pmem\n", __func__,
__LINE__);
}
}
buf->phys_addr = 0;
buf->write_addr = 0;
buf->read_addr = 0;
}
static int mdp4_update_pcc_regs(uint32_t offset,