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msm: Reorganize CPU config options to be meaningful

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commit e02db89be5da3cf610e548e162cfdd824a45b581
	Author:     Stepan Moskovchenko <stepanm@codeaurora.org>
	AuthorDate: Thu May 12 19:41:50 2011 -0700

	Reorganize the meaning of CONFIG_ARCH_MSM_SCORPION and
	CONFIG_ARCH_MSM_SCORPIONMP to be more intuitive, and to
	facilitate adding future targets. The SCORPION option now
	represents any target containing a Scorpion processor,
	regardless of the number of cores present. The MSM_SMP option now
	represents targets containing a multi-processor complex, and is
	selected regardless of CONFIG_SMP.
	The SCORPIONMP option selects both of these.

	Similarly, the KRAIT option now refers to current and future targets
	containing a Krait processor, regardless of core count. The KRAITMP
	option refers to targets containing a Krait-MP complex, and selects
	both KRAIT and MSM_SMP.

	Previously, SCORPIONMP was selected for targets containing either
	Scorpion or Krait CPUs, which is confusing and compicates adding
	new Krait-based targets, as these CPUs are substantially different.

Change-Id: I297d322c3bd931d9534026950cb64b95a0594ecd
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
This commit is contained in:
Rohit Vaswani
2013-01-22 16:04:13 -08:00
committed by Stephen Boyd
parent cd16cb0832
commit c4dcd5f15c
3 changed files with 10 additions and 12 deletions
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2
arch/arm/mm/Kconfig
View File

@@ -758,7 +758,7 @@ config CPU_DCACHE_SIZE
config CPU_CACHE_ERR_REPORT
bool "Report errors in the L1 and L2 caches"
depends on ARCH_MSM_SCORPION || ARCH_MSM_SCORPIONMP
depends on ARCH_MSM_SCORPION
default n
help
The Scorpion processor supports reporting L2 errors, L1 icache parity

6
arch/arm/mm/fault.c
View File

@@ -514,7 +514,7 @@ do_bad(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
return 1;
}
#ifdef CONFIG_ARCH_MSM_SCORPION
#if defined(CONFIG_ARCH_MSM_SCORPION) && !defined(CONFIG_MSM_SMP)
#define __str(x) #x
#define MRC(x, v1, v2, v4, v5, v6) do { \
unsigned int __##x; \
@@ -531,7 +531,7 @@ do_bad(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
int
do_imprecise_ext(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
{
#ifdef CONFIG_ARCH_MSM_SCORPION
#if defined(CONFIG_ARCH_MSM_SCORPION) && !defined(CONFIG_MSM_SMP)
MRC(ADFSR, p15, 0, c5, c1, 0);
MRC(DFSR, p15, 0, c5, c0, 0);
MRC(ACTLR, p15, 0, c1, c0, 1);
@@ -551,7 +551,7 @@ do_imprecise_ext(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
"mcr p15, 0, %0, c5, c1, 0"
: : "r" (0));
#endif
#ifdef CONFIG_ARCH_MSM_SCORPION
#if defined(CONFIG_ARCH_MSM_SCORPION) && !defined(CONFIG_MSM_SMP)
pr_info("%s: TCSR_SPARE2 = 0x%.8x\n", __func__, readl(MSM_TCSR_SPARE2));
#endif
return 1;

14
arch/arm/mm/proc-v7.S
View File

@@ -257,16 +257,13 @@ __v7_setup:
ldr r6, =NMRR @ NMRR
mcr p15, 0, r5, c10, c2, 0 @ write PRRR
mcr p15, 0, r6, c10, c2, 1 @ write NMRR
#ifdef CONFIG_ARCH_MSM_SCORPION
#ifdef CONFIG_ARCH_QSD8X50
mov r0, #0x77
#else
mov r0, #0x33
#endif
#if defined(CONFIG_ARCH_MSM_SCORPION) && !defined(CONFIG_MSM_SMP)
mov r0, #0x33
mcr p15, 3, r0, c15, c0, 3 @ set L2CR1
#endif
#if defined (CONFIG_ARCH_MSM_SCORPION) || defined (CONFIG_ARCH_MSM_SCORPIONMP)
#if defined (CONFIG_ARCH_MSM_SCORPION)
mrc p15, 0, r0, c1, c0, 1 @ read ACTLR
#ifdef CONFIG_CPU_CACHE_ERR_REPORT
orr r0, r0, #0x37 @ turn on L1/L2 error reporting
@@ -276,12 +273,13 @@ __v7_setup:
#if defined (CONFIG_ARCH_MSM_SCORPIONMP)
orr r0, r0, #0x1 << 24 @ optimal setting for Scorpion MP
#endif
#ifndef CONFIG_ARCH_MSM_KRAIT
mcr p15, 0, r0, c1, c0, 1 @ write ACTLR
#endif
#endif
#if defined (CONFIG_ARCH_MSM_SCORPIONMP)
mrc p15, 3, r0, c15, c0, 2 @ optimal setting for Scorpion MP
orr r0, r0, #0x1 << 21
orr r0, r0, #0x1 << 21
mcr p15, 3, r0, c15, c0, 2
#endif