msm_fb: display: add options to switch blt mode for dsi video
Currently switching mdp blt mode is done in dmap done isr which could cause mdp hang for some panels/targets. One option is added: turning off timing generator when switching blt mode, to avoid hang issues. Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
This commit is contained in:
committed by
Iliyan Malchev
parent
ca82d7b7cd
commit
ffde53dc8f
@@ -93,6 +93,12 @@ enum {
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#define MDP4_PANEL_DSI_CMD BIT(5)
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#define MDP4_PANEL_WRITEBACK BIT(6)
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enum {
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OVERLAY_BLT_SWITCH_TG_ON,
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OVERLAY_BLT_SWITCH_TG_OFF,
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OVERLAY_BLT_ALWAYS_ON
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};
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enum {
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OVERLAY_MODE_NONE,
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OVERLAY_MODE_BLT
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@@ -56,6 +56,7 @@ static struct vsycn_ctrl {
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int wait_vsync_cnt;
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int blt_change;
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int blt_free;
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int blt_ctrl;
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int sysfs_created;
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struct mutex update_lock;
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struct completion ov_comp;
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@@ -194,8 +195,6 @@ int mdp4_dsi_video_pipe_commit(int cndx, int wait)
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}
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spin_unlock_irqrestore(&vctrl->spin_lock, flags);
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mdp4_overlay_mdp_perf_upd(vctrl->mfd, 1);
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if (vctrl->blt_change) {
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pipe = vctrl->base_pipe;
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spin_lock_irqsave(&vctrl->spin_lock, flags);
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@@ -496,9 +495,11 @@ int mdp4_dsi_video_on(struct platform_device *pdev)
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int ret = 0;
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int cndx = 0;
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struct vsycn_ctrl *vctrl;
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struct msm_panel_info *pinfo;
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vctrl = &vsync_ctrl_db[cndx];
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mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
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pinfo = &mfd->panel_info;
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if (!mfd)
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return -ENODEV;
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@@ -508,6 +509,7 @@ int mdp4_dsi_video_on(struct platform_device *pdev)
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vctrl->mfd = mfd;
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vctrl->dev = mfd->fbi->dev;
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vctrl->blt_ctrl = pinfo->lcd.blt_ctrl;
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/* mdp clock on */
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mdp_clk_ctrl(1);
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@@ -1053,8 +1055,41 @@ static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
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spin_unlock_irqrestore(&vctrl->spin_lock, flag);
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return;
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}
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spin_unlock_irqrestore(&vctrl->spin_lock, flag);
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if (vctrl->blt_ctrl == OVERLAY_BLT_SWITCH_TG_OFF) {
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int tg_enabled;
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pr_info("%s: blt enabled by switching TG off\n", __func__);
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vctrl->blt_change = 0;
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tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;
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if (tg_enabled) {
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mdp4_dsi_video_wait4dmap_done(0);
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MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
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msleep(20);
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mipi_dsi_controller_cfg(0);
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}
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mdp4_overlayproc_cfg(pipe);
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mdp4_overlay_dmap_xy(pipe);
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if (tg_enabled) {
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if (pipe->ov_blt_addr) {
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/* preefill on frame */
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spin_lock_irqsave(&vctrl->spin_lock, flag);
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pipe->ov_cnt++;
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vctrl->ov_koff++;
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mdp4_stat.kickoff_ov0++;
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INIT_COMPLETION(vctrl->ov_comp);
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vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
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outpdw(MDP_BASE + 0x0004, 0);
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spin_unlock_irqrestore(&vctrl->spin_lock, flag);
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mdp4_dsi_video_wait4ov(cndx);
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}
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mipi_dsi_sw_reset();
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mipi_dsi_controller_cfg(1);
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MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
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}
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}
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}
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void mdp4_dsi_video_overlay_blt(struct msm_fb_data_type *mfd,
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@@ -1108,7 +1143,6 @@ void mdp4_dsi_video_overlay(struct msm_fb_data_type *mfd)
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mutex_lock(&mfd->dma->ov_mutex);
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mdp4_dsi_video_pipe_commit(0, 0);
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mutex_unlock(&mfd->dma->ov_mutex);
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if (pipe->ov_blt_addr)
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mdp4_dsi_video_wait4ov(0);
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@@ -1116,5 +1150,5 @@ void mdp4_dsi_video_overlay(struct msm_fb_data_type *mfd)
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mdp4_dsi_video_wait4dmap(0);
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mdp4_overlay_mdp_perf_upd(mfd, 0);
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mutex_unlock(&mfd->dma->ov_mutex);
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}
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@@ -65,6 +65,7 @@ struct lcd_panel_info {
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__u32 v_pulse_width;
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__u32 hw_vsync_mode;
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__u32 vsync_notifier_period;
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__u32 blt_ctrl;
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__u32 rev;
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};
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