Since the arch_timer is a system-wide block, other hardware in an SoC
can make use of the counter values. Export a way to read the physical
counter for use by other drivers.
Change-Id: I0bcd95fa4cd7507c41ac608fc9740955d15d4b88
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
Remove modem_wake and from_idle parameters from msm_gic_save
API since they are not used at all.
Change-Id: Icd1a83aea6b0eb988c19ccdbaf65b1f5be9e8ac2
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Certain version of the Krait processor require a specific
code sequence to be executed prior to executing a WFE
instruction to permit that instruction to place the
processor into a low-power state.
Change-Id: I308adc691f110a323cbd84e9779675ac045826fa
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Refactor the inline assembly code in spinlock.h in
preparation for supporting the Krait safe WFE sequence.
Change-Id: I2db4f823c39b164e04673f44cea916e334a20c9a
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Remove the condition argument from the WFE macro in the
spinlock code so it can support a WFE fixup needed on
certain Krait CPUs.
Change-Id: I8b4f85f0e7c130dff1e14fe275fda14a43e6f3f4
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
This patch adds support for CMA to dma-mapping subsystem for ARM
architecture. By default a global CMA area is used, but specific devices
are allowed to have their private memory areas if required (they can be
created with dma_declare_contiguous() function during board
initialisation).
Contiguous memory areas reserved for DMA are remapped with 2-level page
tables on boot. Once a buffer is requested, a low memory kernel mapping
is updated to to match requested memory access type.
GFP_ATOMIC allocations are performed from special pool which is created
early during boot. This way remapping page attributes is not needed on
allocation time.
CMA has been enabled unconditionally for ARMv6+ systems.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Michal Nazarewicz <mina86@mina86.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Rob Clark <rob.clark@linaro.org>
Tested-by: Ohad Ben-Cohen <ohad@wizery.com>
Tested-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Tested-by: Robert Nelson <robertcnelson@gmail.com>
Tested-by: Barry Song <Baohua.Song@csr.com>
Conflicts:
arch/arm/include/asm/mach/map.h
arch/arm/mm/init.c
arch/arm/mm/mm.h
arch/arm/mm/mmu.c
Change-Id: I85e3b43a9fa1e3c4d33cbc85fff6dee1b815041d
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
msm_gic_save/restore APIs were added to save the context of the
GIC across the apps. power collapse since 8625 PM framework
doesn't use the CPUIdle framework of the kernel. If the CPUIdle
framework was in use then we could have used the GIC driver provided
notification mechanism which takes of calling appropriate functions.
There is no need to protect these APIs using this #ifdef since there
is nothing specific to 8625 inside, also add empty functions for save
and restore since not all targets have CPU_PM defined.
Change-Id: I02bb4e4021c31caf7ab1282fb675d45ffba42a66
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
As per sd spec, if a sd card initialized in UHS mode needs to be
reinitialized, then the card should be powered off and then powered
on before proceeding with initialization again. Otherwise the sd
card reports it does not support UHS mode and can't be initialized as
an UHS card.
Currently sd card could be left powered on either because its regulator
is marked as always on or because the sd card was not run-time suspended
at the time of reboot. As a result on reboot, the sd card is not detected
as an UHS card. In order to prevent this the sd card is powered off and
then powered on at boot time.
CRs-fixed: 369644
Change-Id: Ic44fa005a1ac2d59d174b320e5e80dd5323876c3
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
This reverts commit 0bb2b56f7048b2f85be6784eaa8e4a5f0fa8688d.
This change is no longer necessary as of the following change,
since now we only preallocate 16 IRQs for SPARSE_IRQ
configurations. Thus the original problem of the system wasting
descriptions due to preallocated irqs no longer exists.
Author: Rob Herring <rob.herring@calxeda.com>
Date: Tue Jan 3 15:17:23 2012 -0600
ARM: only include mach/irqs.h for !SPARSE_IRQ
This also reverts commit ce4b20b3d79cb2785527fa36620252dac23b5259.
Since the preallocation scheme has been removed, we need to
update the board file to remove the old preallocation
specification.
Change-Id: I8fd819ae81fa0c8276877c0614653b5e5e14b3e2
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Rename gic_is_spi_pending and gic_clear_spi_pending APIs
to generic gic_is_irq_pending and gic_clear_irq_pending names
since this API could be used for anyother interrupts, and while
at it also use proper style for the multi-line comments around
these APIs.
Change-Id: I7d440f3caa0ebc77483d1ba43eff7932d5ac6666
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Extend ARM perf to check if PMU's have any special
constraints for adding events.
e.g. MSM PMU's have column exclusion constraints
that restrict adding events from the same register
and same group.
Change-Id: I36ea093c523f90f083d66dc6995e66cd77129bbd
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Upgrade the perfevents API of 8660 L2CC PMU to work with
the newer infrastructure.
Change-Id: Ib3dc966455f6f4bb680a222c458551b90cfb6b70
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Update the L2CC PMU perf code for 8960 to work with
the new 3.4 perf infrastructure.
Change-Id: I7c1246d6576b6beccd0b928c29de6160979ae23f
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
dfab_clk is used to vote for SDCC AHB clock derived
from Dayatona fabric. This naming convention is invalid
for targets where the AHB clocks are derived from other
buses like peripheral NoC. Hence, rename this to a generic
name that is applicable for all targets.
Change-Id: I9563342f07430cc000c86a93d265ff126003c8a5
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
The current arch_timer only support accessing through CP15 interface.
Add support for ARM processors that only support IO mapped register
interface.
Change-Id: Ide8be070d21609a2b1f4d6f0e0df1a27e6d978ff
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Add build id detection to enable the interleave mode feature in the driver.
In the interleave mode image ( boot, userdata etc ) codewords are written
to the NAND devices in a interleave fashion. Hence modem and apps should
operate in the same mode to read/write the images properly.
Change-Id: Ie9182eadd5750662dde07abfe793b4d231cf0ae1
Signed-off-by: Murali Nalajala <mnalajal@qualcomm.com>
(cherry picked from commit e80fa943d6aba79406c5793c84c5afa076a84e0c)
Conflicts:
arch/arm/mach-msm/board-msm7x30.c
arch/arm/mach-msm/devices-msm7x30.c
drivers/mtd/devices/msm_nand.c
For the Nand controller on 7x30 and 7x27a, the
uncorrectable error bit in the NANDC_BUFFER_STATUS
register is changed to BIT(8) from BIT(3) (in legacy
targets) due to change in the ECC requirements. Currently,
this is handled only in dual nandc mode (default for 7x30
and 7x27a). In case, if only single nandc is used, the
uncorrectable bit check is broken and the driver wouldn't
detect any ECC errors.
Add software version info in platform data to differentiate
between the targets that have different register interface.
CRs-Fixed: 365433
Change-Id: I3c33ccb0e936e262116dd20798d56530dbae900f
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
(cherry picked from commit ec9b3250fe233e4ff96b4ad23372df5f8299fc67)
Conflicts:
arch/arm/mach-msm/devices-9615.c
arch/arm/mach-msm/devices-msm7x27a.c
arch/arm/mach-msm/devices-msm7x30.c
Fix NR_IPI to be 7 instead of 6 because both googly and core add
an IPI.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Conflicts:
arch/arm/Kconfig
arch/arm/common/Makefile
arch/arm/include/asm/hardware/cache-l2x0.h
arch/arm/mm/cache-l2x0.c
arch/arm/mm/mmu.c
include/linux/wakelock.h
kernel/power/Kconfig
kernel/power/Makefile
kernel/power/main.c
kernel/power/power.h
Clean the #if nesting by using the COHERENT_IS_NORMAL flag. Introduce a
compiler barrier() in the pre case when COHERENT_IS_NORMAL is 0 and arch is
not coherent. Note that for Xscale we will have to force dmb() as it uses
kmalloc for coherent memory.
Change-Id: I1753fc62f5dfa3333c65269ab1815cd29e5698f7
Signed-off-by: Abhijeet Dharmapurikar <adharmap@quicinc.com>
(cherry picked from commit 496709819ea8e94acd3b781bd64dc54eba940226)
Conflicts:
arch/arm/include/asm/dma-mapping.h
arch/arm/include/asm/pgtable.h
Coherent memory in ARMv6+ could be StronglyOrdered or Normal. On ARMv7
StronglyOrdered guarantees program order execution only within 1KB and
Normal memory could have speculative fetches on them. Hence we need
barrier operations before and after dma for coherent memory.
Signed-off-by: Abhijeet Dharmapurikar <adharmap@quicinc.com>
Change-Id: I33a5f37af7114a7bf13d6b6706c4eca1340b5e41
(cherry picked from commit 32d12f613584053674ed6064a98aa2515aece9a0)
The subarchitecture field in the fpsid register is 7 bits wide.
The topmost bit is used to designate that the subarchitecture
designer is not ARM.
This change has the side effect of causing VFP implementations
other than ARM to be reported as VFPv3 with common VFP subarch
v3. Before this change it would be reported as VFPv1 with
an implementation defined subarchitecture.
CRs-Fixed: 268685
Change-Id: If304d284e2a104202b617ede86942bc89de0fb45
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
The gic_set_irq_secure function can be called from drivers
that are also compiled for targets which use an interrupt
controller other than GIC.
Add empty stub for this function to prevent compilation errors.
Change-Id: Ie3ab3a704b238751cd0dadf800d7e9b90ad257e7
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
(cherry picked from commit 4a771c59914d20b8fe234ceac2129be017052178)
Conflicts:
arch/arm/include/asm/hardware/gic.h
Most of the readl/writel macros for logging to the RTB
very similar. Create a dedicated macro to use for all of them
to make the code more readable and easier to maintain.
Change-Id: I6d8e7bc6bde7de6ad6cb53107362512d083b7423
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
(cherry picked from commit 9fba2a57b6f9f7d616bc0cb0aa41613240269f90)
Log readl/writel accesses in the small uncached buffer.
readl/writel are typically used for reading from memory
mapped registers, which can cause hangs if accessed
unclocked. Log this information in a buffer to aid in
debugging.
Change-Id: Id72da6b028a3faf5d0d8e069e14d90e4671e3564
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
(cherry picked from commit 0f9c7767132eed7f8a701f5281866aafa659632f)
Conflicts:
arch/arm/include/asm/io.h
arch/arm/mach-msm/include/mach/msm_rtb.h
arch/arm/mach-msm/include/mach/uncompress.h
Some CPUs perform speculative fetches. This may occur while a region of
memory is being written via DMA, so that region must be invalidated when
it is brought under CPU control after the DMA transaction finishes,
assuming the DMA was either bidirectional or from the device.
Signed-off-by: Dima Zavin <dima@android.com>
(cherry picked from commit fe79fc554afbfaa2652542129fb7380f4f7c4934)
Conflicts:
arch/arm/include/asm/dma-mapping.h
Change-Id: Id2a66fe567066a9301859b897d540885667253e6
For smp, barriers are required when a mutex lock is acquired or
released. Mutex slowpath routines already contain the necessary
barriers.
Change-Id: I774fc6e7bd5b1db9a0f51dee456b71c569cd512e
Signed-off-by: Brent DeGraaf <bdegraaf@codeaurora.org>
(cherry picked from commit 62c6b43d05a6aab278eb7d5d0030bd731b7684ea)
bank_pfn_end macro overflows when physical memory space
configuration ends at 0xFFFFFFFF.
The macro adds start and size together before converting
to a page frame number. Change the macro to convert start
and size first and then add them together.
Change-Id: If091fd860e6cc94f2221164bd79bf34415819e66
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
(cherry picked from commit b40b91eb8101b996f6dca5ccfee91b1949aa27e6)
The ARM generic timer now supports DT routines to parse the
device tree and populate its members, so remove this from
the board file and invoke the DT routine exposed from the
ARM generic timer.
Change-Id: Id383aff8f5f2c8fdb541f1df72242f8938229784
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit 2f27a173d075e9f5d6fa6c6705e56a6d101da024)
Conflicts:
arch/arm/boot/dts/msmcopper.dts
arch/arm/mach-msm/board-dt.c
Moving code which modifies the GIC registers. As there is no global
lock in gic code, moving the code out.
Change-Id: I85a2bd580dbeefc942a3307f3c0cad8b1da509b7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
(cherry picked from commit bc9248ab6fd94f9f5f2a818e7d8b67645b4310cb)
Conflicts:
arch/arm/common/gic.c
arch/arm/mach-msm/mpm-8625.c
arch/arm/mach-msm/platsmp-8625.c
Configure the GIC to run in secure mode and handle
secure as well as non-secure interrupts. This patch
adds an API to configure an IRQ as a secure IRQ so that
it can be treated as an FIQ in the secure mode.
Change-Id: Ic3321e76c95a4c10d6287ba418e84623e7004cb1
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit 26e44869e1e730ec7434e899dfd5857530b63415)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/gic.h
While in suspend state, the system should not wake up due to triggering
of a non wakeup interrupt. Implement suspend and resume functions to be
called from power management code to switch enabled interrupts between
wakeup set or normal set.
Change-Id: Iaceae286707460eadc5f05c0baef72b43c942777
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
(cherry picked from commit 3f2f06c6205445266aabdb9c843da70a4dd5d22f)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/gic.h
Some kernel code needs to check for and clear specific pending
interrupt explicitly. The polling and clearing may happen in
contexts where interrupts are masked off at the cpu level.
Change-Id: Icba9bb2f05e9fc61dd48c4174c4d276ab20b4244
Signed-off-by: Ai Li <aili@codeaurora.org>
(cherry picked from commit 20b3c0ee6e4852af8c52fb5f98188530760c8c74)
Conflicts:
arch/arm/include/asm/hardware/gic.h
Add support for the A15 generic timer and clocksource.
As the timer generates interrupts on a different PPI depending
on the execution mode (normal or secure), it is possible to
register two different PPIs.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Conflicts:
[Integrate to the recent patch which has changes to
local timer registration mechanism.
This fixes the crash seen during hotplug operations
where after a secondary CPU is brought back online,
the clock event device setup was happening as part
of the online notification mechanism which was too
late. With this change in the local timer mechanims,
the clock event device is now setup as part of the
secondary CPU boot initialization making it available
early enough for use.
Update the board file with the appropriate changes in
the argument for timer registration.]
arch/arm/Kconfig
arch/arm/include/asm/arch_timer.h
arch/arm/kernel/arch_timer.c
arch/arm/kernel/smp.c
Change-Id: I0bc80097c145fb2aac2150db0c5dff3c5e215a58
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit df590ccd9d8210cc3e059671efad06dab7e70d4c)
Change-Id: Iedac55e097b8d983c42799b98f2d11f7b1a95f04
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
The commit 292b293 creates the MSM boot failures, so squash
the commit 28af690 with it to avoid such failures. The commit ddd847
and 0c1991 are required to keep the watchdog and Copper targets working.
commit 292b293cee
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Wed Jul 20 16:24:14 2011 +0100
ARM: gic: consolidate PPI handling
PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).
Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.
This also allows the removal of some duplicated code.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit 28af690a28
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Fri Jul 22 12:52:37 2011 +0100
ARM: gic, local timers: use the request_percpu_irq() interface
This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).
PPIs are now useable for more than just the local timers.
Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).
Cc: David Brown <davidb@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit ddd8478d68f8cf75ee9771667c0cbe2a9d1caeb9
Author: Trilok Soni <tsoni@codeaurora.org>
Date: Tue Dec 6 00:56:01 2011 +0530
msm: watchdog: Use request_percpu_irq() interface
Change-Id: I7c319344f6a7f7a7c70682ac87f5c385e56d130c
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
commit 0c19915e092214a4c17a9920c4c1f3d78610217d
Author: Sathish Ambley <sambley@codeaurora.org>
Date: Fri Dec 9 17:07:37 2011 +0530
arm: arch_timer: Use request_percpu_irq() API
Change-Id: Iee9b218d538f315cd884a47d95bcc0dcc49b0fe1
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
Change-Id: I7bbba706b1f2e55814be5891ed76063725c2bfb1
Signed-off-by: Ravi Kumar <kumarrav@codeaurora.org>
[tsoni@codeaurora.org: MSM specific fixes]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
(cherry picked from commit eecb28c59054b1b9d8b9f410a903f87c8eb1ac48)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/entry-macro-gic.S
arch/arm/include/asm/localtimer.h
arch/arm/include/asm/smp.h
arch/arm/include/asm/smp_twd.h
arch/arm/kernel/smp.c
arch/arm/kernel/smp_twd.c
arch/arm/mach-exynos4/include/mach/entry-macro.S
arch/arm/mach-exynos4/mct.c
arch/arm/mach-msm/board-8064.c
arch/arm/mach-msm/board-8960.c
arch/arm/mach-msm/board-copper.c
arch/arm/mach-msm/board-dt.c
arch/arm/mach-msm/devices-9615.c
arch/arm/mach-msm/devices-msm8x60.c
arch/arm/mach-msm/include/mach/entry-macro-qgic.S
arch/arm/mach-msm/msm_watchdog.c
arch/arm/mach-msm/timer.c
arch/arm/mach-omap2/include/mach/entry-macro.S
L2 cache settings for improving memory performance on msm8625.
To improve write bandwidth, L2 is forced to No-Write-Allocate
through L2_AUX_CTRL(Enable bit 23).
To improve read bandwidth, Prefech offset of 3(Bit 0-4)and
Double line fill(Bit 23, 30)are enabled through L2_PREFETCH_CTRL.
Change-Id: Ia05cc41f8dee65486af9b0b7269b7f5763b5a988
Signed-off-by: Prachee Ramsinghani <pracheer@codeaurora.org>
(cherry picked from commit 86b1f6566dedc2df8fa98808709bd003d437b6ff)
Conflicts:
arch/arm/mach-msm/devices-msm7x27a.c
This reverts commit a022290fe5165ffe4973355cb76556ce8c629d70.
Save the contents of the L2CC registers in l2x0_init itself as
they are not modified later.
CRs-Fixed: 356696
Change-Id: I05ec3bcce8d1e2f941a9ecbaae8c6598f52831c5
Signed-off-by: Taniya Das <tdas@codeaurora.org>
(cherry picked from commit 38a8c6e63b1478cc520c795e07cd1b6370901d06)
Conflicts:
arch/arm/include/asm/hardware/cache-l2x0.h
arch/arm/mach-msm/pm-8x60.c
arch/arm/mach-msm/pm2.c
arch/arm/mm/cache-l2x0.c
Adds a function to encapsulate the locking, removal of write-protection,
word write, cache flush and invalidate and restoration
of write protection. This is a convenience function for callers
needing to update a word in kernel text space.
Change-Id: I9832f0ff659ddc62c55819af5318c94b70f5c11c
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
(cherry picked from commit 32942757bdfb3c67af2cd9c30427adf7d722f7c8)
STRICT_MEMORY_RWX write-protects the kernel text section. This
is a problem for tools such as kprobes which need write access
to kernel text space.
This patch introduces a function to temporarily make part of the
kernel text space writeable and another to restore the original state.
They can be called by code which is intentionally writing to
this space, while still leaving the kernel protected from
unintentional writes at other times.
Change-Id: I879009c41771198852952e5e7c3b4d1368f12d5f
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
(cherry picked from commit f06ab97f06fe6e8b3141434695b235e673f5ae37)
Conflicts:
arch/arm/mm/mmu.c
If CONFIG_STRICT_MEMORY_RWX is set, make kernel text RX,
kernel data/stack RW and rodata RO so that writing
on kernel text, executing kernel data or stack, or
writing on or executing read-only data is prohibited.
Change-Id: Ib2242c20dabddb63ef3f5655d5794fe418cb6287
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>
(cherry picked from commit 5a5305e90d4204fdf0586fbbd9a19b92181e74ea)
Conflicts:
arch/arm/mm/mmu.c
