Bottom 8 bits [7:0] of ETMSYNCFR are reserved on Krait pass3. This
means only bits [11:8] are valid since bits [31:12] are specified
as reserved by PFTv1.1 specification.
Use an appropriate value for the synchronization frequency in light
of this change on Krait pass3.
Change-Id: I5f32ad6546fc8a72e0a222cc90e0f23c9779ee3c
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
LPASS and MSS have different requirements related to the order that
their clocks are enable/disabled and resets are asserted/de-asserted.
Currently, this causes 'clock stuck off' warnings in the kernel logs
when MSS is booted multiple times.
Fix this by reordering the MSS clock calls so that the core_clk reset
is de-asserted prior to enabling its iface_clk. Because doing this
would break LPASS (which requires iface_clk to be on for the core_clk
reset de-assertion to work), we are forced to separate the MSS and
LPASS clock sequences into separate functions and move them into their
respective PIL files.
MSS PIL also requires an additional clock that is added as part of
this fixup. The gcc_mss_q6_bimc_axi_clk is needed for the MSS Q6
to access memory.
Change-Id: Id877781f201a7267f72b52045ed2b87ebf7b4e05
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
The MSS subsystem needs the gcc_mss_q6_bimc_axi_clk to be turned
on to allow the modem Q6 to access DDR. Add support for this
clock.
Change-Id: I2fe0d8740143d8f18eb5c8770bc4c4b07339c060
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
When notify packet transfer failed, notify_count and cpkt_resp_q
would go out of sync. After the fix the packets are also removed from
the queue.
Change-Id: If33ea5070f460617179a77063a9e58c47ed93167
CRs-Fixed: 383661
Signed-off-by: Anna Perel <aperel@codeaurora.org>
We get the error message for the incorrect aspect ratio
with each frame of the video. By reducing the priority,
error message will appear only when we enable it.
Change-Id: Iacb8002383ea6c0b7ee86e9cfe14478c0e5ca5c3
Signed-off-by: Rajeshwar Kurapaty <rkurapat@codeaurora.org>
Maximum allowed size of BAM descriptor is 32K-1, the size
allocated by demux was changed accordingly. Notifications
from TSPP driver is set based on number of descriptors and
not on number of bytes.
TSIF buffer was enlarged to cope with 80Mbit/sec streams
Change-Id: Ic9a9f0a5144293ac30e5548bbbb4d284d72c3a9e
Signed-off-by: Hamad Kadmany <hkadmany@codeaurora.org>
Enable OCMEM power debug and OCMEM power control
disable mode until all power operations are verified with RPM.
Change-Id: I915ef53d1b84344f3cdef8f45f94eafa067b0172
Signed-off-by: Naveen Ramaraj <nramaraj@codeaurora.org>
This clock must be enabled for the LPASS Q6 to access the memory
from which it will execute.
Change-Id: I1bdd4d8fb32d85c28296de3827f70505be7ee70e
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
The PIL driver needs to enable a clock required by the
LPASS subsystem. Add support for this clock.
Change-Id: I38ecf1ce84939967b633b0ef37b764893ec19252
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
The slimbus driver needs a frequency of 24.576 MHz from their
core clock.
Change-Id: Ic978bfb47f944778613954db12d7b373b7e8751f
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
With the full boot chain, the secondary CPUs are held in
reset until the primary CPU explicitly releases them from
reset.
Change-Id: Ie2a9f235386133d570dc826fe1cf5b44587a0706
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The GCC_BOOT_CLOCK_* register forces on certain USB and Krait
clocks. Clearing these registers is causing unclocked accesses
or possibly removing the clock from under the CPU. Temporarily
leave these registers alone.
This reverts commit fc3c55c65927f977185969f9b01b4b6e391f78ac.
Change-Id: I32e5dbcce94c931e1c56a42483e6cdeca479f055
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The FSM targets need to use the Watchdog1 timer instead of the
Watchdog0 timer. Add support to get the base and the interrupt
information from the platform data so that the watchdog driver
can support both WDT0 and WDT1.
Change-Id: Ibce013c0287e34dbd702d75dab2c3f321132e9ed
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
The mentioned device data entries were defined earlier in a patch but
does not match the relevant documentation. In due course of merging/
auto-rebasing on the initial patch (that added these entries), the
changes in this file was replaced with the incorrect ones, which got
merged.
This patch corrects the entries as per the documentation by doing the
following:
-Add reg-names to refer to the crypto register base and bam register
base.
-Rename "bam-pipes" to "bame-pipe-pair".
Change-Id: I47974b3c12500ca70ea46fcd58841af741461004
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
This allows the clock selected for measurement to be observed
using test equipment attached to the PLL_TEST pin on the MSM.
Change-Id: I91384690e0979cbd51d5fe2ff417ceb711d01a11
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Add thermal monitoring and mitigation to kernel boot on msm8974
to prevent thermal conditions during boot time.
Change-Id: I9db10a4a69772fdcb8f2a450044ce446da8b593c
Signed-off-by: Eugene Seah <eseah@codeaurora.org>
The documentation followed to enumerate the subtype values was
found to differ from the actual implementation in hardware.
Update to the values actually found in the hardware.
Change-Id: I3a6d3027593bfb043b87d9c072c882981c649a6e
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
This reverts commit a1cc890f04279b8e13b20cd3b3bceeb0d28a4e9b.
Bus scaling is known to break on Rumi.
Change-Id: I7d66469aa8a32d8cd9594e4fad8b4da6039479ad
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Have STM hardware event and port enable sysfs nodes to allow users to
selectively enable and disable either hardware events or stimulus
ports while STM as a whole is enabled.
Change-Id: I32c23f62a3782487e67eb5e6a9da5a5bf7e11df8
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Dup ftrace event traffic (including writes to trace_marker file from
userspace) to STM. Also dup printk traffic to STM. This allows Linux
tracing and log data to be correlated with other data transported over
STM.
Change-Id: Ieb0b856447f7667eb0005a6a884211dc46f50217
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Provide CoreSight abort debug api to stop the active trace sink
from any context. This is a best effort api that can be used to
abruptly stop and disable the current trace sink from anywhere
in the kernel to avoid tracing and hence polluting the trace data
after the point of interest has been executed.
Change-Id: I34c528d9febec4265088a7267dbcf0e7a1f87fcf
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
This driver manages CoreSight TMC (Trace Memory Controller) which
can be pre-configured as an ETF (Embedded Trace FIFO) or ETR
(Embedded Trace Router). ETF when configured in circular buffer mode
acts as an ETB (Embedded Trace Buffer).
Change-Id: I1ca40e1fbd3049dc7addb834c064ab3a6c4c22e0
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add CoreSight component devices (sinks, links and sources) to the
msm8974 device tree. CoreSight devices provide tracing support for
the SoC.
Change-Id: I33c4d3adff45c263b36141f1158434d9c83f0662
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add additional main-mux voltage channels to read ADC
from VADC USRP peripheral. The new channels have different
pre-div scaling compared to previous channel voltage node.
The new channel nodes include support to read vbatt, vcharger
that can be used by the battery driver. In addition, the
625mV and 1.125V channel nodes are added to verify the
reference channels used for absolute calibration.
Change-Id: I53265a00b95ba4f5fb726731532070b8b758d86a
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
The debugfs TRRS entry is for overriding headset button polling.
Fix regression not to start button polling when this flag is set.
CRs-fixed: 386038
Change-Id: I469c366bc111f37ecbb46708d2800200dd3d7584
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Some of accessories on the headset jack takes longer to settle down
voltage. Make adjust time to be configurable so those accessories can
be detected correctly.
Change-Id: I3c2f68c8a4bb1a8f94669bd910728f014ee39874
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
The graphics driver wishes to set the rate on the gfx3d_clk_src
via the oxili_gfx3d_clk. Add a voter clock for the ocmemgx_clk
and set this new clock as the parent of oxili_gfx3d_clk.
Change-Id: I8e469b93d88f0c71b51e95807db90a97240a9e06
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
The RPM-SMD driver and the correponding communication protocol
with the RPM does not currently support querying of clock rates.
Allow handoff to always succeed for RPM-SMD clocks. Previously,
the older RPM driver API stub would always return failure
causing RPM handoff to fail.
Change-Id: I357430dec06a2305cdad2af4c213a3b98965e1e1
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
To be able to access certain audio core registers, the
audio_core_ixfabric_clk needs to be on. Turn it on in
post_init.
Change-Id: I29ab8a80bb01696f362d97f98f53538c85f29a18
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
The GCC_BOOT_CLOCK_* registers allow the boot code to
forcefully turn on certain USB and Krait clocks. Clear
a bit in these registers to be able to turn those clocks
off.
Change-Id: I58671ac9bd0af72fd13f8ee0171979bb2a954348
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
The LPASS debug mux index in the GCC top level mux
and the bit to activate the debug mux output have
been updated in documentation. Update the code to
reflect this.
Change-Id: Iad40c91ddba756a0fad455b93bf0f725ff27eae6
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
The 1536000 rate has an incorrect n value. Correct this.
Change-Id: I018aa4677c05db0c25d994c150689a61296e9eeb
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
If the MBA encounters an error, it puts a negative error code
number in its status register. Rather than just detecting this
and failing, print the error number to assist with debugging.
Change-Id: I864b7eb19eb31dfd901a3e58dbcc0c8aba410c2e
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Add LDO 13 and LDO 25 configurations and contraints in
board-8930-regulator.c so that these regulators can be controlled
by regulator framework consumers.
Change-Id: Idd8bfd5bca1f8104a071b566d09fb9c756db8853
CRs-Fixed: 385569
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add configuration data for PMIC PM8038 LDO 13 (VREG_XO) and
LDO 25 (VREG_RF_CLK) so that these regulators may be controlled
via the RPM.
Change-Id: Idcc81617dc40c37b4e7493cfb3febd4946815150
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add Taiko codec to device tree so that platform specific data
can be read from device tree.
Change-Id: I8b470bb7f40925baec95fff5fd08be5eb04b3a84
Signed-off-by: Kiran Kandi <kkandi@codeaurora.org>
In reset function, venus internal clocks need to be on to access some of
the iommu registers. Fix the order to turn on the internal clocks and then
program iommu.
In the shutdown function, iommu unmap and detach should be done before
halting AXI and AXI OCMEM VBIF access. Otherwise, the iommu TLB flush can't
go through. In addition, to avoid iommu page faults due to ARM9 accessing
unmapped memory, reset to ARM9 must be asserted before unmapping and
detaching iommu.
Change-Id: I6df152fd63b5d0583b9660370310e7a9b80ab6a8
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
Support for reading hardware data for CoreSight devices from device
tree.
Change-Id: I4d149991c89b458384465d163386084f500a4028
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
The LPASS Audio Core GDSC needs to be on to unhalt various
audio core CBCs in the LPASS CC. Temporarily enable it.
Change-Id: Ie593e2b53a3eea89540d0feb308d23a8e5d2123f
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
If a panel probe does not succeed, call mdp_clk_ctrl to maintain
mdp_clk_cnt counter else mismatch in counter results in mdp clock
to never go off in cases like suspend-resume.
CRs-Fixed: 385560
Change-Id: I4ca54b051af98e823dc7f3ff7b9bcb960532c7e8
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
Increase the upper limit for the pixel clock that
changed with the newer version of the DSI controller.
CRs-Fixed: 380003
Change-Id: Ibbeaa478b4d12ae8f350be41f959d53a6ae6c923
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Using RGB888 as source format and rgb565 as destination pixel format,
will cause image corruption on the display. Fix this issue by
setting the destination format as RGB888 in MDP and DSI controller
pixel format as RGB565 for DSI specific panels.
CRs-Fixed: 377484
Change-Id: If58976ee9cd4825efb39437170e54796fa2213e0
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Add devices for the PMIC that match against the qpnp-regulator
driver for all supported regulator devices from the apps side.
Remove most devices from the rpm_bus with the exception of the
devices that acpuclock is currently using. These need to stay
since acpuclock is calling rpm_regulator_get() that is only
available on the rpm-regulator driver.
For regulators that are duplicates between rpm and local, rename
the local names to end if a suffix of "_local" to make them
unique. With the absense of a RPM, these RPM devices will amount
to NOPs at runtime.
This switch to local control is temporary and will be reverted
once the RPM regulator support has been validated on 8974 CDP.
Change-Id: Ie50db44595e487dcad659e67d623d32f4883d987
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Low power mode is not supported as of now on targets which are
using device tree. Revert this later when support is in place.
Change-Id: I05d6089d037312a0e719f4263093bde730c3a8ad
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
This is required to support console on
JTAG debuggers.
Change-Id: If9d1d26f1800ab40c57fcb79e249eea6936ab6fe
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The mmss_s0_axi clock needs to be turned on to allow MMSS NOC
slaves to be able to access memory across the MMSS NOC and
System NOC interconnect. However, this clock needs the
mmssnoc_axi_clk to be on for the NOC handshake to work.
Therefore, have the bus driver turn on the mmss_s0_axi_clk when
there are bandwidth requests for the MMSS NOC AXI clock and have
mmss_s0_axi_clk depend on the mmssnoc_axi_clk.
Change-Id: I81d0dc27ea7a7983ddbebbfff67c3426b3c6da94
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
