This reverts commit f27e4f0e730b99ca4dabed0b408d96dbf73a8fac.
With 01b1dee in system/core to set ADDR_COMPAT_LAYOUT, this is
not needed any longer.
Bug: 8470684
Signed-off-by: Ajay Dudani <adudani@codeaurora.org>
Acked-by: Laura Abbot <lauraa@codeaurora.org>
Commit a76d7bd96d65 ("ARM: 7467/1: mutex: use generic xchg-based
implementation for ARMv6+") removed the barrier-less, ARM-specific
mutex implementation in favour of the generic xchg-based code.
Since then, a bug was uncovered in the xchg code when running on SMP
platforms, due to interactions between the locking paths and the
MUTEX_SPIN_ON_OWNER code. This was fixed in 0bce9c46bf3b ("mutex: place
lock in contended state after fastpath_lock failure"), however, the
atomic_dec-based mutex algorithm is now marginally more efficient for
ARM (~0.5% improvement in hackbench scores on dual A15).
This patch moves ARMv6+ platforms to the atomic_dec-based mutex code.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The open-coded mutex implementation for ARMv6+ cores suffers from a
severe lack of barriers, so in the uncontended case we don't actually
protect any accesses performed during the critical section.
Furthermore, the code is largely a duplication of the ARMv6+ atomic_dec
code but optimised to remove a branch instruction, as the mutex fastpath
was previously inlined. Now that this is executed out-of-line, we can
reuse the atomic access code for the locking (in fact, we use the xchg
code as this produces shorter critical sections).
This patch uses the generic xchg based implementation for mutexes on
ARMv6+, which introduces barriers to the lock/unlock operations and also
has the benefit of removing a fair amount of inline assembly code.
Cc: <stable@vger.kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Nicolas Pitre <nico@linaro.org>
Reported-by: Shan Kang <kangshan0910@gmail.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When a CPU is hotplugged out while a perf session
is active, disarm the IRQ when the CPU is preparing
to die. This ensures that perf doesn't lock up when
it tries to free the irq of a hotplugged CPU.
Similarly, when a CPU comes online during a perf session
enable the IRQ so that perf doesn't try to disable
an unarmed IRQ when it finishes.
Change-Id: Ic4e412e5f1effae0db34a3e4b5e7e5c65faed2a0
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
This is in preparation for adding support for the unicore A5
and dualcore A5, both of which have the same MIDR value.
Instead of adding extra parsing to the ARM generic perf_event file,
this patch moves it to the 'mach' directory where targets types
can be detected in an implementation specific manner.
The default behavior is maintained for all other ARM targets.
Change-Id: I041937273dbbd0fa4c602cf89a2e0fee7f73342b
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Since the L1CC PMU's are per CPU, the variable to detect if a CPU
came out of powercollapse also needs to be a per CPU variable. This
ensures that we reset and restore the correct CPU's PMU counters.
Change-Id: I02273df2eff9f6d88d68f46a7752c107b290a8ef
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
A killed task can stay in the task list long after its
memory has been returned to the system, therefore
ignore any tasks whose mm struct has been freed.
Change-Id: I76394b203b4ab2312437c839976f0ecb7b6dde4e
CRs-fixed: 450383
Signed-off-by: Liam Mark <lmark@codeaurora.org>
Move cp14.h to include/asm/hardware so that it can be used by code
inside mach-msm as well as drivers/coresight.
Change-Id: I3f5cd6e1768378ec26abcd1e7328977836dce60f
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Currently, the only attributes supported for DMA memory are
writecombine and coherent. Both of these allow speculative
prefetches to occur. For certain use cases (e.g. content
protection) there are requirements to disallow prefetching.
Relatedly, there may be cases where buffering is not enough
for high performance use cases and the full cache should
be used. Add appropriate APIs for the strongly ordered and
cached memory types for the needed use cases.
Change-Id: Ibe17b3d002f9615e2cb34183f47f6d1bcd045611
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
This patch add a complete implementation of DMA-mapping API for
devices which have IOMMU support.
This implementation tries to optimize dma address space usage by remapping
all possible physical memory chunks into a single dma address space chunk.
DMA address space is managed on top of the bitmap stored in the
dma_iommu_mapping structure stored in device->archdata. Platform setup
code has to initialize parameters of the dma address space (base address,
size, allocation precision order) with arm_iommu_create_mapping() function.
To reduce the size of the bitmap, all allocations are aligned to the
specified order of base 4 KiB pages.
dma_alloc_* functions allocate physical memory in chunks, each with
alloc_pages() function to avoid failing if the physical memory gets
fragmented. In worst case the allocated buffer is composed of 4 KiB page
chunks.
dma_map_sg() function minimizes the total number of dma address space
chunks by merging of physical memory chunks into one larger dma address
space chunk. If requested chunk (scatter list entry) boundaries
match physical page boundaries, most calls to dma_map_sg() requests will
result in creating only one chunk in dma address space.
dma_map_page() simply creates a mapping for the given page(s) in the dma
address space.
All dma functions also perform required cache operation like their
counterparts from the arm linear physical memory mapping version.
This patch contains code and fixes kindly provided by:
- Krishna Reddy <vdumpa@nvidia.com>,
- Andrzej Pietrasiewicz <andrzej.p@samsung.com>,
- Hiroshi DOYU <hdoyu@nvidia.com>
Change-Id: I4a9b155bef4d5f2b8a8dfe87751d82960b09b253
[lauraa: context conflicts]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Tested-By: Subash Patel <subash.ramaswamy@linaro.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
This patch converts dma_alloc/free/mmap_{coherent,writecombine}
functions to use generic alloc/free/mmap methods from dma_map_ops
structure. A new DMA_ATTR_WRITE_COMBINE DMA attribute have been
introduced to implement writecombine methods.
Change-Id: I2709e3ffc97546df2f505d555b29c3bb8148daec
[lauraa: context conflicts]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-By: Subash Patel <subash.ramaswamy@linaro.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
This patch removes dma bounce hooks from the common dma mapping
implementation on ARM architecture and creates a separate set of
dma_map_ops for dma bounce devices.
Change-Id: I42d7869b4f74ffa5f36a4a7526bc0c55aaf6bab7
[lauraa: conflicts due to code cruft]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-By: Subash Patel <subash.ramaswamy@linaro.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
This patch modifies dma-mapping implementation on ARM architecture to
use common dma_map_ops structure and asm-generic/dma-mapping-common.h
helpers.
Change-Id: I574a3b5ac883cd5d9beb79deef8f5cb44fd83296
[lauraa: conflicts due to code cruft/context changes]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-By: Subash Patel <subash.ramaswamy@linaro.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Some device has problems in packed write for eMMC.
So we can set packed write feature in platform data.
Change-Id: I7e76c78fd076fa5cb0d540c1312fd6ae69aae1b4
This patch removes the need for the offset parameter in dma bounce
functions. This is required to let dma-mapping framework on ARM
architecture to use common, generic dma_map_ops based dma-mapping
helpers.
Background and more detailed explaination:
dma_*_range_* functions are available from the early days of the dma
mapping api. They are the correct way of doing a partial syncs on the
buffer (usually used by the network device drivers). This patch changes
only the internal implementation of the dma bounce functions to let
them tunnel through dma_map_ops structure. The driver api stays
unchanged, so driver are obliged to call dma_*_range_* functions to
keep code clean and easy to understand.
The only drawback from this patch is reduced detection of the dma api
abuse. Let us consider the following code:
dma_addr = dma_map_single(dev, ptr, 64, DMA_TO_DEVICE);
dma_sync_single_range_for_cpu(dev, dma_addr+16, 0, 32, DMA_TO_DEVICE);
Without the patch such code fails, because dma bounce code is unable
to find the bounce buffer for the given dma_address. After the patch
the above sync call will be equivalent to:
dma_sync_single_range_for_cpu(dev, dma_addr, 16, 32, DMA_TO_DEVICE);
which succeeds.
I don't consider this as a real problem, because DMA API abuse should be
caught by debug_dma_* function family. This patch lets us to simplify
the internal low-level implementation without chaning the driver visible
API.
Change-Id: I9a847e30f345bf5e69fded1747ff79057750fb66
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-By: Subash Patel <subash.ramaswamy@linaro.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
commit 7dbaa46678
(ARM: 7169/1: topdown mmap support) allocates mmap addresses from
the top addresses instead of the bottom. Unfortunately, some
userspace components are broken and do checks such as the following:
void* addr = mmap(...);
// Top bit is now the sign bit...
int test = (int)addr;
if (test < 0) {
//failure
}
Which means that any address greater than 0x80000000 will be marked
as a failure. Until we verify all userspace components are fixed,
revert this change.
Change-Id: I2eacbfb4f7b8fc9bf5704ca90d31c409819d7fbe
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Counters need to be individually re-enabled after the CPU
comes out of power collapse. Without this the counters
will simply be set to their MAX period and starting the PMU
will have no effect.
Change-Id: I3988a45277057eb80cf580b90ce697d0e6a00c43
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Disabling interrupts during the Krait WFE fixup can result
in deadlock if a thread tries to acquire a spinlock that is
released from an interrupt context. Instead of disabling
interrupts, modify the interrupt handler to reset the fixup
condition to put the processor into a safe state in the
event that the interrupt came in during the fixup window.
CRs-Fixed: 383670
Change-Id: Id504f46d6f840dc32ca11ed2f813003143e60f2d
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Since the arch_timer is a system-wide block, other hardware in an SoC
can make use of the counter values. Export a way to read the physical
counter for use by other drivers.
Change-Id: I0bcd95fa4cd7507c41ac608fc9740955d15d4b88
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
Remove modem_wake and from_idle parameters from msm_gic_save
API since they are not used at all.
Change-Id: Icd1a83aea6b0eb988c19ccdbaf65b1f5be9e8ac2
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Certain version of the Krait processor require a specific
code sequence to be executed prior to executing a WFE
instruction to permit that instruction to place the
processor into a low-power state.
Change-Id: I308adc691f110a323cbd84e9779675ac045826fa
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Refactor the inline assembly code in spinlock.h in
preparation for supporting the Krait safe WFE sequence.
Change-Id: I2db4f823c39b164e04673f44cea916e334a20c9a
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Remove the condition argument from the WFE macro in the
spinlock code so it can support a WFE fixup needed on
certain Krait CPUs.
Change-Id: I8b4f85f0e7c130dff1e14fe275fda14a43e6f3f4
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
This patch adds support for CMA to dma-mapping subsystem for ARM
architecture. By default a global CMA area is used, but specific devices
are allowed to have their private memory areas if required (they can be
created with dma_declare_contiguous() function during board
initialisation).
Contiguous memory areas reserved for DMA are remapped with 2-level page
tables on boot. Once a buffer is requested, a low memory kernel mapping
is updated to to match requested memory access type.
GFP_ATOMIC allocations are performed from special pool which is created
early during boot. This way remapping page attributes is not needed on
allocation time.
CMA has been enabled unconditionally for ARMv6+ systems.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Michal Nazarewicz <mina86@mina86.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Rob Clark <rob.clark@linaro.org>
Tested-by: Ohad Ben-Cohen <ohad@wizery.com>
Tested-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Tested-by: Robert Nelson <robertcnelson@gmail.com>
Tested-by: Barry Song <Baohua.Song@csr.com>
Conflicts:
arch/arm/include/asm/mach/map.h
arch/arm/mm/init.c
arch/arm/mm/mm.h
arch/arm/mm/mmu.c
Change-Id: I85e3b43a9fa1e3c4d33cbc85fff6dee1b815041d
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
msm_gic_save/restore APIs were added to save the context of the
GIC across the apps. power collapse since 8625 PM framework
doesn't use the CPUIdle framework of the kernel. If the CPUIdle
framework was in use then we could have used the GIC driver provided
notification mechanism which takes of calling appropriate functions.
There is no need to protect these APIs using this #ifdef since there
is nothing specific to 8625 inside, also add empty functions for save
and restore since not all targets have CPU_PM defined.
Change-Id: I02bb4e4021c31caf7ab1282fb675d45ffba42a66
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
As per sd spec, if a sd card initialized in UHS mode needs to be
reinitialized, then the card should be powered off and then powered
on before proceeding with initialization again. Otherwise the sd
card reports it does not support UHS mode and can't be initialized as
an UHS card.
Currently sd card could be left powered on either because its regulator
is marked as always on or because the sd card was not run-time suspended
at the time of reboot. As a result on reboot, the sd card is not detected
as an UHS card. In order to prevent this the sd card is powered off and
then powered on at boot time.
CRs-fixed: 369644
Change-Id: Ic44fa005a1ac2d59d174b320e5e80dd5323876c3
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
This reverts commit 0bb2b56f7048b2f85be6784eaa8e4a5f0fa8688d.
This change is no longer necessary as of the following change,
since now we only preallocate 16 IRQs for SPARSE_IRQ
configurations. Thus the original problem of the system wasting
descriptions due to preallocated irqs no longer exists.
Author: Rob Herring <rob.herring@calxeda.com>
Date: Tue Jan 3 15:17:23 2012 -0600
ARM: only include mach/irqs.h for !SPARSE_IRQ
This also reverts commit ce4b20b3d79cb2785527fa36620252dac23b5259.
Since the preallocation scheme has been removed, we need to
update the board file to remove the old preallocation
specification.
Change-Id: I8fd819ae81fa0c8276877c0614653b5e5e14b3e2
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Rename gic_is_spi_pending and gic_clear_spi_pending APIs
to generic gic_is_irq_pending and gic_clear_irq_pending names
since this API could be used for anyother interrupts, and while
at it also use proper style for the multi-line comments around
these APIs.
Change-Id: I7d440f3caa0ebc77483d1ba43eff7932d5ac6666
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Extend ARM perf to check if PMU's have any special
constraints for adding events.
e.g. MSM PMU's have column exclusion constraints
that restrict adding events from the same register
and same group.
Change-Id: I36ea093c523f90f083d66dc6995e66cd77129bbd
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Upgrade the perfevents API of 8660 L2CC PMU to work with
the newer infrastructure.
Change-Id: Ib3dc966455f6f4bb680a222c458551b90cfb6b70
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Update the L2CC PMU perf code for 8960 to work with
the new 3.4 perf infrastructure.
Change-Id: I7c1246d6576b6beccd0b928c29de6160979ae23f
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
dfab_clk is used to vote for SDCC AHB clock derived
from Dayatona fabric. This naming convention is invalid
for targets where the AHB clocks are derived from other
buses like peripheral NoC. Hence, rename this to a generic
name that is applicable for all targets.
Change-Id: I9563342f07430cc000c86a93d265ff126003c8a5
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
The current arch_timer only support accessing through CP15 interface.
Add support for ARM processors that only support IO mapped register
interface.
Change-Id: Ide8be070d21609a2b1f4d6f0e0df1a27e6d978ff
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Add build id detection to enable the interleave mode feature in the driver.
In the interleave mode image ( boot, userdata etc ) codewords are written
to the NAND devices in a interleave fashion. Hence modem and apps should
operate in the same mode to read/write the images properly.
Change-Id: Ie9182eadd5750662dde07abfe793b4d231cf0ae1
Signed-off-by: Murali Nalajala <mnalajal@qualcomm.com>
(cherry picked from commit e80fa943d6aba79406c5793c84c5afa076a84e0c)
Conflicts:
arch/arm/mach-msm/board-msm7x30.c
arch/arm/mach-msm/devices-msm7x30.c
drivers/mtd/devices/msm_nand.c
For the Nand controller on 7x30 and 7x27a, the
uncorrectable error bit in the NANDC_BUFFER_STATUS
register is changed to BIT(8) from BIT(3) (in legacy
targets) due to change in the ECC requirements. Currently,
this is handled only in dual nandc mode (default for 7x30
and 7x27a). In case, if only single nandc is used, the
uncorrectable bit check is broken and the driver wouldn't
detect any ECC errors.
Add software version info in platform data to differentiate
between the targets that have different register interface.
CRs-Fixed: 365433
Change-Id: I3c33ccb0e936e262116dd20798d56530dbae900f
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
(cherry picked from commit ec9b3250fe233e4ff96b4ad23372df5f8299fc67)
Conflicts:
arch/arm/mach-msm/devices-9615.c
arch/arm/mach-msm/devices-msm7x27a.c
arch/arm/mach-msm/devices-msm7x30.c
Fix NR_IPI to be 7 instead of 6 because both googly and core add
an IPI.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Conflicts:
arch/arm/Kconfig
arch/arm/common/Makefile
arch/arm/include/asm/hardware/cache-l2x0.h
arch/arm/mm/cache-l2x0.c
arch/arm/mm/mmu.c
include/linux/wakelock.h
kernel/power/Kconfig
kernel/power/Makefile
kernel/power/main.c
kernel/power/power.h
Clean the #if nesting by using the COHERENT_IS_NORMAL flag. Introduce a
compiler barrier() in the pre case when COHERENT_IS_NORMAL is 0 and arch is
not coherent. Note that for Xscale we will have to force dmb() as it uses
kmalloc for coherent memory.
Change-Id: I1753fc62f5dfa3333c65269ab1815cd29e5698f7
Signed-off-by: Abhijeet Dharmapurikar <adharmap@quicinc.com>
(cherry picked from commit 496709819ea8e94acd3b781bd64dc54eba940226)
Conflicts:
arch/arm/include/asm/dma-mapping.h
arch/arm/include/asm/pgtable.h
Coherent memory in ARMv6+ could be StronglyOrdered or Normal. On ARMv7
StronglyOrdered guarantees program order execution only within 1KB and
Normal memory could have speculative fetches on them. Hence we need
barrier operations before and after dma for coherent memory.
Signed-off-by: Abhijeet Dharmapurikar <adharmap@quicinc.com>
Change-Id: I33a5f37af7114a7bf13d6b6706c4eca1340b5e41
(cherry picked from commit 32d12f613584053674ed6064a98aa2515aece9a0)
The subarchitecture field in the fpsid register is 7 bits wide.
The topmost bit is used to designate that the subarchitecture
designer is not ARM.
This change has the side effect of causing VFP implementations
other than ARM to be reported as VFPv3 with common VFP subarch
v3. Before this change it would be reported as VFPv1 with
an implementation defined subarchitecture.
CRs-Fixed: 268685
Change-Id: If304d284e2a104202b617ede86942bc89de0fb45
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
