The platform data was requesting the wrong number,
it should request the first perf irq item.
Change-Id: I4a25b4704ed9e76172c6b0d4ca4b28a3286ab2ad
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
When a CPU is hotplugged out while a perf session
is active, disarm the IRQ when the CPU is preparing
to die. This ensures that perf doesn't lock up when
it tries to free the irq of a hotplugged CPU.
Similarly, when a CPU comes online during a perf session
enable the IRQ so that perf doesn't try to disable
an unarmed IRQ when it finishes.
Change-Id: Ic4e412e5f1effae0db34a3e4b5e7e5c65faed2a0
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
The MSM SoC's which have ARM's CPU's can power collapse. Ensure
the CPU side PMU's correctly restore the counters after coming
out of power collapse.
Change-Id: I544a1dd8ced26f726ba115d14867d9e34c2a7944
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
If the platform descriptor does not provide
its own free_irq function, default to the fallback
version.
Change-Id: I185186bf68b79e2dbfba77b0de66eb4daaf32fb8
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
The L2 perf code shares some resource reservation functions
with the L1 perf code. In these functions, use defaults
only if they're not defined for the L1 and L2.
Change-Id: I5a390aa0085694466800db78b51837556aa12cdd
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
This is in preparation for adding support for the unicore A5
and dualcore A5, both of which have the same MIDR value.
Instead of adding extra parsing to the ARM generic perf_event file,
this patch moves it to the 'mach' directory where targets types
can be detected in an implementation specific manner.
The default behavior is maintained for all other ARM targets.
Change-Id: I041937273dbbd0fa4c602cf89a2e0fee7f73342b
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
For ARMV7 based PMU's implemented outside Qcomm, default
to the generic IRQ handlers to maintain original behavior.
Change-Id: Ic65379104cc708460f2f84c00ea86c1e284bbd29
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Unicore targets can't use the percpu IRQ API,
so fallback to the generic versions of the functions
at init.
Change-Id: Id3db611fe4a7e0dcfbeb2f3ae08a5f7189132034
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Remove target name from IRQ string, since the percpu IRQ API
is shared with all Qcomm targets.
Change-Id: Id0e7d9267654b373e9360806900259e00bf5a0ab
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Since the L1CC PMU's are per CPU, the variable to detect if a CPU
came out of powercollapse also needs to be a per CPU variable. This
ensures that we reset and restore the correct CPU's PMU counters.
Change-Id: I02273df2eff9f6d88d68f46a7752c107b290a8ef
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
New ftrace events (user_fault and undef_instr) for data, prefetch
or undefined instruction aborts. The new ftrace events are under
events/exception.
Change-Id: Iea328b71a1f623861cac9b45d858c3bbe09e1b82
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Nothing stops a process from hotplugging in a CPU concurrently
with a sys_reboot() call. In such a situation we could have
ipi_cpu_stop() mark a cpu as 'offline' and _cpu_up() ignore the
fact that the CPU is not really offline and call the
CPU_UP_PREPARE notifier. When this happens stop_machine code will
complain that the cpu thread already exists and BUG_ON().
CPU0 CPU1
sys_reboot()
kernel_restart()
machine_restart()
machine_shutdown()
smp_send_stop()
... ipi_cpu_stop()
set_cpu_online(1, false)
local_irq_disable()
while(1)
<PREEMPT>
cpu_up()
_cpu_up()
if (!cpu_online(1))
__cpu_notify(CPU_UP_PREPARE...)
cpu_stop_cpu_callback()
BUG_ON(stopper->thread)
This is easily reproducible by hotplugging in and out in a tight
loop while also rebooting.
Since the CPU is not really offline and hasn't gone through the
proper steps to be marked as such, let's mark the CPU as inactive.
This is just as easily testable as online and avoids any possibility
of _cpu_up() trying to bring the CPU back online when it never was
offline to begin with.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit 4a734179d918a4ee42c5fd6d54220eb6dd671ff0)
Change-Id: Id751200d45b58f12bf7d31ae5a7bc2ddd42ef92a
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
Currently, we enable the timer hardware and unmask its interrupt in
the set_next_event callback. However, during hotplug, this callback
can be called after the timer is already supposed to be disabled.
Since the timer will be completely turned back on by set_next_event,
we will soon receive an interrupt, potentially causing us to wake up
from hotplug.
Instead, continue unmasking the interrupt when set_next_event is
called, but only enable the timer hardware in the set_mode callback.
This means that, once arch_timer_disable is called, we are guaranteed
to not receive more timer interrupts until the cpu is intentionally
hotplugged back in.
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
(cherry picked from commit 9e31f169e9e9a6255fdfcef0dfda86c8287e5a54)
Change-Id: I24dd67905f8fd772fbb9dbc42ca3cdaa7dc4345f
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
If one process calls sys_reboot and that process then stops other
CPUs while those CPUs are within a spin_lock() region we can
potentially encounter a deadlock scenario like below.
CPU 0 CPU 1
----- -----
spin_lock(my_lock)
smp_send_stop()
send_IPI handle_IPI()
disable_preemption/irqs
while(1);
<PREEMPT>
spin_lock(my_lock) <--- Waits forever
We shouldn't attempt to run any other tasks after we send a stop
IPI to a CPU so disable preemption so that this task runs to
completion.
Change-Id: I528af0b4448433bd9d6ca12d6a0e2c422a55d4be
CRs-Fixed: 396169
Reported-by: Sundarajan Srinivasan <sundaraj@codeaurora.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit 78e9b56740ad789351b6d15cd9a67fe03091a3a1)
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
Since the smp call to stop the other cpus are handled in those
cpus in interrupt context, there's a potential for those smp
handlers to interrupt threads holding spin locks (such as the
one a mutex holds). This prevents those threads from ever
releasing their spin lock, so if the cpu doing the shutdown
is allowed to switch to another thread that tries to grab the
same lock/mutex, we could get into a deadlock (the spin lock
call is called with preemption disabled in the mutex lock code).
To avoid that possibility, disable preemption before doing the
smp_send_stop().
Change-Id: I7976c5382d7173fcb3cd14da8cc5083d442b2544
Signed-off-by: Mike J. Chen <mjchen@google.com>
cherry-picking from kernel v3.5
There is just no point mapping up to 512MB for a serial port.
Using a single 1MB entry is way sufficient for all users.
This will create less interference for the following debugging patch.
Change-Id: Ifc06ec5dbf1c1f25053adb08b9d0a3dccfe46f3e
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Currently we enable the timer and unmask the interrupt
before setting the TVAL.
(in commit 9c642ecd6b71bb068c8a931285dc1dce043b137c)
This could cause a regression by opening a window
where TVAL can be negative (from a previous timer trigger)
and the interrupt unmasked, which would lead to an
immediate trigger, before TVAL is updated with the new value.
We need to set the TVAL after unmasking the interrupt, but
before enabling the timer.
Change-Id: I4989834f5dd50aa72e4e97f9ab15b82931bfdd1c
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Counters need to be individually re-enabled after the CPU
comes out of power collapse. Without this the counters
will simply be set to their MAX period and starting the PMU
will have no effect.
Change-Id: I3988a45277057eb80cf580b90ce697d0e6a00c43
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Disabling interrupts during the Krait WFE fixup can result
in deadlock if a thread tries to acquire a spinlock that is
released from an interrupt context. Instead of disabling
interrupts, modify the interrupt handler to reset the fixup
condition to put the processor into a safe state in the
event that the interrupt came in during the fixup window.
CRs-Fixed: 383670
Change-Id: Id504f46d6f840dc32ca11ed2f813003143e60f2d
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Since the arch_timer is a system-wide block, other hardware in an SoC
can make use of the counter values. Export a way to read the physical
counter for use by other drivers.
Change-Id: I0bcd95fa4cd7507c41ac608fc9740955d15d4b88
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
Memory reservations for memory pools or using memblock remove
must happen early at bootup. Add a function at early boot to
walk the flattened device tree and extract memory reservation
information from appropriate bindings in device tree. To ensure
that the memory is only reserved when a driver is enabled,
drivers must put EXPORT_COMPAT(<compat string>) in the driver
as well as adding the binding to the device tree. More
documentation is available in
Documentation/devicetree/bindings/arm/msm/memory-reserve.txt
Change-Id: I28fa71d7a30cea9af5447acb5d2dde562fa0f6de
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Use immediate operations for creating constants in
__enable_mmu to avoid a situation where the constant area
may not have been fully mapped by the initial identity
mapping.
CRs-Fixed: 375963
Change-Id: I0e43854f6a2947d90c075b7e3be60e4612960953
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
While running hotplug tests I ran into this RCU splat
===============================
[ INFO: suspicious RCU usage. ]
3.4.0 #3275 Tainted: G W
-------------------------------
include/linux/rcupdate.h:729 rcu_read_lock() used illegally while idle!
other info that might help us debug this:
RCU used illegally from idle CPU!
rcu_scheduler_active = 1, debug_locks = 0
RCU used illegally from extended quiescent state!
4 locks held by swapper/2/0:
#0: ((cpu_died).wait.lock){......}, at: [<c00ab128>] complete+0x1c/0x5c
#1: (&p->pi_lock){-.-.-.}, at: [<c00b275c>] try_to_wake_up+0x2c/0x388
#2: (&rq->lock){-.-.-.}, at: [<c00b2860>] try_to_wake_up+0x130/0x388
#3: (rcu_read_lock){.+.+..}, at: [<c00abe5c>] cpuacct_charge+0x28/0x1f4
stack backtrace:
[<c001521c>] (unwind_backtrace+0x0/0x12c) from [<c00abec8>] (cpuacct_charge+0x94/0x1f4)
[<c00abec8>] (cpuacct_charge+0x94/0x1f4) from [<c00b395c>] (update_curr+0x24c/0x2c8)
[<c00b395c>] (update_curr+0x24c/0x2c8) from [<c00b59c4>] (enqueue_task_fair+0x50/0x194)
[<c00b59c4>] (enqueue_task_fair+0x50/0x194) from [<c00afea4>] (enqueue_task+0x30/0x34)
[<c00afea4>] (enqueue_task+0x30/0x34) from [<c00b0908>] (ttwu_activate+0x14/0x38)
[<c00b0908>] (ttwu_activate+0x14/0x38) from [<c00b28a8>] (try_to_wake_up+0x178/0x388)
[<c00b28a8>] (try_to_wake_up+0x178/0x388) from [<c00a82a0>] (__wake_up_common+0x34/0x78)
[<c00a82a0>] (__wake_up_common+0x34/0x78) from [<c00ab154>] (complete+0x48/0x5c)
[<c00ab154>] (complete+0x48/0x5c) from [<c07db7cc>] (cpu_die+0x2c/0x58)
[<c07db7cc>] (cpu_die+0x2c/0x58) from [<c000f954>] (cpu_idle+0x64/0xfc)
[<c000f954>] (cpu_idle+0x64/0xfc) from [<80208160>] (0x80208160)
When a cpu is marked offline during its idle thread it calls
cpu_die() during an RCU idle period. cpu_die() calls complete()
to notify the killing process that the cpu has died. complete()
calls into the scheduler code and eventually grabs an RCU read
lock in cpuacct_charge().
Mark complete() as RCU_NONIDLE so that RCU pays attention to this
CPU for the duration of the complete() function even though it's
in idle.
Change-Id: I548a278e595737390bbc2c97bddda06a0725ecbd
Suggested-by: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds support for CMA to dma-mapping subsystem for ARM
architecture. By default a global CMA area is used, but specific devices
are allowed to have their private memory areas if required (they can be
created with dma_declare_contiguous() function during board
initialisation).
Contiguous memory areas reserved for DMA are remapped with 2-level page
tables on boot. Once a buffer is requested, a low memory kernel mapping
is updated to to match requested memory access type.
GFP_ATOMIC allocations are performed from special pool which is created
early during boot. This way remapping page attributes is not needed on
allocation time.
CMA has been enabled unconditionally for ARMv6+ systems.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Michal Nazarewicz <mina86@mina86.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Rob Clark <rob.clark@linaro.org>
Tested-by: Ohad Ben-Cohen <ohad@wizery.com>
Tested-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Tested-by: Robert Nelson <robertcnelson@gmail.com>
Tested-by: Barry Song <Baohua.Song@csr.com>
Conflicts:
arch/arm/include/asm/mach/map.h
arch/arm/mm/init.c
arch/arm/mm/mm.h
arch/arm/mm/mmu.c
Change-Id: I85e3b43a9fa1e3c4d33cbc85fff6dee1b815041d
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
From v3.4 onwards PMU's can be accessed using names
listed under /sys/bus/event_source/devices/
This patch sets up format attributes per PMU to describe how to
construct events for each PMU.
Change-Id: I2dd1293e0a906c3075c02a125ccceefeb33a80e3
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
This patch trivially changes variable names in a function
that is shared between 8960 and 8660 perf code.
Change-Id: Id59b9beef2cc83a3c4bf5671419dcd0effb5c190
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
This reverts commit 0bb2b56f7048b2f85be6784eaa8e4a5f0fa8688d.
This change is no longer necessary as of the following change,
since now we only preallocate 16 IRQs for SPARSE_IRQ
configurations. Thus the original problem of the system wasting
descriptions due to preallocated irqs no longer exists.
Author: Rob Herring <rob.herring@calxeda.com>
Date: Tue Jan 3 15:17:23 2012 -0600
ARM: only include mach/irqs.h for !SPARSE_IRQ
This also reverts commit ce4b20b3d79cb2785527fa36620252dac23b5259.
Since the preallocation scheme has been removed, we need to
update the board file to remove the old preallocation
specification.
Change-Id: I8fd819ae81fa0c8276877c0614653b5e5e14b3e2
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Extend ARM perf to check if PMU's have any special
constraints for adding events.
e.g. MSM PMU's have column exclusion constraints
that restrict adding events from the same register
and same group.
Change-Id: I36ea093c523f90f083d66dc6995e66cd77129bbd
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Upgrade the perfevents API of 8660 L2CC PMU to work with
the newer infrastructure.
Change-Id: Ib3dc966455f6f4bb680a222c458551b90cfb6b70
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
This patch upgrades the perfevents API of the L1CC
PMU on the 8660.
Change-Id: Ic9f575ec906d0ce22633a8c98160ceba4633f303
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Update the CPU PM notifier functions in perf to use the new
perf data structures.
Change-Id: I0f183072b8de65057f56d92301c22d1e9f93218b
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Update the L2CC PMU perf code for 8960 to work with
the new 3.4 perf infrastructure.
Change-Id: I7c1246d6576b6beccd0b928c29de6160979ae23f
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
If a timer uses the CP15 interface, it will not have a
memory mapped base address as part of its device tree
node. If an address is present, use this information and
ignore the CP15 interface.
Change-Id: Ibdba849e3195f1b46e590cf4b5a4204fbc45de3a
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
The current arch_timer only support accessing through CP15 interface.
Add support for ARM processors that only support IO mapped register
interface.
Change-Id: Ide8be070d21609a2b1f4d6f0e0df1a27e6d978ff
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Fix NR_IPI to be 7 instead of 6 because both googly and core add
an IPI.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Conflicts:
arch/arm/Kconfig
arch/arm/common/Makefile
arch/arm/include/asm/hardware/cache-l2x0.h
arch/arm/mm/cache-l2x0.c
arch/arm/mm/mmu.c
include/linux/wakelock.h
kernel/power/Kconfig
kernel/power/Makefile
kernel/power/main.c
kernel/power/power.h
This allows arch-specific cleanup when kexec is jumping
into the new kernel.
Change-Id: Ic2f8136b3fb7fb88ac7aae0a4c478dc780449a1f
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
(cherry picked from commit eb36b8b0f7c64cb6dfcc71f08ad65c4948a11e73)
MSM implements CONFIG_RWX and disallows the kernel text to be written.
However, in cases where we temporarily need to write the kernel text,
we explicitly mark it writeable for a short period of time.
Change-Id: I532b663a9bd0115ea5e7177e9dac4ac54e007725
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Add runtime DT support and documentation for the Cortex A7/A15
architected timers.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Conflicts:
[Resolve conflicts for adding support for the feature
ARCH_HAS_READ_CURRENT_TIMER]
arch/arm/kernel/arch_timer.c
Change-Id: I4b1d1dc2a8c69466497423475f7a3dd4d2c380c1
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit f2caa5109ee0ce7d988d864207e06fdb19e75c39)
Add support for the A15 generic timer and clocksource.
As the timer generates interrupts on a different PPI depending
on the execution mode (normal or secure), it is possible to
register two different PPIs.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Conflicts:
[Integrate to the recent patch which has changes to
local timer registration mechanism.
This fixes the crash seen during hotplug operations
where after a secondary CPU is brought back online,
the clock event device setup was happening as part
of the online notification mechanism which was too
late. With this change in the local timer mechanims,
the clock event device is now setup as part of the
secondary CPU boot initialization making it available
early enough for use.
Update the board file with the appropriate changes in
the argument for timer registration.]
arch/arm/Kconfig
arch/arm/include/asm/arch_timer.h
arch/arm/kernel/arch_timer.c
arch/arm/kernel/smp.c
Change-Id: I0bc80097c145fb2aac2150db0c5dff3c5e215a58
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit df590ccd9d8210cc3e059671efad06dab7e70d4c)
Change-Id: Iedac55e097b8d983c42799b98f2d11f7b1a95f04
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
The commit 292b293 creates the MSM boot failures, so squash
the commit 28af690 with it to avoid such failures. The commit ddd847
and 0c1991 are required to keep the watchdog and Copper targets working.
commit 292b293cee
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Wed Jul 20 16:24:14 2011 +0100
ARM: gic: consolidate PPI handling
PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).
Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.
This also allows the removal of some duplicated code.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit 28af690a28
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Fri Jul 22 12:52:37 2011 +0100
ARM: gic, local timers: use the request_percpu_irq() interface
This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).
PPIs are now useable for more than just the local timers.
Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).
Cc: David Brown <davidb@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit ddd8478d68f8cf75ee9771667c0cbe2a9d1caeb9
Author: Trilok Soni <tsoni@codeaurora.org>
Date: Tue Dec 6 00:56:01 2011 +0530
msm: watchdog: Use request_percpu_irq() interface
Change-Id: I7c319344f6a7f7a7c70682ac87f5c385e56d130c
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
commit 0c19915e092214a4c17a9920c4c1f3d78610217d
Author: Sathish Ambley <sambley@codeaurora.org>
Date: Fri Dec 9 17:07:37 2011 +0530
arm: arch_timer: Use request_percpu_irq() API
Change-Id: Iee9b218d538f315cd884a47d95bcc0dcc49b0fe1
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
Change-Id: I7bbba706b1f2e55814be5891ed76063725c2bfb1
Signed-off-by: Ravi Kumar <kumarrav@codeaurora.org>
[tsoni@codeaurora.org: MSM specific fixes]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
(cherry picked from commit eecb28c59054b1b9d8b9f410a903f87c8eb1ac48)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/entry-macro-gic.S
arch/arm/include/asm/localtimer.h
arch/arm/include/asm/smp.h
arch/arm/include/asm/smp_twd.h
arch/arm/kernel/smp.c
arch/arm/kernel/smp_twd.c
arch/arm/mach-exynos4/include/mach/entry-macro.S
arch/arm/mach-exynos4/mct.c
arch/arm/mach-msm/board-8064.c
arch/arm/mach-msm/board-8960.c
arch/arm/mach-msm/board-copper.c
arch/arm/mach-msm/board-dt.c
arch/arm/mach-msm/devices-9615.c
arch/arm/mach-msm/devices-msm8x60.c
arch/arm/mach-msm/include/mach/entry-macro-qgic.S
arch/arm/mach-msm/msm_watchdog.c
arch/arm/mach-msm/timer.c
arch/arm/mach-omap2/include/mach/entry-macro.S
Fix the following warning seen while linking
WARNING: vmlinux.o(.text+0xc4b8): Section mismatch in reference
from the function arch_timer_register() to the (unknown reference)
.cpuinit.data:(unknown)
The function arch_timer_register() references
the (unknown reference) __cpuinitdata (unknown).
This is often because arch_timer_register lacks a __cpuinitdata
annotation or the annotation of (unknown) is wrong.
Change-Id: I2646e63550b9f46d36a34d9e3b2841c7d6204386
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit d7cd1bda5932db92b6d2d0a25151def06a10e3ad)
Level triggered interrupt is deasserted when a new TVAL is written
only when the interrupt is unmasked. Make sure that the interrupt
is unmasked in CTL register before TVAL is written.
Change-Id: I1bbfe262137fb27c0de68a552b07e285f424b259
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit 9c642ecd6b71bb068c8a931285dc1dce043b137c)
Register interrupts using interrupt action mechanism instead of
gic_request_ppi() which is dependent on an another patch series
that doesn't exist yet.
Add read_current_timer() to support ARCH_HAS_READ_CURRENT_TIMER
and register the delay loop routine.
Change-Id: I2e7309b93a7bdae37103b738d547eb20f86fe9f7
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit 8a30982a61b775c57067939b7189c49c3d108907)
Provide an A15 sched_clock implementation using the virtual counter,
which is thought to be more useful than the physical one in a
virtualised environment, as it can offset the time spent in another
VM or the hypervisor.
Change-Id: Ica870d279dba38304581763654c683cd09f87153
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[sambley@codeaurora.org Fix conflicts due to patched code not
against latest version of arch_timer.c]
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit 165a4743bc9a809ff78b703b10f986b1a1071785)
Init code, text, rodata and data need different permissions
and so they need to be on different pages. The kernel 1-to-1
mapping is constructed using 1M pages to improve TLB performance
and this should not be changed (to 4K pages). Therefore
ensure that each of these regions starts on a 1M boundary.
Change-Id: I855b58d3deff6c34e58d1cbdef4b360c2b23ca6d
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>
Signed-off-by: Jin Hong <jinh@codeaurora.org>
(cherry picked from commit 4cfee820adbdd7514b67e59c1b87008436d984ab)
