Since the arch_timer is a system-wide block, other hardware in an SoC
can make use of the counter values. Export a way to read the physical
counter for use by other drivers.
Change-Id: I0bcd95fa4cd7507c41ac608fc9740955d15d4b88
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
Memory reservations for memory pools or using memblock remove
must happen early at bootup. Add a function at early boot to
walk the flattened device tree and extract memory reservation
information from appropriate bindings in device tree. To ensure
that the memory is only reserved when a driver is enabled,
drivers must put EXPORT_COMPAT(<compat string>) in the driver
as well as adding the binding to the device tree. More
documentation is available in
Documentation/devicetree/bindings/arm/msm/memory-reserve.txt
Change-Id: I28fa71d7a30cea9af5447acb5d2dde562fa0f6de
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Use immediate operations for creating constants in
__enable_mmu to avoid a situation where the constant area
may not have been fully mapped by the initial identity
mapping.
CRs-Fixed: 375963
Change-Id: I0e43854f6a2947d90c075b7e3be60e4612960953
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
While running hotplug tests I ran into this RCU splat
===============================
[ INFO: suspicious RCU usage. ]
3.4.0 #3275 Tainted: G W
-------------------------------
include/linux/rcupdate.h:729 rcu_read_lock() used illegally while idle!
other info that might help us debug this:
RCU used illegally from idle CPU!
rcu_scheduler_active = 1, debug_locks = 0
RCU used illegally from extended quiescent state!
4 locks held by swapper/2/0:
#0: ((cpu_died).wait.lock){......}, at: [<c00ab128>] complete+0x1c/0x5c
#1: (&p->pi_lock){-.-.-.}, at: [<c00b275c>] try_to_wake_up+0x2c/0x388
#2: (&rq->lock){-.-.-.}, at: [<c00b2860>] try_to_wake_up+0x130/0x388
#3: (rcu_read_lock){.+.+..}, at: [<c00abe5c>] cpuacct_charge+0x28/0x1f4
stack backtrace:
[<c001521c>] (unwind_backtrace+0x0/0x12c) from [<c00abec8>] (cpuacct_charge+0x94/0x1f4)
[<c00abec8>] (cpuacct_charge+0x94/0x1f4) from [<c00b395c>] (update_curr+0x24c/0x2c8)
[<c00b395c>] (update_curr+0x24c/0x2c8) from [<c00b59c4>] (enqueue_task_fair+0x50/0x194)
[<c00b59c4>] (enqueue_task_fair+0x50/0x194) from [<c00afea4>] (enqueue_task+0x30/0x34)
[<c00afea4>] (enqueue_task+0x30/0x34) from [<c00b0908>] (ttwu_activate+0x14/0x38)
[<c00b0908>] (ttwu_activate+0x14/0x38) from [<c00b28a8>] (try_to_wake_up+0x178/0x388)
[<c00b28a8>] (try_to_wake_up+0x178/0x388) from [<c00a82a0>] (__wake_up_common+0x34/0x78)
[<c00a82a0>] (__wake_up_common+0x34/0x78) from [<c00ab154>] (complete+0x48/0x5c)
[<c00ab154>] (complete+0x48/0x5c) from [<c07db7cc>] (cpu_die+0x2c/0x58)
[<c07db7cc>] (cpu_die+0x2c/0x58) from [<c000f954>] (cpu_idle+0x64/0xfc)
[<c000f954>] (cpu_idle+0x64/0xfc) from [<80208160>] (0x80208160)
When a cpu is marked offline during its idle thread it calls
cpu_die() during an RCU idle period. cpu_die() calls complete()
to notify the killing process that the cpu has died. complete()
calls into the scheduler code and eventually grabs an RCU read
lock in cpuacct_charge().
Mark complete() as RCU_NONIDLE so that RCU pays attention to this
CPU for the duration of the complete() function even though it's
in idle.
Change-Id: I548a278e595737390bbc2c97bddda06a0725ecbd
Suggested-by: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds support for CMA to dma-mapping subsystem for ARM
architecture. By default a global CMA area is used, but specific devices
are allowed to have their private memory areas if required (they can be
created with dma_declare_contiguous() function during board
initialisation).
Contiguous memory areas reserved for DMA are remapped with 2-level page
tables on boot. Once a buffer is requested, a low memory kernel mapping
is updated to to match requested memory access type.
GFP_ATOMIC allocations are performed from special pool which is created
early during boot. This way remapping page attributes is not needed on
allocation time.
CMA has been enabled unconditionally for ARMv6+ systems.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Michal Nazarewicz <mina86@mina86.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Rob Clark <rob.clark@linaro.org>
Tested-by: Ohad Ben-Cohen <ohad@wizery.com>
Tested-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Tested-by: Robert Nelson <robertcnelson@gmail.com>
Tested-by: Barry Song <Baohua.Song@csr.com>
Conflicts:
arch/arm/include/asm/mach/map.h
arch/arm/mm/init.c
arch/arm/mm/mm.h
arch/arm/mm/mmu.c
Change-Id: I85e3b43a9fa1e3c4d33cbc85fff6dee1b815041d
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
From v3.4 onwards PMU's can be accessed using names
listed under /sys/bus/event_source/devices/
This patch sets up format attributes per PMU to describe how to
construct events for each PMU.
Change-Id: I2dd1293e0a906c3075c02a125ccceefeb33a80e3
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
This patch trivially changes variable names in a function
that is shared between 8960 and 8660 perf code.
Change-Id: Id59b9beef2cc83a3c4bf5671419dcd0effb5c190
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
This reverts commit 0bb2b56f7048b2f85be6784eaa8e4a5f0fa8688d.
This change is no longer necessary as of the following change,
since now we only preallocate 16 IRQs for SPARSE_IRQ
configurations. Thus the original problem of the system wasting
descriptions due to preallocated irqs no longer exists.
Author: Rob Herring <rob.herring@calxeda.com>
Date: Tue Jan 3 15:17:23 2012 -0600
ARM: only include mach/irqs.h for !SPARSE_IRQ
This also reverts commit ce4b20b3d79cb2785527fa36620252dac23b5259.
Since the preallocation scheme has been removed, we need to
update the board file to remove the old preallocation
specification.
Change-Id: I8fd819ae81fa0c8276877c0614653b5e5e14b3e2
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Extend ARM perf to check if PMU's have any special
constraints for adding events.
e.g. MSM PMU's have column exclusion constraints
that restrict adding events from the same register
and same group.
Change-Id: I36ea093c523f90f083d66dc6995e66cd77129bbd
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Upgrade the perfevents API of 8660 L2CC PMU to work with
the newer infrastructure.
Change-Id: Ib3dc966455f6f4bb680a222c458551b90cfb6b70
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
This patch upgrades the perfevents API of the L1CC
PMU on the 8660.
Change-Id: Ic9f575ec906d0ce22633a8c98160ceba4633f303
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Update the CPU PM notifier functions in perf to use the new
perf data structures.
Change-Id: I0f183072b8de65057f56d92301c22d1e9f93218b
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Update the L2CC PMU perf code for 8960 to work with
the new 3.4 perf infrastructure.
Change-Id: I7c1246d6576b6beccd0b928c29de6160979ae23f
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
If a timer uses the CP15 interface, it will not have a
memory mapped base address as part of its device tree
node. If an address is present, use this information and
ignore the CP15 interface.
Change-Id: Ibdba849e3195f1b46e590cf4b5a4204fbc45de3a
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
The current arch_timer only support accessing through CP15 interface.
Add support for ARM processors that only support IO mapped register
interface.
Change-Id: Ide8be070d21609a2b1f4d6f0e0df1a27e6d978ff
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Fix NR_IPI to be 7 instead of 6 because both googly and core add
an IPI.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Conflicts:
arch/arm/Kconfig
arch/arm/common/Makefile
arch/arm/include/asm/hardware/cache-l2x0.h
arch/arm/mm/cache-l2x0.c
arch/arm/mm/mmu.c
include/linux/wakelock.h
kernel/power/Kconfig
kernel/power/Makefile
kernel/power/main.c
kernel/power/power.h
This allows arch-specific cleanup when kexec is jumping
into the new kernel.
Change-Id: Ic2f8136b3fb7fb88ac7aae0a4c478dc780449a1f
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
(cherry picked from commit eb36b8b0f7c64cb6dfcc71f08ad65c4948a11e73)
MSM implements CONFIG_RWX and disallows the kernel text to be written.
However, in cases where we temporarily need to write the kernel text,
we explicitly mark it writeable for a short period of time.
Change-Id: I532b663a9bd0115ea5e7177e9dac4ac54e007725
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Add runtime DT support and documentation for the Cortex A7/A15
architected timers.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Conflicts:
[Resolve conflicts for adding support for the feature
ARCH_HAS_READ_CURRENT_TIMER]
arch/arm/kernel/arch_timer.c
Change-Id: I4b1d1dc2a8c69466497423475f7a3dd4d2c380c1
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit f2caa5109ee0ce7d988d864207e06fdb19e75c39)
Add support for the A15 generic timer and clocksource.
As the timer generates interrupts on a different PPI depending
on the execution mode (normal or secure), it is possible to
register two different PPIs.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Conflicts:
[Integrate to the recent patch which has changes to
local timer registration mechanism.
This fixes the crash seen during hotplug operations
where after a secondary CPU is brought back online,
the clock event device setup was happening as part
of the online notification mechanism which was too
late. With this change in the local timer mechanims,
the clock event device is now setup as part of the
secondary CPU boot initialization making it available
early enough for use.
Update the board file with the appropriate changes in
the argument for timer registration.]
arch/arm/Kconfig
arch/arm/include/asm/arch_timer.h
arch/arm/kernel/arch_timer.c
arch/arm/kernel/smp.c
Change-Id: I0bc80097c145fb2aac2150db0c5dff3c5e215a58
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit df590ccd9d8210cc3e059671efad06dab7e70d4c)
Change-Id: Iedac55e097b8d983c42799b98f2d11f7b1a95f04
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
The commit 292b293 creates the MSM boot failures, so squash
the commit 28af690 with it to avoid such failures. The commit ddd847
and 0c1991 are required to keep the watchdog and Copper targets working.
commit 292b293cee
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Wed Jul 20 16:24:14 2011 +0100
ARM: gic: consolidate PPI handling
PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).
Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.
This also allows the removal of some duplicated code.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit 28af690a28
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Fri Jul 22 12:52:37 2011 +0100
ARM: gic, local timers: use the request_percpu_irq() interface
This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).
PPIs are now useable for more than just the local timers.
Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).
Cc: David Brown <davidb@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit ddd8478d68f8cf75ee9771667c0cbe2a9d1caeb9
Author: Trilok Soni <tsoni@codeaurora.org>
Date: Tue Dec 6 00:56:01 2011 +0530
msm: watchdog: Use request_percpu_irq() interface
Change-Id: I7c319344f6a7f7a7c70682ac87f5c385e56d130c
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
commit 0c19915e092214a4c17a9920c4c1f3d78610217d
Author: Sathish Ambley <sambley@codeaurora.org>
Date: Fri Dec 9 17:07:37 2011 +0530
arm: arch_timer: Use request_percpu_irq() API
Change-Id: Iee9b218d538f315cd884a47d95bcc0dcc49b0fe1
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
Change-Id: I7bbba706b1f2e55814be5891ed76063725c2bfb1
Signed-off-by: Ravi Kumar <kumarrav@codeaurora.org>
[tsoni@codeaurora.org: MSM specific fixes]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
(cherry picked from commit eecb28c59054b1b9d8b9f410a903f87c8eb1ac48)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/entry-macro-gic.S
arch/arm/include/asm/localtimer.h
arch/arm/include/asm/smp.h
arch/arm/include/asm/smp_twd.h
arch/arm/kernel/smp.c
arch/arm/kernel/smp_twd.c
arch/arm/mach-exynos4/include/mach/entry-macro.S
arch/arm/mach-exynos4/mct.c
arch/arm/mach-msm/board-8064.c
arch/arm/mach-msm/board-8960.c
arch/arm/mach-msm/board-copper.c
arch/arm/mach-msm/board-dt.c
arch/arm/mach-msm/devices-9615.c
arch/arm/mach-msm/devices-msm8x60.c
arch/arm/mach-msm/include/mach/entry-macro-qgic.S
arch/arm/mach-msm/msm_watchdog.c
arch/arm/mach-msm/timer.c
arch/arm/mach-omap2/include/mach/entry-macro.S
Fix the following warning seen while linking
WARNING: vmlinux.o(.text+0xc4b8): Section mismatch in reference
from the function arch_timer_register() to the (unknown reference)
.cpuinit.data:(unknown)
The function arch_timer_register() references
the (unknown reference) __cpuinitdata (unknown).
This is often because arch_timer_register lacks a __cpuinitdata
annotation or the annotation of (unknown) is wrong.
Change-Id: I2646e63550b9f46d36a34d9e3b2841c7d6204386
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit d7cd1bda5932db92b6d2d0a25151def06a10e3ad)
Level triggered interrupt is deasserted when a new TVAL is written
only when the interrupt is unmasked. Make sure that the interrupt
is unmasked in CTL register before TVAL is written.
Change-Id: I1bbfe262137fb27c0de68a552b07e285f424b259
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit 9c642ecd6b71bb068c8a931285dc1dce043b137c)
Register interrupts using interrupt action mechanism instead of
gic_request_ppi() which is dependent on an another patch series
that doesn't exist yet.
Add read_current_timer() to support ARCH_HAS_READ_CURRENT_TIMER
and register the delay loop routine.
Change-Id: I2e7309b93a7bdae37103b738d547eb20f86fe9f7
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit 8a30982a61b775c57067939b7189c49c3d108907)
Provide an A15 sched_clock implementation using the virtual counter,
which is thought to be more useful than the physical one in a
virtualised environment, as it can offset the time spent in another
VM or the hypervisor.
Change-Id: Ica870d279dba38304581763654c683cd09f87153
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[sambley@codeaurora.org Fix conflicts due to patched code not
against latest version of arch_timer.c]
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit 165a4743bc9a809ff78b703b10f986b1a1071785)
Init code, text, rodata and data need different permissions
and so they need to be on different pages. The kernel 1-to-1
mapping is constructed using 1M pages to improve TLB performance
and this should not be changed (to 4K pages). Therefore
ensure that each of these regions starts on a 1M boundary.
Change-Id: I855b58d3deff6c34e58d1cbdef4b360c2b23ca6d
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>
Signed-off-by: Jin Hong <jinh@codeaurora.org>
(cherry picked from commit 4cfee820adbdd7514b67e59c1b87008436d984ab)
ARM builds seem to be plagued by an occasional build error:
Inconsistent kallsyms data
This is a bug - please report about it
Try "make KALLSYMS_EXTRA_PASS=1" as a workaround
The problem has to do with alignment of some sections by the linker.
The kallsyms data is built in two passes by first linking the kernel
without it, and then linking the kernel again with the symbols
included. Normally, this just shifts the symbols, without changing
their order, and the compression used by the kallsyms gives the same
result.
on non SMP, the per CPU data is empty. Depending on the where the
alignment ends up, it can come out as either:
+-------------------+
| last text segment |
+-------------------+
/* padding */
+-------------------+ <- L1_CACHE_BYTES alignemnt
| per cpu (empty) |
+-------------------+
__per_cpu_end:
/* padding */
__data_loc:
+-------------------+ <- THREAD_SIZE alignment
| data |
+-------------------+
or
+-------------------+
| last text segment |
+-------------------+
/* padding */
+-------------------+ <- L1_CACHE_BYTES alignemnt
| per cpu (empty) |
+-------------------+
__per_cpu_end:
/* no padding */
__data_loc:
+-------------------+ <- THREAD_SIZE alignment
| data |
+-------------------+
if the alignment satisfies both. Because symbols that have the same
address are sorted by 'nm -n', the second case will be in a different
order than the first case. This changes the compression, changing the
size of the kallsym data, causing the build failure.
The KALLSYMS_EXTRA_PASS=1 workaround usually works, but it is still
possible to have the alignment change between the second and third
pass. It's probably even possible for it to never reach a fixedpoint.
The problem only occurs on non-SMP, when the per-cpu data is empty,
and when the data segment has alignment (and immediately follows the
text segments). In these cases, add the THREAD_SIZE alignment above
the per-cpu data so that the empty segment will always be adjacent to
the data segment.
This shouldn't ever change the size of the kernel, and only should
affect the location of the per_cpu symbols, which contain no data.
Signed-off-by: David Brown <davidb@codeaurora.org>
Change-Id: I1b5eaf9025fc9f0f5153bf59d95db0cb4cd74932
(cherry picked from commit da8ba55725b7683ef54cf110f61f1f67a055a773)
This patch implements CONFIG_DEBUG_RODATA, allowing
the kernel text section to be marked read-only in
order to catch bugs that write over the kernel. This
requires mapping the kernel code, plus up to 4MB, using
pages instead of sections, which can increase TLB
pressure.
The kernel is normally mapped using 1MB section entries
in the first level page table, and the first level page
table is copied into every mm. This prevents marking
the kernel text read-only, because the 1MB section
entries are too large granularity to separate the init
section, which is reused as read-write memory after
init, and the kernel text section. Also, the top level
page table for every process would need to be updated,
which is not possible to do safely and efficiently on SMP.
To solve both problems, allow alloc_init_pte to overwrite
an existing section entry with a fully-populated second
level page table. When CONFIG_DEBUG_RODATA is set, all
the section entries that overlap the kernel text section
will be replaced with page mappings. The kernel always
uses a pair of 2MB-aligned 1MB sections, so up to 2MB
of memory before and after the kernel may end up page
mapped.
When the top level page tables are copied into each
process the second level page tables are not copied,
leaving a single second level page table that will
affect all processes on all cpus. To mark a page
read-only, the second level page table is located using
the pointer in the first level page table for the
current process, and the supervisor RO bit is flipped
atomically. Once all pages have been updated, all TLBs
are flushed to ensure the changes are visible on all
cpus.
If CONFIG_DEBUG_RODATA is not set, the kernel will be
mapped using the normal 1MB section entries.
Change-Id: I94fae337f882c2e123abaf8e1082c29cd5d483c6
Signed-off-by: Colin Cross <ccross@android.com>
(cherry picked from commit e5e483d133)
Conflicts:
arch/arm/mm/mmu.c
For cases with SPARSE_IRQ enabled, irqs preallocated with
arch_probe_nr_irqs() are already marked as allocated in the
allocated_irqs bitmap. As a consequence, irq chip drivers that
allocate irqs will feel one of two behaviors:
1. An allocation will succeed with the starting irq_base one
more than the preallocated irqs. This will thus waste the
preceeding interrupt resources that were preallocated, unless a
legacy chip driver happens to assume ownership of these by some
platform definition. The GIC driver is a typical primary chip
driver, and abides to the allocation APIs. So this can be a
problem in many trivial usecases.
2. An allocation will fail with < 0. This can also happen in the
GIC driver, which interprets this value as meaning the irq_descs
are already preallocated. But in Device Tree configurations, the
fallback irq_base is -1. This results in an invalid irq_base
value.
Looking forward, we are moving towards a world where preallocation
of irqs is no longer necessary. irq_domain is scoped to handle all
irq_desc allocations in the future. Thus, we should support
configurations where the platform wants to preallocate no irqs.
One easy way to achieve this is to allow for
machine_desc->nr_irqs < 0, which indicates not to preallocate any
interrupts.
Change-Id: Ie793932c58de72c1b91b6e039b77a8e5d64ecc75
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
(cherry picked from commit 0bb2b56f7048b2f85be6784eaa8e4a5f0fa8688d)
Cortex A5 has access to 3 hardware breakpoint registers and writing to
extra register causes an illegal instruction. Add Kconfig option for
such chips which doesn't allow the rw access beyond the available
breakpoint registers.
Change-Id: I7b771031e55e72a1f6d9d4987a3b5554760f238d
Signed-off-by: Taniya Das <tdas@codeaurora.org>
(cherry picked from commit 63269b42ac0603fd5ffb7598553e1b8f3bbddf5e)
Conflicts:
arch/arm/kernel/hw_breakpoint.c
arch/arm/mach-msm/Kconfig
The MSM perf_event code wants to know which cpu the event is for.
Pass this during the enable call.
Change-Id: I1151ac9361c3050ecb40455c017368ead25c6fdc
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
MSM code needs this to be non-const for now.
Change-Id: If2e3d1b62ac167d05c83955adf27635570066a1c
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Contains the squash of 2 patches
commit 39242ba4253db8a1bebc37526d1fddc74889c200
Author: Ashwin Chaugule <ashwinc@codeaurora.org>
AuthorDate: Mon Oct 29 16:30:05 2012 -0400
Commit: Ashwin Chaugule <ashwinc@codeaurora.org>
CommitDate: Thu Nov 8 14:37:56 2012 -0500
Perf: Let platforms decide IRQ request methods.
This is in preparation for adding support for the unicore A5
and dualcore A5, both of which have the same MIDR value.
Instead of adding extra parsing to the ARM generic perf_event
file,
this patch moves it to the 'mach' directory where targets
types
can be detected in an implementation specific manner.
The default behavior is maintained for all other ARM
targets.
commit 4afdedccc111b9b60b66d156cce43988c4cbe7f0
Author: Ashwin Chaugule <ashwinc@codeaurora.org>
AuthorDate: Tue Jan 17 13:23:50 2012 -0500
Commit: Ashwin Chaugule <ashwinc@codeaurora.org>
CommitDate: Fri Feb 3 16:27:51 2012 -0500
Perf: Switch to per-cpu IRQ framework
The L1CC PMU interrupt is a PPI, so
use the per-CPU
request, free, enable, disable
API.
Change-Id: I0d2cd9c5eac5b020f4d1b640cb9c397afe0ea2ad
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Some multi-core ARM chips designate a unique IRQ number for each core for
private peripheral interrupts (PPIs). Others designate a common IRQ number
for all cores. In the latter case, requesting/freeing private peripheral
interrupts currently enables/disables the interrupt for only the executing
core, respectively.
Secondary enable/disable functions should only be defined for chips that
use a PPI for their PMU IRQ. This will enable/disable the PMU IRQ on all
cores after request_irq/free_irq, respectively.
Change-Id: Ia6b0ff4187ef34c5defa8a5bc27553ff8b3d557a
Signed-off-by: Stephen Caudle <scaudle@codeaurora.org>
(cherry picked from commit 7e0b69375543feebbed6a8421f158d48f4aeabb1)
Conflicts:
arch/arm/kernel/perf_event.c
This commit adds support for performance monitors provided by
Scorpion and ScorpionMP processor to perfevents.
Change-Id: I1796db44d486a3c94b02c09c628689d2afc5ffae
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
(cherry picked from commit 1e6b885dcf3aa33bc2ab6bf2997f497abbcd95ce)
Conflicts:
arch/arm/kernel/perf_event.c
This commit enables Oprofile on Scorpion and Scorpion-MP based
chips. It only adds the generic arm performance monitors.
It also adds necessary support to all the underlying perf
components.
Change-Id: I525f35097595b3c4c9c94f9bbb47e4209edf5ddb
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
(cherry picked from commit b014badff96a5915218d8e7e0d99906976264a58)
Conflicts:
arch/arm/include/asm/perf_event.h
arch/arm/kernel/perf_event.c
arch/arm/mach-msm/Makefile
In the next patch we're going to allow machines to override the
__delay() implementation at runtime so they can implement a timer
based __delay() routine. It's easier to do this using C, so lets
write udelay and friends in C.
We lose the #if 0 code, which according to Russell is used "to
make the delay loop more stable and predictable on older CPUs"
(see http://article.gmane.org/gmane.linux.kernel/888867 for more
info). We shouldn't be too worried though, since the next patch
adds functionality to allow a machine to set the __delay() loop
themselves, therefore allowing machines to resurrect the
commented out code if they need it.
bloat-o-meter shows an increase of 12 bytes. Further inspection
of the assembly shows GCC copying the loops_per_jiffy pointer and
the magic HZ value to the ends of __const_udelay() and _delay()
thus contributing an extra 4 and 8 bytes of data to each
function. These two values weren't taken into account in the
delay.S version since they weren't part of the function in nm's
eyes. This means we only really gained an extra 4 bytes due to
GCC's decision to duplicate the loops_per_jiffy pointer in
__const_udelay.
$ scripts/bloat-o-meter vmlinux.orig vmlinux.new
add/remove: 0/0 grow/shrink: 2/0 up/down: 12/0 (12)
function old new delta
__udelay 48 56 +8
__const_udelay 40 44 +4
Change-Id: Ibfaab52d0f5e09471571be082232db04726d5532
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Saravana Kannan <skannan@codeaurora.org>
(cherry picked from commit 8d5868d8205d10a0a8e423f53e9cc9bb3e9d1a34)
Conflicts:
arch/arm/kernel/armksyms.c
arch/arm/lib/delay.S
Add support for the A15 generic timer and clocksource.
As the timer generates interrupts on a different PPI depending
on the execution mode (normal or secure), it is possible to
register two different PPIs.
Change-Id: Ibaddc7f174bc168cef579b66ab06b966878ae155
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit f5b3b2b2a44e813fbbe1799965a8879429f59329)
Conflicts:
arch/arm/kernel/Makefile
KSAPI records performance statistics for Snapdragon linux platform.
It uses the /proc FS as a means to exchange configuration data and counter
statistics. It can monitor the counter statistics for Scorpion processor
supported hardware performance counters on a per thread basis or AXI
counters on an overall system basis.
Change-Id: Iaaf51db68dbd6d5a55fe34328d041bde5015230d
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
(cherry picked from commit 4e6bb52bcee479762f283b4a44a1bdd4f1277aa2)
Conflicts:
arch/arm/Kconfig
Define arm_pm_idle to be arch_idle which is defined in pm-8x60.c
(This code should be moved to the pm-8x60 file later on)
Change-Id: I345d436111c585e4dfbae367dac5d24d1a1f9711
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
ARM restart code flushes the cpu caches, but leaves
the external caches unflushed. Disable the external cache
to get all the desired data and prevent loss of further
information.
Change-Id: Ie6a6765cdc1dfc8ee7d4c4ed473fdbf4d5ef9b88
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
(cherry picked from commit eee780eafdf990702fdd8178b865af322b2a7621)
Conflicts:
arch/arm/kernel/process.c
Hotplug occurs frequently enough on our targets that its messages are
clogging up the logs. There is no need for any messages to be printed
when hotplug is successful.
Change-Id: Icf213ab409ba428f39439f886cdf4c070a48bfbf
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
(cherry picked from commit 4d0bd4217b4e451843dc21208036d25f9d2871f8)
Conflicts:
arch/arm/kernel/smp.c
Commit 'ad3b6993' converted ARM smp_cross_call() to take IPI number
as a parameter to handle more event than SGI and do_IPI was suppose
to recover SGI number. But the do_IPI doesn't consider it and it's
getting detected as 'Unknown IPI message 0x1' with ipi numbers are
moved to starts from 'IPI_TIMER=2"
There can be 16 different SGI but only SGI1 is used as IPI so
only that one is handled in do_IPI as IPI_CPU_START.
Added IPI_CPU_START because it wasn't used and thought it's
appropriate. Not sure whether its the right one.
Change-Id: I4dbe7c489d9611fbbb4036c15ac247659fde4119
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
[johlstei@codeaurora.org: fixed bounds check error]
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
(cherry picked from commit 7f685e51169149a877cb3100670567fb03c969f5)
Due to changes of the order of initialization of
the ARM-specfic memory management code in 3.0, it
is necessary to create a way to call platform specific
code earlier than is currently possible.
Change-Id: I77dae10c85085358f7240889a50b78b07d5af6d1
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>
(cherry picked from commit f81fb5655af9aaf573cb11b9a64e0a826fa580e2)
Conflicts:
arch/arm/kernel/setup.c
Some userspace applications use /proc/cpuinfo to determine how many CPUs
the system has. CPU hotplug can offline a CPU at runtime and causing the
offline CPU not present in /proc/cpuinfo if we only show online cpu in
/proc/cpuinfo.
CRs-Fixed: 354430
Change-Id: I22a15d2d141c713dcd4abaa8bb74ecad6508900f
Signed-off-by: Jin Hong <jinh@codeaurora.org>
(cherry picked from commit 1e28794d0ff00fc6567d68b5b4e863b0745cfe20)
When emulating a SWP/SWPB instruction, check the condition
code of the instruction and compare it against CPSR status
bits rather than relying on the architecture to only raise
an undefined instruction exception if the condition checks
are passing.
Change-Id: I9707960b091c3a5af20e396e0b6d5ed2aaf935ff
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
(cherry picked from commit 3308e7be1800faab8988f2b87c83c3bbb72d7e22)
