Update the L2CC PMU perf code for 8960 to work with
the new 3.4 perf infrastructure.
Change-Id: I7c1246d6576b6beccd0b928c29de6160979ae23f
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
dfab_clk is used to vote for SDCC AHB clock derived
from Dayatona fabric. This naming convention is invalid
for targets where the AHB clocks are derived from other
buses like peripheral NoC. Hence, rename this to a generic
name that is applicable for all targets.
Change-Id: I9563342f07430cc000c86a93d265ff126003c8a5
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
The current arch_timer only support accessing through CP15 interface.
Add support for ARM processors that only support IO mapped register
interface.
Change-Id: Ide8be070d21609a2b1f4d6f0e0df1a27e6d978ff
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Add build id detection to enable the interleave mode feature in the driver.
In the interleave mode image ( boot, userdata etc ) codewords are written
to the NAND devices in a interleave fashion. Hence modem and apps should
operate in the same mode to read/write the images properly.
Change-Id: Ie9182eadd5750662dde07abfe793b4d231cf0ae1
Signed-off-by: Murali Nalajala <mnalajal@qualcomm.com>
(cherry picked from commit e80fa943d6aba79406c5793c84c5afa076a84e0c)
Conflicts:
arch/arm/mach-msm/board-msm7x30.c
arch/arm/mach-msm/devices-msm7x30.c
drivers/mtd/devices/msm_nand.c
For the Nand controller on 7x30 and 7x27a, the
uncorrectable error bit in the NANDC_BUFFER_STATUS
register is changed to BIT(8) from BIT(3) (in legacy
targets) due to change in the ECC requirements. Currently,
this is handled only in dual nandc mode (default for 7x30
and 7x27a). In case, if only single nandc is used, the
uncorrectable bit check is broken and the driver wouldn't
detect any ECC errors.
Add software version info in platform data to differentiate
between the targets that have different register interface.
CRs-Fixed: 365433
Change-Id: I3c33ccb0e936e262116dd20798d56530dbae900f
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
(cherry picked from commit ec9b3250fe233e4ff96b4ad23372df5f8299fc67)
Conflicts:
arch/arm/mach-msm/devices-9615.c
arch/arm/mach-msm/devices-msm7x27a.c
arch/arm/mach-msm/devices-msm7x30.c
Fix NR_IPI to be 7 instead of 6 because both googly and core add
an IPI.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Conflicts:
arch/arm/Kconfig
arch/arm/common/Makefile
arch/arm/include/asm/hardware/cache-l2x0.h
arch/arm/mm/cache-l2x0.c
arch/arm/mm/mmu.c
include/linux/wakelock.h
kernel/power/Kconfig
kernel/power/Makefile
kernel/power/main.c
kernel/power/power.h
Clean the #if nesting by using the COHERENT_IS_NORMAL flag. Introduce a
compiler barrier() in the pre case when COHERENT_IS_NORMAL is 0 and arch is
not coherent. Note that for Xscale we will have to force dmb() as it uses
kmalloc for coherent memory.
Change-Id: I1753fc62f5dfa3333c65269ab1815cd29e5698f7
Signed-off-by: Abhijeet Dharmapurikar <adharmap@quicinc.com>
(cherry picked from commit 496709819ea8e94acd3b781bd64dc54eba940226)
Conflicts:
arch/arm/include/asm/dma-mapping.h
arch/arm/include/asm/pgtable.h
Coherent memory in ARMv6+ could be StronglyOrdered or Normal. On ARMv7
StronglyOrdered guarantees program order execution only within 1KB and
Normal memory could have speculative fetches on them. Hence we need
barrier operations before and after dma for coherent memory.
Signed-off-by: Abhijeet Dharmapurikar <adharmap@quicinc.com>
Change-Id: I33a5f37af7114a7bf13d6b6706c4eca1340b5e41
(cherry picked from commit 32d12f613584053674ed6064a98aa2515aece9a0)
The subarchitecture field in the fpsid register is 7 bits wide.
The topmost bit is used to designate that the subarchitecture
designer is not ARM.
This change has the side effect of causing VFP implementations
other than ARM to be reported as VFPv3 with common VFP subarch
v3. Before this change it would be reported as VFPv1 with
an implementation defined subarchitecture.
CRs-Fixed: 268685
Change-Id: If304d284e2a104202b617ede86942bc89de0fb45
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
The gic_set_irq_secure function can be called from drivers
that are also compiled for targets which use an interrupt
controller other than GIC.
Add empty stub for this function to prevent compilation errors.
Change-Id: Ie3ab3a704b238751cd0dadf800d7e9b90ad257e7
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
(cherry picked from commit 4a771c59914d20b8fe234ceac2129be017052178)
Conflicts:
arch/arm/include/asm/hardware/gic.h
Most of the readl/writel macros for logging to the RTB
very similar. Create a dedicated macro to use for all of them
to make the code more readable and easier to maintain.
Change-Id: I6d8e7bc6bde7de6ad6cb53107362512d083b7423
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
(cherry picked from commit 9fba2a57b6f9f7d616bc0cb0aa41613240269f90)
Log readl/writel accesses in the small uncached buffer.
readl/writel are typically used for reading from memory
mapped registers, which can cause hangs if accessed
unclocked. Log this information in a buffer to aid in
debugging.
Change-Id: Id72da6b028a3faf5d0d8e069e14d90e4671e3564
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
(cherry picked from commit 0f9c7767132eed7f8a701f5281866aafa659632f)
Conflicts:
arch/arm/include/asm/io.h
arch/arm/mach-msm/include/mach/msm_rtb.h
arch/arm/mach-msm/include/mach/uncompress.h
Some CPUs perform speculative fetches. This may occur while a region of
memory is being written via DMA, so that region must be invalidated when
it is brought under CPU control after the DMA transaction finishes,
assuming the DMA was either bidirectional or from the device.
Signed-off-by: Dima Zavin <dima@android.com>
(cherry picked from commit fe79fc554afbfaa2652542129fb7380f4f7c4934)
Conflicts:
arch/arm/include/asm/dma-mapping.h
Change-Id: Id2a66fe567066a9301859b897d540885667253e6
For smp, barriers are required when a mutex lock is acquired or
released. Mutex slowpath routines already contain the necessary
barriers.
Change-Id: I774fc6e7bd5b1db9a0f51dee456b71c569cd512e
Signed-off-by: Brent DeGraaf <bdegraaf@codeaurora.org>
(cherry picked from commit 62c6b43d05a6aab278eb7d5d0030bd731b7684ea)
bank_pfn_end macro overflows when physical memory space
configuration ends at 0xFFFFFFFF.
The macro adds start and size together before converting
to a page frame number. Change the macro to convert start
and size first and then add them together.
Change-Id: If091fd860e6cc94f2221164bd79bf34415819e66
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
(cherry picked from commit b40b91eb8101b996f6dca5ccfee91b1949aa27e6)
The ARM generic timer now supports DT routines to parse the
device tree and populate its members, so remove this from
the board file and invoke the DT routine exposed from the
ARM generic timer.
Change-Id: Id383aff8f5f2c8fdb541f1df72242f8938229784
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit 2f27a173d075e9f5d6fa6c6705e56a6d101da024)
Conflicts:
arch/arm/boot/dts/msmcopper.dts
arch/arm/mach-msm/board-dt.c
Moving code which modifies the GIC registers. As there is no global
lock in gic code, moving the code out.
Change-Id: I85a2bd580dbeefc942a3307f3c0cad8b1da509b7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
(cherry picked from commit bc9248ab6fd94f9f5f2a818e7d8b67645b4310cb)
Conflicts:
arch/arm/common/gic.c
arch/arm/mach-msm/mpm-8625.c
arch/arm/mach-msm/platsmp-8625.c
Configure the GIC to run in secure mode and handle
secure as well as non-secure interrupts. This patch
adds an API to configure an IRQ as a secure IRQ so that
it can be treated as an FIQ in the secure mode.
Change-Id: Ic3321e76c95a4c10d6287ba418e84623e7004cb1
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit 26e44869e1e730ec7434e899dfd5857530b63415)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/gic.h
While in suspend state, the system should not wake up due to triggering
of a non wakeup interrupt. Implement suspend and resume functions to be
called from power management code to switch enabled interrupts between
wakeup set or normal set.
Change-Id: Iaceae286707460eadc5f05c0baef72b43c942777
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
(cherry picked from commit 3f2f06c6205445266aabdb9c843da70a4dd5d22f)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/gic.h
Some kernel code needs to check for and clear specific pending
interrupt explicitly. The polling and clearing may happen in
contexts where interrupts are masked off at the cpu level.
Change-Id: Icba9bb2f05e9fc61dd48c4174c4d276ab20b4244
Signed-off-by: Ai Li <aili@codeaurora.org>
(cherry picked from commit 20b3c0ee6e4852af8c52fb5f98188530760c8c74)
Conflicts:
arch/arm/include/asm/hardware/gic.h
Add support for the A15 generic timer and clocksource.
As the timer generates interrupts on a different PPI depending
on the execution mode (normal or secure), it is possible to
register two different PPIs.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Conflicts:
[Integrate to the recent patch which has changes to
local timer registration mechanism.
This fixes the crash seen during hotplug operations
where after a secondary CPU is brought back online,
the clock event device setup was happening as part
of the online notification mechanism which was too
late. With this change in the local timer mechanims,
the clock event device is now setup as part of the
secondary CPU boot initialization making it available
early enough for use.
Update the board file with the appropriate changes in
the argument for timer registration.]
arch/arm/Kconfig
arch/arm/include/asm/arch_timer.h
arch/arm/kernel/arch_timer.c
arch/arm/kernel/smp.c
Change-Id: I0bc80097c145fb2aac2150db0c5dff3c5e215a58
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit df590ccd9d8210cc3e059671efad06dab7e70d4c)
Change-Id: Iedac55e097b8d983c42799b98f2d11f7b1a95f04
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
The commit 292b293 creates the MSM boot failures, so squash
the commit 28af690 with it to avoid such failures. The commit ddd847
and 0c1991 are required to keep the watchdog and Copper targets working.
commit 292b293cee
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Wed Jul 20 16:24:14 2011 +0100
ARM: gic: consolidate PPI handling
PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).
Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.
This also allows the removal of some duplicated code.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit 28af690a28
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Fri Jul 22 12:52:37 2011 +0100
ARM: gic, local timers: use the request_percpu_irq() interface
This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).
PPIs are now useable for more than just the local timers.
Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).
Cc: David Brown <davidb@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit ddd8478d68f8cf75ee9771667c0cbe2a9d1caeb9
Author: Trilok Soni <tsoni@codeaurora.org>
Date: Tue Dec 6 00:56:01 2011 +0530
msm: watchdog: Use request_percpu_irq() interface
Change-Id: I7c319344f6a7f7a7c70682ac87f5c385e56d130c
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
commit 0c19915e092214a4c17a9920c4c1f3d78610217d
Author: Sathish Ambley <sambley@codeaurora.org>
Date: Fri Dec 9 17:07:37 2011 +0530
arm: arch_timer: Use request_percpu_irq() API
Change-Id: Iee9b218d538f315cd884a47d95bcc0dcc49b0fe1
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
Change-Id: I7bbba706b1f2e55814be5891ed76063725c2bfb1
Signed-off-by: Ravi Kumar <kumarrav@codeaurora.org>
[tsoni@codeaurora.org: MSM specific fixes]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
(cherry picked from commit eecb28c59054b1b9d8b9f410a903f87c8eb1ac48)
Conflicts:
arch/arm/common/gic.c
arch/arm/include/asm/hardware/entry-macro-gic.S
arch/arm/include/asm/localtimer.h
arch/arm/include/asm/smp.h
arch/arm/include/asm/smp_twd.h
arch/arm/kernel/smp.c
arch/arm/kernel/smp_twd.c
arch/arm/mach-exynos4/include/mach/entry-macro.S
arch/arm/mach-exynos4/mct.c
arch/arm/mach-msm/board-8064.c
arch/arm/mach-msm/board-8960.c
arch/arm/mach-msm/board-copper.c
arch/arm/mach-msm/board-dt.c
arch/arm/mach-msm/devices-9615.c
arch/arm/mach-msm/devices-msm8x60.c
arch/arm/mach-msm/include/mach/entry-macro-qgic.S
arch/arm/mach-msm/msm_watchdog.c
arch/arm/mach-msm/timer.c
arch/arm/mach-omap2/include/mach/entry-macro.S
L2 cache settings for improving memory performance on msm8625.
To improve write bandwidth, L2 is forced to No-Write-Allocate
through L2_AUX_CTRL(Enable bit 23).
To improve read bandwidth, Prefech offset of 3(Bit 0-4)and
Double line fill(Bit 23, 30)are enabled through L2_PREFETCH_CTRL.
Change-Id: Ia05cc41f8dee65486af9b0b7269b7f5763b5a988
Signed-off-by: Prachee Ramsinghani <pracheer@codeaurora.org>
(cherry picked from commit 86b1f6566dedc2df8fa98808709bd003d437b6ff)
Conflicts:
arch/arm/mach-msm/devices-msm7x27a.c
This reverts commit a022290fe5165ffe4973355cb76556ce8c629d70.
Save the contents of the L2CC registers in l2x0_init itself as
they are not modified later.
CRs-Fixed: 356696
Change-Id: I05ec3bcce8d1e2f941a9ecbaae8c6598f52831c5
Signed-off-by: Taniya Das <tdas@codeaurora.org>
(cherry picked from commit 38a8c6e63b1478cc520c795e07cd1b6370901d06)
Conflicts:
arch/arm/include/asm/hardware/cache-l2x0.h
arch/arm/mach-msm/pm-8x60.c
arch/arm/mach-msm/pm2.c
arch/arm/mm/cache-l2x0.c
Adds a function to encapsulate the locking, removal of write-protection,
word write, cache flush and invalidate and restoration
of write protection. This is a convenience function for callers
needing to update a word in kernel text space.
Change-Id: I9832f0ff659ddc62c55819af5318c94b70f5c11c
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
(cherry picked from commit 32942757bdfb3c67af2cd9c30427adf7d722f7c8)
STRICT_MEMORY_RWX write-protects the kernel text section. This
is a problem for tools such as kprobes which need write access
to kernel text space.
This patch introduces a function to temporarily make part of the
kernel text space writeable and another to restore the original state.
They can be called by code which is intentionally writing to
this space, while still leaving the kernel protected from
unintentional writes at other times.
Change-Id: I879009c41771198852952e5e7c3b4d1368f12d5f
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
(cherry picked from commit f06ab97f06fe6e8b3141434695b235e673f5ae37)
Conflicts:
arch/arm/mm/mmu.c
If CONFIG_STRICT_MEMORY_RWX is set, make kernel text RX,
kernel data/stack RW and rodata RO so that writing
on kernel text, executing kernel data or stack, or
writing on or executing read-only data is prohibited.
Change-Id: Ib2242c20dabddb63ef3f5655d5794fe418cb6287
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>
(cherry picked from commit 5a5305e90d4204fdf0586fbbd9a19b92181e74ea)
Conflicts:
arch/arm/mm/mmu.c
This patch implements CONFIG_DEBUG_RODATA, allowing
the kernel text section to be marked read-only in
order to catch bugs that write over the kernel. This
requires mapping the kernel code, plus up to 4MB, using
pages instead of sections, which can increase TLB
pressure.
The kernel is normally mapped using 1MB section entries
in the first level page table, and the first level page
table is copied into every mm. This prevents marking
the kernel text read-only, because the 1MB section
entries are too large granularity to separate the init
section, which is reused as read-write memory after
init, and the kernel text section. Also, the top level
page table for every process would need to be updated,
which is not possible to do safely and efficiently on SMP.
To solve both problems, allow alloc_init_pte to overwrite
an existing section entry with a fully-populated second
level page table. When CONFIG_DEBUG_RODATA is set, all
the section entries that overlap the kernel text section
will be replaced with page mappings. The kernel always
uses a pair of 2MB-aligned 1MB sections, so up to 2MB
of memory before and after the kernel may end up page
mapped.
When the top level page tables are copied into each
process the second level page tables are not copied,
leaving a single second level page table that will
affect all processes on all cpus. To mark a page
read-only, the second level page table is located using
the pointer in the first level page table for the
current process, and the supervisor RO bit is flipped
atomically. Once all pages have been updated, all TLBs
are flushed to ensure the changes are visible on all
cpus.
If CONFIG_DEBUG_RODATA is not set, the kernel will be
mapped using the normal 1MB section entries.
Change-Id: I94fae337f882c2e123abaf8e1082c29cd5d483c6
Signed-off-by: Colin Cross <ccross@android.com>
(cherry picked from commit e5e483d133)
Conflicts:
arch/arm/mm/mmu.c
On ScorpionMP targets, the TLBIMVAIS instruction can, under
certain conditions, result in a faulty ASID broadcast,
necessitating the use of the TLBIMVAAIS instruction
instead.
Change-Id: Ica7a95a21a816424c86c59a0585c495a02aa0cac
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
(cherry picked from commit 097881f039742ccd4f930c6849cb6d765a6af7f3)
Conflicts:
arch/arm/include/asm/tlbflush.h
For cases with SPARSE_IRQ enabled, irqs preallocated with
arch_probe_nr_irqs() are already marked as allocated in the
allocated_irqs bitmap. As a consequence, irq chip drivers that
allocate irqs will feel one of two behaviors:
1. An allocation will succeed with the starting irq_base one
more than the preallocated irqs. This will thus waste the
preceeding interrupt resources that were preallocated, unless a
legacy chip driver happens to assume ownership of these by some
platform definition. The GIC driver is a typical primary chip
driver, and abides to the allocation APIs. So this can be a
problem in many trivial usecases.
2. An allocation will fail with < 0. This can also happen in the
GIC driver, which interprets this value as meaning the irq_descs
are already preallocated. But in Device Tree configurations, the
fallback irq_base is -1. This results in an invalid irq_base
value.
Looking forward, we are moving towards a world where preallocation
of irqs is no longer necessary. irq_domain is scoped to handle all
irq_desc allocations in the future. Thus, we should support
configurations where the platform wants to preallocate no irqs.
One easy way to achieve this is to allow for
machine_desc->nr_irqs < 0, which indicates not to preallocate any
interrupts.
Change-Id: Ie793932c58de72c1b91b6e039b77a8e5d64ecc75
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
(cherry picked from commit 0bb2b56f7048b2f85be6784eaa8e4a5f0fa8688d)
The MSM perf_event code wants to know which cpu the event is for.
Pass this during the enable call.
Change-Id: I1151ac9361c3050ecb40455c017368ead25c6fdc
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Contains the squash of 2 patches
commit 39242ba4253db8a1bebc37526d1fddc74889c200
Author: Ashwin Chaugule <ashwinc@codeaurora.org>
AuthorDate: Mon Oct 29 16:30:05 2012 -0400
Commit: Ashwin Chaugule <ashwinc@codeaurora.org>
CommitDate: Thu Nov 8 14:37:56 2012 -0500
Perf: Let platforms decide IRQ request methods.
This is in preparation for adding support for the unicore A5
and dualcore A5, both of which have the same MIDR value.
Instead of adding extra parsing to the ARM generic perf_event
file,
this patch moves it to the 'mach' directory where targets
types
can be detected in an implementation specific manner.
The default behavior is maintained for all other ARM
targets.
commit 4afdedccc111b9b60b66d156cce43988c4cbe7f0
Author: Ashwin Chaugule <ashwinc@codeaurora.org>
AuthorDate: Tue Jan 17 13:23:50 2012 -0500
Commit: Ashwin Chaugule <ashwinc@codeaurora.org>
CommitDate: Fri Feb 3 16:27:51 2012 -0500
Perf: Switch to per-cpu IRQ framework
The L1CC PMU interrupt is a PPI, so
use the per-CPU
request, free, enable, disable
API.
Change-Id: I0d2cd9c5eac5b020f4d1b640cb9c397afe0ea2ad
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
This commit enables Oprofile on Scorpion and Scorpion-MP based
chips. It only adds the generic arm performance monitors.
It also adds necessary support to all the underlying perf
components.
Change-Id: I525f35097595b3c4c9c94f9bbb47e4209edf5ddb
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
(cherry picked from commit b014badff96a5915218d8e7e0d99906976264a58)
Conflicts:
arch/arm/include/asm/perf_event.h
arch/arm/kernel/perf_event.c
arch/arm/mach-msm/Makefile
This patch prevents memory hotplug from marking pages of the memmap that
only reference holes in the physical address space as private. Some
architectures (including ARM) attempt to free these unneeded parts of the
memmap, and attempting to free a private page will throw bad_page warnings
and tie up the memory indefinitely.
This patch also allows early_pfn_valid to be architecture specific and
defines it for ARM. The definition for ARM takes into account memory banks
and the holes in physical memory.
CRs-Fixed: 247010
Change-Id: Iad88d427b1b923a808b026c22d2899fa0483cb9e
Signed-off-by: jesset@codeaurora.org
(cherry picked from commit 0b610c773ad6281a3d217fbbe894b2476e9e71dd)
Conflicts:
arch/arm/mm/init.c
udelay() can be incorrect on SMP machines that scale their CPU
frequencies independently of one another (as pointed out here
http://article.gmane.org/gmane.linux.kernel/977567). The delay
loop can either be too fast or too slow depending on which CPU the
loops_per_jiffy counter is calibrated on and which CPU the delay
loop is running on. udelay() can also be incorrect if the
CPU frequency switches during the __delay() loop, causing the loop
to either terminate too early, or too late.
We'd rather not fix udelay() by forcing it to run on one CPU or
take the penalty of a rather large loops_per_jiffy being used in
udelay() when the CPU is actually running slower. Instead we
solve the problem by making __delay() into a timer based loop
which should be unaffected by CPU frequency scaling. Therefore,
implement a timer based __delay() loop which can be used in place
of the current register based __delay() if a machine so chooses.
The kernel is already prepared for a timer based approach
(evident by the read_current_timer() function). If an arch
implements read_current_timer(), calibrate_delay() will use a
timer based function, calibrate_delay_direct(), to calculate
loops_per_jiffy (in which case loops_per_jiffy should really be
renamed to timer_ticks_per_jiffy). Since the loops_per_jiffy will
be based on timer ticks, __delay() should be implemented as a
loop around read_current_timer().
Doing this makes the expensive loops_per_jiffy calculation go
away (saving ~150ms on boot time on my machine) and fixes
udelay() by making it safe in the face of independently scaling
CPUs. The only prerequisite is that read_current_timer() is
monotonically increasing across calls (and doesn't overflow
within ~2000us).
There is a downside to this approach though. BogoMIPS is no
longer "accurate" in that it reflects the BogoMIPS of the timer
and not the CPU. On most SoC's the timer isn't running anywhere
near as fast as the CPU so BogoMIPS will be ridiculously low (my
timer runs at 4.8 MHz and thus my BogoMIPS is 9.6 compared to my
CPU's 800). This shouldn't be too much of a concern though since
BogoMIPS are bogus anyway (hence the name).
This loop is pretty much a copy of AVR's version made more generic.
Change-Id: I1a80718d93a4821ea55bde99ff0f9cd1c19990ae
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Saravana Kannan <skannan@codeaurora.org>
(cherry picked from commit 976eafa8b18252876e15f861944acf693b07ce7e)
Some machines want to implement their own __delay() routine based
on fixed timers. Expose functionality to set the __delay()
routine at runtime. This should allow two machines with different
__delay() routines to happily co-exist within the same kernel
with minimal overhead.
Russell expressed concern that using a timer based __delay()
would cause problems where an iomapped device isn't mapped in
before a delay call was made (see
http://article.gmane.org/gmane.linux.ports.arm.kernel/78543 for
more info). We can sidestep that issue with this approach since
the __delay() routine _should_ only be pointed to a timer based
delay once the timer has been properly mapped. Up until that
point __delay() and udelay() will use delay_loop() which is
always safe to call.
This patch is inspired by x86's delay.c
Change-Id: I1ed80eef1eed6d6df881f93f4515de778ad60f67
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Saravana Kannan <skannan@codeaurora.org>
(cherry picked from commit bc0ef8ab167272890f1aab62928b04a9aeb87ce9)
In the next patch we're going to allow machines to override the
__delay() implementation at runtime so they can implement a timer
based __delay() routine. It's easier to do this using C, so lets
write udelay and friends in C.
We lose the #if 0 code, which according to Russell is used "to
make the delay loop more stable and predictable on older CPUs"
(see http://article.gmane.org/gmane.linux.kernel/888867 for more
info). We shouldn't be too worried though, since the next patch
adds functionality to allow a machine to set the __delay() loop
themselves, therefore allowing machines to resurrect the
commented out code if they need it.
bloat-o-meter shows an increase of 12 bytes. Further inspection
of the assembly shows GCC copying the loops_per_jiffy pointer and
the magic HZ value to the ends of __const_udelay() and _delay()
thus contributing an extra 4 and 8 bytes of data to each
function. These two values weren't taken into account in the
delay.S version since they weren't part of the function in nm's
eyes. This means we only really gained an extra 4 bytes due to
GCC's decision to duplicate the loops_per_jiffy pointer in
__const_udelay.
$ scripts/bloat-o-meter vmlinux.orig vmlinux.new
add/remove: 0/0 grow/shrink: 2/0 up/down: 12/0 (12)
function old new delta
__udelay 48 56 +8
__const_udelay 40 44 +4
Change-Id: Ibfaab52d0f5e09471571be082232db04726d5532
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Saravana Kannan <skannan@codeaurora.org>
(cherry picked from commit 8d5868d8205d10a0a8e423f53e9cc9bb3e9d1a34)
Conflicts:
arch/arm/kernel/armksyms.c
arch/arm/lib/delay.S
Add support for the A15 generic timer and clocksource.
As the timer generates interrupts on a different PPI depending
on the execution mode (normal or secure), it is possible to
register two different PPIs.
Change-Id: Ibaddc7f174bc168cef579b66ab06b966878ae155
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
(cherry picked from commit f5b3b2b2a44e813fbbe1799965a8879429f59329)
Conflicts:
arch/arm/kernel/Makefile
KSAPI records performance statistics for Snapdragon linux platform.
It uses the /proc FS as a means to exchange configuration data and counter
statistics. It can monitor the counter statistics for Scorpion processor
supported hardware performance counters on a per thread basis or AXI
counters on an overall system basis.
Change-Id: Iaaf51db68dbd6d5a55fe34328d041bde5015230d
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
(cherry picked from commit 4e6bb52bcee479762f283b4a44a1bdd4f1277aa2)
Conflicts:
arch/arm/Kconfig
A driver using fiq functions should be usable on targets
with or without CONFIG_FIQ enabled. Instead of making code
dependent on #ifdef CONFIG_FIQ, add empty stubs for the fiq
functions.
Change-Id: Ie8b1905ba53664d99bd707be3c83291c97eb1066
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
(cherry picked from commit eb81fb3bdea411fed5c26400f9769bad7fb0743f)
Commit 'ad3b6993' converted ARM smp_cross_call() to take IPI number
as a parameter to handle more event than SGI and do_IPI was suppose
to recover SGI number. But the do_IPI doesn't consider it and it's
getting detected as 'Unknown IPI message 0x1' with ipi numbers are
moved to starts from 'IPI_TIMER=2"
There can be 16 different SGI but only SGI1 is used as IPI so
only that one is handled in do_IPI as IPI_CPU_START.
Added IPI_CPU_START because it wasn't used and thought it's
appropriate. Not sure whether its the right one.
Change-Id: I4dbe7c489d9611fbbb4036c15ac247659fde4119
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
[johlstei@codeaurora.org: fixed bounds check error]
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
(cherry picked from commit 7f685e51169149a877cb3100670567fb03c969f5)
